Texas Instruments AFE79 Series Programming & User Manual page 417

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2.5.91 Register 8Fh (offset = 8Fh) [reset = 1h]
7 6
LINK1_SCR 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-7 LINK1_SCR
6-5 0
4-0 LINK1_ILA_L_M1
2.5.92 Register 90h (offset = 90h) [reset = 1h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-0 LINK1_ILA_F_M1
2.5.93 Register 91h (offset = 91h) [reset = 0h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-0 LINK1_ILA_K_M1
SBAU337 – May 2020
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Figure 2-587. Register 8Fh
5 4
0
R/W-0h
Table 2-592. Register 8F Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 1h
Figure 2-588. Register 90h
5 4
LINK1_ILA_F_M1
R/W-1h
Table 2-593. Register 90 Field Descriptions
Type Reset
R/W 1h
Figure 2-589. Register 91h
5 4
LINK1_ILA_K_M1
R/W-0h
Table 2-594. Register 91 Field Descriptions
Type Reset
R/W 0h
Copyright © 2020, Texas Instruments Incorporated
3 2
LINK1_ILA_L_M1
R/W-1h
Description
JESD link config for STX2/6
For JESD-B/C
When 1, scrambler (present between transport layer and link
layer) is enabled
1+x^14+x^15
0 : scrambler disabled
1 : scrambler enabled
Must read or write 0
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else L derived from LMFS is used.
3 2
Description
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else F derived from LMFS is used.
3 2
Description
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else K derived from link1_k_m1 reg
Serial Interface Register Maps
ADC JESD Register Map
1 0
1 0
1 0
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