Texas Instruments AFE79 Series Programming & User Manual
  1. Manuals
  2. Brands
  3. Texas Instruments Manuals
  4. Control Unit
  5. AFE79 Series
  6. Programming & user manual

Texas Instruments AFE79 Series Programming & User Manual

Hide thumbs Also See for AFE79 Series:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
Table of Contents

Advertisement

Quick Links

AFE79xx Programming User Guide
Technical Reference Manual
Literature Number: SBAU337
May 2020

Advertisement

Table of Contents
loading

Related Manuals for Texas Instruments AFE79 Series

Summary of Contents for Texas Instruments AFE79 Series

  • Page 1 AFE79xx Programming User Guide Technical Reference Manual Literature Number: SBAU337 May 2020...

  • Page 2: Table Of Contents

    Register 4h (offset = 4h) [reset = 78h] ................2.1.6 Register 5h (offset = 5h) [reset = 0h] ................ 2.1.7 Register 6h (offset = 6h) [reset = 11h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 3 2.3.15 Register 31h (offset = 31h) [reset = 88h] ..............2.3.16 Register 32h (offset = 32h) [reset = 88h] ..............2.3.17 Register 33h (offset = 33h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 4 2.3.68 Register 7Ch (offset = 7Ch) [reset = C3h] ..............2.3.69 Register 7Dh (offset = 7Dh) [reset = 0h] ..............2.3.70 Register 7Eh (offset = 7Eh) [reset = 9h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 5 2.3.121 Register CCh (offset = CCh) [reset = 0h] ..............2.3.122 Register CDh (offset = CDh) [reset = 11h] ..............2.3.123 Register CEh (offset = CEh) [reset = 22h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 6 2.3.174 Register 193h (offset = 193h) [reset = 0h] ..............2.3.175 Register 194h (offset = 194h) [reset = 0h] ..............2.3.176 Register 195h (offset = 195h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 7 2.4.38 Register 45h (offset = 45h) [reset = 0h] ..............2.4.39 Register 46h (offset = 46h) [reset = 0h] ..............2.4.40 Register 47h (offset = 47h) [reset = 1h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 8 2.4.91 Register 7Ah (offset = 7Ah) [reset = 0h] ..............2.4.92 Register 7Bh (offset = 7Bh) [reset = 0h] ..............2.4.93 Register 7Ch (offset = 7Ch) [reset = 3h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 9 2.4.144 Register B8h (offset = B8h) [reset = 0h] ..............2.4.145 Register B9h (offset = B9h) [reset = 0h] ..............2.4.146 Register BAh (offset = BAh) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 10 2.4.197 Register FEh (offset = FEh) [reset = 0h] ..............2.4.198 Register FFh (offset = FFh) [reset = 0h] ..............2.4.199 Register 100h (offset = 100h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 11 2.4.250 Register 13Eh (offset = 13Eh) [reset = 0h] ..............2.4.251 Register 13Fh (offset = 13Fh) [reset = 0h] ..............2.4.252 Register 140h (offset = 140h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 12 2.5.35 Register 49h (offset = 49h) [reset = 0h] ..............2.5.36 Register 4Ah (offset = 4Ah) [reset = 1h] ..............2.5.37 Register 4Bh (offset = 4Bh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 13 2.5.88 Register 8Ch (offset = 8Ch) [reset = 0h] ..............2.5.89 Register 8Dh (offset = 8Dh) [reset = 0h] ..............2.5.90 Register 8Eh (offset = 8Eh) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 14 2.5.141 Register CDh (offset = CDh) [reset = 0h] ..............2.5.142 Register CEh (offset = CEh) [reset = 0h] ..............2.5.143 Register CFh (offset = CFh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 15 2.5.194 Register 114h (offset = 114h) [reset = 0h] ..............2.5.195 Register 115h (offset = 115h) [reset = 0h] ..............2.5.196 Register 116h (offset = 116h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 16 2.6.28 Register 4025h (offset = 4025h) [reset = 0h] ............... 2.6.29 Register 4038h (offset = 4038h) [reset = 0h] ............... 2.6.30 Register 4039h (offset = 4039h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 17 2.6.81 Register 4141h (offset = 4141h) [reset = 40h] ............. 2.6.82 Register 4142h (offset = 4142h) [reset = AAh] ............. 2.6.83 Register 4143h (offset = 4143h) [reset = AAh] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 18 2.6.134 Register 49EAh (offset = 49EAh) [reset = B4h] ............2.6.135 Register 49EBh (offset = 49EBh) [reset = 14h] ............2.6.136 Register 49ECh (offset = 49ECh) [reset = 40h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 19 2.6.187 Register 7E0Ch (offset = 7E0Ch) [reset = 0h] ............2.6.188 Register 7E0Dh (offset = 7E0Dh) [reset = 0h] ............. 2.6.189 Register 7E0Eh (offset = 7E0Eh) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 20 2.8.21 Register B4h (offset = B4h) [reset = 0h] ..............2.8.22 Register B5h (offset = B5h) [reset = 0h] ..............2.8.23 Register B6h (offset = B6h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 21 2.8.74 Register E9h (offset = E9h) [reset = 0h] ..............2.8.75 Register EAh (offset = EAh) [reset = 0h] ..............2.8.76 Register EBh (offset = EBh) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 22 2.8.127 Register 11Eh (offset = 11Eh) [reset = 0h] ..............2.8.128 Register 11Fh (offset = 11Fh) [reset = 0h] ..............2.8.129 Register 120h (offset = 120h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 23 2.10.3 Register 89h (offset = 89h) [reset = 0h] ..............2.10.4 Register 8Ah (offset = 8Ah) [reset = 0h] ..............2.10.5 Register 8Ch (offset = 8Ch) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 24 2.10.56 Register 1CCh (offset = 1CCh) [reset = 0h] ..............2.10.57 Register 1D0h (offset = 1D0h) [reset = 0h] ..............2.10.58 Register 1D4h (offset = 1D4h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 25 2.12.10 Register 65h (offset = 65h) [reset = 0h] ..............2.12.11 Register 66h (offset = 66h) [reset = 0h] ..............2.12.12 Register 68h (offset = 68h) [reset = 4h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 26 2.12.63 Register 314h (offset = 314h) [reset = 2h] ..............2.12.64 Register 31Ch (offset = 31Ch) [reset = 0h] ..............2.12.65 Register 31Eh (offset = 31Eh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 27 2.12.116 Register 51Dh (offset = 51Dh) [reset = 0h] ............... 2.12.117 Register 51Eh (offset = 51Eh) [reset = 0h] ............... 2.12.118 Register 520h (offset = 520h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 28 2.12.169 Register 570h (offset = 570h) [reset = 0h] ............... 2.12.170 Register 571h (offset = 571h) [reset = 0h] ............... 2.12.171 Register 574h (offset = 574h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 29 2.13.12 Register 70h (offset = 70h) [reset = 1h] ..............2.13.13 Register A0h (offset = A0h) [reset = 0h] ..............2.13.14 Register A1h (offset = A1h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 30 2.13.65 Register 247h (offset = 247h) [reset = 2Dh] ..............2.13.66 Register 288h (offset = 288h) [reset = 5h] ..............2.13.67 Register 400h (offset = 400h) [reset = Ah] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 31 2.13.118 Register 45Dh (offset = 45Dh) [reset = 0h] ............... 2.13.119 Register 45Eh (offset = 45Eh) [reset = 8h] ............... 2.13.120 Register 460h (offset = 460h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 32 2.13.171 Register 4BFh (offset = 4BFh) [reset = 0h] ............... 2.13.172 Register 4C0h (offset = 4C0h) [reset = 0h] ............... 2.13.173 Register 4C1h (offset = 4C1h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 33 2.13.224 Register 4F4h (offset = 4F4h) [reset = 0h] ............... 2.13.225 Register 4F5h (offset = 4F5h) [reset = 0h] ............... 2.13.226 Register 4F6h (offset = 4F6h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 34 2.13.277 Register 529h (offset = 529h) [reset = 0h] ............... 2.13.278 Register 52Ah (offset = 52Ah) [reset = 0h] ............... 2.13.279 Register 52Bh (offset = 52Bh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 35 2.13.330 Register 55Eh (offset = 55Eh) [reset = 0h] ............... 2.13.331 Register 55Fh (offset = 55Fh) [reset = 0h] ............... 2.13.332 Register 560h (offset = 560h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 36 2.13.383 Register 593h (offset = 593h) [reset = 0h] ............... 2.13.384 Register 594h (offset = 594h) [reset = 0h] ............... 2.13.385 Register 595h (offset = 595h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 37 2.13.436 Register 5E4h (offset = 5E4h) [reset = 0h] ............... 2.13.437 Register 5E5h (offset = 5E5h) [reset = 0h] ............... 2.13.438 Register 5E6h (offset = 5E6h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 38 2.14.17 Register A7h (offset = A7h) [reset = 0h] ..............2.14.18 Register A8h (offset = A8h) [reset = 0h] ..............2.14.19 Register A9h (offset = A9h) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 39 2.14.70 Register 40Ah (offset = 40Ah) [reset = 6h] ..............2.14.71 Register 40Bh (offset = 40Bh) [reset = 2h] ..............2.14.72 Register 40Ch (offset = 40Ch) [reset = 2h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 40 2.14.123 Register 49Ch (offset = 49Ch) [reset = 0h] ............... 2.14.124 Register 49Dh (offset = 49Dh) [reset = 0h] ............... 2.14.125 Register 49Eh (offset = 49Eh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 41 2.14.176 Register 4D7h (offset = 4D7h) [reset = 0h] ............... 2.14.177 Register 4D8h (offset = 4D8h) [reset = 0h] ............... 2.14.178 Register 4D9h (offset = 4D9h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 42 2.14.229 Register 54Ch (offset = 54Ch) [reset = 0h] ............... 2.14.230 Register 54Dh (offset = 54Dh) [reset = 0h] ............... 2.14.231 Register 54Eh (offset = 54Eh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 43 2.14.282 Register 5D0h (offset = 5D0h) [reset = 0h] ............... 2.14.283 Register 5D1h (offset = 5D1h) [reset = 0h] ............... 2.14.284 Register 5D4h (offset = 5D4h) [reset = 0h] SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 44 2.15.10 Register 8Dh (offset = 8Dh) [reset = 0h] ..............2.15.11 Register 8Eh (offset = 8Eh) [reset = 0h] ..............2.15.12 Register 8Fh (offset = 8Fh) [reset = 0h] Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 45 2.16.6 Register 206h (offset = 206h) [reset = 0h] 1000 ..............2.16.7 Register 208h (offset = 208h) [reset = 1h] 1000 ..............2.16.8 Register 209h (offset = 209h) [reset = 2h] 1000 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 46 2.16.59 Register 24Dh (offset = 24Dh) [reset = 2h] 1015 ............... 2.16.60 Register 24Eh (offset = 24Eh) [reset = 0h] 1015 ............... 2.16.61 Register 250h (offset = 250h) [reset = 1h] 1015 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 47 2.16.112 Register 294h (offset = 294h) [reset = 1h] 1030 .............. 2.16.113 Register 295h (offset = 295h) [reset = 2h] 1030 .............. 2.16.114 Register 296h (offset = 296h) [reset = 0h] 1030 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 48 2.16.165 Register 2DAh (offset = 2DAh) [reset = 0h] 1045 ............2.16.166 Register 2DCh (offset = 2DCh) [reset = 1h] 1045 ............2.16.167 Register 2DDh (offset = 2DDh) [reset = 2h] 1046 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 49 2.16.218 Register 321h (offset = 321h) [reset = 2h] 1060 .............. 2.16.219 Register 322h (offset = 322h) [reset = 0h] 1060 .............. 2.16.220 Register 324h (offset = 324h) [reset = 1h] 1061 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 50 2.16.271 Register 43Ch (offset = 43Ch) [reset = 1h] 1079 .............. 2.16.272 Register 43Fh (offset = 43Fh) [reset = 0h] 1079 .............. 2.16.273 Register 440h (offset = 440h) [reset = 1h] 1079 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 51 2.16.324 Register 4A7h (offset = 4A7h) [reset = 0h] 1100 ............. 2.16.325 Register 4A8h (offset = 4A8h) [reset = 1h] 1100 ............. 2.16.326 Register 4ABh (offset = 4ABh) [reset = 0h] 1101 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 52 2.16.377 Register 510h (offset = 510h) [reset = 1h] 1121 .............. 2.16.378 Register 513h (offset = 513h) [reset = 0h] 1121 .............. 2.16.379 Register 514h (offset = 514h) [reset = 1h] 1122 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 53 2.16.430 Register 839h (offset = 839h) [reset = 2h] 1140 ............. 2.16.431 Register 83Ch (offset = 83Ch) [reset = 0h] 1141 ............. 2.16.432 Register 83Dh (offset = 83Dh) [reset = 2h] 1141 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 54 2.16.483 Register 8B4h (offset = 8B4h) [reset = 0h] 1158 ............. 2.16.484 Register 8B5h (offset = 8B5h) [reset = 2h] 1158 ............. 2.16.485 Register 8B8h (offset = 8B8h) [reset = 0h] 1159 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 55 2.16.536 Register A0Dh (offset = A0Dh) [reset = 2h] 1176 ............. 2.16.537 Register A10h (offset = A10h) [reset = 0h] 1176 ............. 2.16.538 Register A11h (offset = A11h) [reset = 2h] 1177 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 56 2.16.589 Register 108Dh (offset = 108Dh) [reset = 2h] 1194 ............2.16.590 Register 1090h (offset = 1090h) [reset = 0h] 1194 ............2.16.591 Register 1091h (offset = 1091h) [reset = 2h] 1194 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 57 2.16.642 Register 140Bh (offset = 140Bh) [reset = 0h] 1211 ............2.16.643 Register 140Ch (offset = 140Ch) [reset = 0h] 1211 ............2.16.644 Register 140Dh (offset = 140Dh) [reset = 0h] 1211 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 58 2.16.695 Register 17EEh (offset = 17EEh) [reset = 0h] 1228 ............2.16.696 Register 17EFh (offset = 17EFh) [reset = 0h] 1228 ............2.16.697 Register 17F0h (offset = 17F0h) [reset = 0h] 1229 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 59 2.16.748 Register 182Bh (offset = 182Bh) [reset = 0h] 1245 ............2.16.749 Register 182Ch (offset = 182Ch) [reset = 0h] 1245 ............2.16.750 Register 182Dh (offset = 182Dh) [reset = 0h] 1246 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 60 2.16.801 Register 1860h (offset = 1860h) [reset = 0h] 1262 ............2.16.802 Register 1861h (offset = 1861h) [reset = 0h] 1262 ............2.16.803 Register 1862h (offset = 1862h) [reset = 0h] 1262 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 61 2.16.810 Register 1886h (offset = 1886h) [reset = 0h] 1264 ............2.16.811 Register 1887h (offset = 1887h) [reset = 0h] 1264 ....................Appendix: SPI Interface 1266 SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 62 Contents SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 63: Revision History

    Revision History www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SBAU337 – May 2020 Contents Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 64 April 2020 Changed PLL Register Map section. Changed AFE79xx Macro Interface figure. Changed Fields within Macro Status Registers figure. Changed Macro Interface Categories table. May 2020 Revision History SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 65 REVISION NOTES Added Update TX Channel Frequency Set – Single Band section. Added TX TONE generator Configuration section. Added AGC External DVGA Configuration Macro section. SBAU337 – May 2020 Revision History Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 66: Preface

    This document describes the Macro Interface protocol, lists all the Macro commands (along with their functionality) and provides the SPI direct register maps. SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 67: Macro

    20 x 32b Large Data 1k x 32b Results Macro Result Registers Status Macro Status Register 2 x 32b 18 x 32b Figure 1-1. AFE79xx Macro Interface SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 68 AFE79xx microcontroller, which in turn executes the command. To reduce the time taken for Macro configuration, it is recommended that the SPI streaming (burst) mode be used to program the Macro operands. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 69 Operand 1 Operand 2 Operand 3 Opcode OPERAND_BA OPCODE_BA Burst Mode ++ Figure 1-3. SPI write sequence for initiating Macro Figure 1-4shows a simplified transaction diagram. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 70 SPI:DATA=OPCODE OPCODE SPI:ADDR=0xF0 Repeat till Addr STATUS_BA SPI:READ_DATA=? READ_DATA && READ_DATA 0x1 == 1 Read results Figure 1-4. Interaction between Host and AFE79xx – (Polling method) Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 71 2. Write calibration data one byte at a time (SPI streaming mode) 3. Activate SPI page for Customer registers 4. Write Macro Operands (SPI streaming mode) 5. Write Macro opcode in trigger register SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 72 SPI Page Change Operand 0 Operand 1 Opcode OPERAND_BA (Customer) OPCODE_BA Burst Mode ++ Figure 1-6. SPI write sequence for initiating Macro with large data transfer mode Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 73 Addr STATUS_BA SPI:READ_DATA=? READ_DATA && READ_DATA 0x1 == 1 Read results Figure 1-7. Interaction between Host and AFE79xx – Macro Interface large data transfer mode (Polling method) SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 74 SPI:READ_DATA=? Confirm READ_DATA READ_DATA && 0x1 == 1 Read results Figure 1-8. Interaction between Host and AFE79xx – initiating Macro with large data transfer (Interrupt method) Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 75 [Bit 3] MACRO_ERROR: Value of 1 means that the last macro issued to the device had an error. Each Macro execution normally goes through these three states. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 76 1.1.1.4.4 Macro Error Code Fields The two error code fields give further information on the cause of macro error. The interpretation of these error codes is specific to each macro. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 77: 1.1.2 Macro Interface Categories

    RX Interface rate: the data rate for the traffic receiver quadrature signal after the decimation stage. • FB Interface rate: the data rate for the feedback receiver quadrature signal after the decimation stage. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 78: List Of Macros

    0x63 AGC Dual LNA Time Crossings 0x65 AGC Customer RF Macro 0x66 AGC External LNA Gain Control Configuration Macro 0x67 AGC Gain Step Size Configuration Macro Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 79: 1.2.1 System Configuration

    Bit 1: 0 → 2TX Disabled, 1 → 2TX Enabled Bit 2: 0 → 3TX Disabled, 1 →3TX Enabled Bit 3: 0 → 4TX Disabled, 1 →4TX Enabled SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 80 3 → RESERVED Bit[5:4]: 0 → ADC1 is used for 1 → ADC2 is used for 2 → ADC3 is used for 3 → RESERVED Bit[7:6]: RESERVED Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 81 Table 1-7. Error Status Registers Interpretation Error Code 1 (16-bit) Bit[0]: ‘1’ → Invalid TDD/FDD mode argument Error Code 2 (32-bit) Not Used SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 82 For a given RX Channel ADC rate, only a specific subset of interface rates is supported. Table 1-10. Macro RX Interface Rate Configuration Opcode 0x29 Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 83 This macro specifies the interface rate(s) for FB channel(s). A total of 8 interface rates are supported as tabulated below. For a given FB Channel ADC rate, only a specific subset of interface rates is supported. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 84 For a given TX Channel DAC rate, only a specific subset of interface rates is supported. Table 1-14. Macro TX Interface Rate Configuration Opcode 0x2B Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 85 The supported rates are listed below. Note that the ratio of ADC rates of the 2 sides (RX12 and RX34) can only be 1:1, 1:2 or 2:1. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 86 RX channel, the ADC rate configured for both should be identical. Table 1-18. Macro FB ADC Rate configuration Opcode 0x2D Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 87 This macro specifies the Digital-to-Analog Converter (DAC) sampling rate(s) for the TX chain(s). The supported rates are tabulated below. Table 1-20. Macro TX DAC Rate configuration Opcode 0x2E Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 88 . Example for RX Channels it will be RX-ADC-RATE/2 ; for FB channels it will be FB-ADC-RATE/2 ; for TX channels it will be TX-DAC- RATE/2 Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 89 Bit 2: 1 → Channel Frequency value is applicable to 3TX Bit 3: 1 → Channel Frequency value is applicable to 4TX Bits 7:4 → RESERVED SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 90 Bit[3]: ‘1’ → Invalid second Frequency Value argument. Bit[4]: ‘1’ → Invalid third Frequency Value argument. Bit[5]: ‘1’ → Invalid fourth Frequency Value argument. Error Code 2 (32-bit) Not Used Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 91 RX Channel frequency for NCO 1, Band 2 in specified resolution. In case of 1-kHz resolution mode, value of up to RX- ADC-RATE is only allowed. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 92 RATE. Note that the Nyquist zone of the target channel-frequency should be specified through the RX-FB Nyquist Zone Configuration Macro. Table 1-28. Macro FB Channel frequency set Opcode 0x32 Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 93 FB- ADC-RATE is only allowed. Memory Not used 1.2.1.14.1 Error Reporting Table 1-29 lists the error conditions associated with this macro. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 94 Error Status Registers Interpretation Bit[0]: ‘1’ → Invalid Channel Validity argument. Error Code 1 (16-bit) Bit[1]: ‘1’ → Unsupported Nyquist zone. Error Code 2 (32-bit) Not Used Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 95 0x3E Operand Offset Length Value Functionality Results 0x00 TX Channel Select TX Channel Select 0x00 → 1TX 0x01 → 2TX 0x02 → 3TX 0x03 → 4TX SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 96 NCO channel frequency. This macro should be called only after calling the initial Tune System Macro. Table 1-36. Macro Update TX Channel Frequency Set – Single Band Opcode 0x37 Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 97 0x38 Operand Offset Length Value Functionality Results 0x00 RX Channel Select RX Channel Select 0x00 → 1RX 0x01 → 2RX 0x02 → 3RX 0x03 → 4RX SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 98 0x01 → 2FB 0x01 NCO Select 0x00 → Update NCO 1 0x01 → Update NCO 2 0x02 → Update NCO 3 0x03 → Update NCO 4 Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 99: 1.2.2 System Initialization

    Bit[1]: ‘1’ → Error in FB DDC Configuration More details will be in Error Code 2. Error Code 1 (16-bit) Bit[2]: ‘1’ → Error in TX DUC Configuration More details will be in Error Code 2. Bit[15:3]: ‘1’ → RESERVED. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 100 Error Status Registers Interpretation Error Code 1 (16-bit) 0 → NO_ERROR 1 → RESERVED 2 → PKT_CHECKSUM_FAILED: Checksum check on loaded packet failed >2 → RESERVED Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 101: 1.2.3 Factory Calibration

    3 → Continue RX Calibration 4 → Generate the Calibration Packet – Assumes that all required bands have been calibrated and the final calibration packet is to be generated SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 102 Write 0x63 here 0x0A RESERVED Write 0 here 0x0B RESERVED Write 0 here 0x0C RESERVED Write 0 here 0x0D RESERVED Write 0 here 0x0E RESERVED Write 0 here Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 103 This macro triggers the DSA gain phase calibration sequence for TX channels in AFE79xx. This should be called after the system tune is done. Table 1-49. Macro TX DSA Gain-Phase Factory Calibration Opcode 0x42 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 104 Bits[3:2]: Bands to be enabled for 2TX Bits[5:4]: Bands to be enabled for 3TX Bits[7:6]: Bands to be enabled for 4TX 0x05 RESERVED Write 0 here Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 105 Bit[5:3]: Contains information about the second error condition in the above 16-bit register. Example: Bit[1] and Bit[2] of above register is set -> these 3-bits indicate the nature of input signal integrity error SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 106 1-dB step, the actual resolution is ~ 2 dB for low back-off values. 0x08 RESERVED Write 0 here 0x09 RESERVED Write 0 here Memory Not Used Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 107 3. Once the desired operations with the tone signals are done, the TX channel settings can be restored. Table 1-55. Operand Value Comments 0x00 Set TX Channel as 1TX 0x04 Restore TX channel 1 and 2 configuration. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 108: 1.2.4 Tx Gain Control

    (e.g. if TX Side Select is 0, this corresponds to 1TX). E.g. field value of 10 implies 1.25 dB attenuation. Attenuation > 39 dB is NOT allowed. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 109: Rx Automatic Gain Control (Agc)

    1.2.5 RX AUTOMATIC GAIN CONTROL (AGC) 1.2.5.1 AGC Digital Detector Configuration Table 1-58. Macro AGC Digital Detector Configuration Macro Opcode 0x58 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 110 –0.25 0x06 Detector Threshold Power Detector Attack Threshold with resolution of –0.25 dB 0x07 Detector Threshold Power Detector Decay Threshold with resolution of –0.25 dB Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 111 Bit 5 → RESERVED 0x01 Time Constant Big Step Attack Time Constant (fast attack) (1 LSB = 10 ns). For example value of 1024 implies 10240 ns. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 112 Bit 4 → RESERVED Bit 5 → RESERVED 0x01 Fraction of samples crossing signal threshold in given time constant for Big Step Attack detector to declare attack Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 113 1.2.5.4 AGC Digital Detector Absolute Time Crossing Macro Table 1-61. Macro AGC Digital Detector Absolute Time Crossing Opcode 0x5B Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 114 In case of decay detectors, the trigger happens if the actual number of crossings is less than the programmed crossing limit from this macro. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 115 Each pin select is a 15 bit number with each bit corresponding to a different detector output. This macro does not perform any GPIO connections. The bit wise detector mapping is as below: SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 116 Enables Control of peak detector reset using GPIO.This macro doesn’t perform any GPIO connections (applicable only in External AGC mode). SBAA417 configuration document for configuration of GPIO. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 117 1 → Freeze the decay detectors along with the AGC state during the OFF period of TDD. Attack detectors are always reset during the OFF period of TDD. SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 118 LSB being 0.5 dB change in the value. 1.2.5.9 AGC External DVGA Configuration Macro Table 1-67. Macro AGC External DVGA Configuration Macro Opcode 0x60 Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 119 25 MHz Memory Not used 1.2.5.10 AGC External LNA Configuration Macro Table 1-68. Macro AGC External LNA Configuration Macro Opcode 0x61 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 120 0x04 Band Detector Bandwidth Selection (Applicable only when dual LNA control and band detectors are enabled) 0: Higher bandwidth 1: Output bandwidth. Table 1-71. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 121 RESERVED 0x04 RESERVED 1.2.5.12 AGC Dual LNA Time Crossings Macro Table 1-70. Macro AGC Dual LNA Time Crossings Opcode 0x63 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 122 If Band Detector Bandwidth Selection is set to output bandwidth then F = Output Rate. BAND If Band Detector Bandwidth Selection is set to higher bandwidth then use the table below. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 123 Mode: 0x0: Customer AGC (External AGC mode) 0x1: Very big step attack 0x2: As detector to bypass LNA 0x03 Absolute/Relative option for Time Crossings 0:Absolute 1:Relative SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 124 3RX. Bit 3: 1 → Value specified in subsequent operands is valid for 4RX. Bit 4 → RESERVED Bit 5 → RESERVED Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 125 3RX. Bit 3: 1 → Value specified in subsequent operands is valid for 4RX. Bit 4 → RESERVED Bit 5 → RESERVED SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 126 3RX. Bit 3: 1 → Value specified in subsequent operands is valid for 4RX. Bit 4 → RESERVED Bit 5 → RESERVED Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 127 4 → INVALID_INT_AND_EXT_AGC_COMBINATION Error Code 2 (32-bit) Not Used 1.2.5.17 ALC Configuration Macro Table 1-77. Macro ALC Configuration Opcode 0x69 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 128 2. Other way is to mention a different value in the Macro itself. Then the lower 6 bits should be programmed to the required value and the MSB should be made 0. ALC Mode: There are several modes in which ALC can operate: Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 129 3. 0x02 → 4-bit exponent, 11-bit mantissa and 1-bit sign 1.2.5.19 ALC Coarse Fine Mode Macro Table 1-79. Macro ALC Coarse Fine Mode Opcode 0x6B Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 130 Coarse Index Invert: Applicable in only modes where coarse index is sent on the LSBs. If 0, send the coarse index. If 1, all the bits of coarse index are flipped and sent. Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 131 Memory Not used 1.2.5.21 ALC Coarse Index Pins Delay Macro Table 1-81. Macro ALC Coarse Index Pins Delay Opcode 0x80 Operand Offset Length Value Functionality Results SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 132: Sleep Mode Control

    Additionally, it allows selective channels to be put into sleep. 1.3.1 Sleep Mode Configuration This Macro specifies the Sleep Mode behaviour. Table 1-82. Macro Sleep Mode Configuration Opcode 0x55 Operand Offset Length Value Functionality Results Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 133 Bit 1: 0 → 2FB will go to light sleep when sleep is triggered 1 → 2FB will go to deep sleep when sleep is triggered SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 134 Write 0 here 0x0D RESERVED Write 0 here 0x0E RESERVED Write 0 here 0x0F RESERVED Write 0 here 0x10 RESERVED Write 0 here Memory Not used Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 135: 1.3.2 Sleep/Active Trigger

    In case of pin, the rise edge will be used for Sleep operation. c. In case of macro: i. Sleep/Active Trigger (Opcode – 0x57) Table 1-85. Operand Value Comments 0x01 Perform sleep operation SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 136: Example Macro Call Sequence

    Configure entire device in TDD mode 1.4.4 System Bands Configuration (Opcode – 0x23) Table 1-90. Operand Value Comments 0xFF Configure Common Setting for all RX and TX Channels Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 137: Rx Interface Rate Configuration (Opcode - 0X29)

    1.4.9 FB ADC Rate Configuration (Opcode – 0x2D) Table 1-95. Operand Value Comments 0x03 Configure Common Setting for both FB Channels 0x07 Select ADC Sampling Rate of 2949.12MHz SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 138: Tx Dac Rate Configuration (Opcode - 0X2E)

    0x01 Dual NCO Mode 0x000867E0 TX Band 1 frequency of 3500MHz modulo FB-ADC-Rate. 0x00100900 TX Band 2 frequency of 4000MHz modulo FB-ADC-Rate. 0x00000000 Unused 0x00000000 Unused Macro SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 139: Tx Channel Frequency Configuration (Opcode - 0X30)

    RATE/2) 1.4.17 Tune System (Opcode – 0x36) All configurations are provided. Now apply these configurations in the device. Table 1-103. Operand Value Comments 0x3F 0x0F 0x0000 SBAU337 – May 2020 Macro Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 140: Serial Interface Register Maps

    Chapter 2 SBAU337 – May 2020 Serial Interface Register Maps Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 141: Afe79Xx_Global Register Map

    Must read or write 0 In streaming mode 1=addreses increases 0=address GLOBAL_ASCEND decreases GLOBAL_4PIN Use 4 pin SPI interface when asserted. Must read or write 0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 142: Register 1H (Offset = 1H) [Reset = 0H]

    2.1.5 Register 4h (offset = 4h) [reset = 78h] Figure 2-5. Register 4h CHIP_ID[7:0] R-78h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 143: Register 5H (Offset = 5H) [Reset = 0H]

    2.1.9 Register 8h (offset = 8h) [reset = 4h] Figure 2-9. Register 8h VENDOR_ID[15:8] R-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 144: Register 10H (Offset = 10H) [Reset = 0H]

    Figure 2-12. Register 12h FB TOP RX TOP R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 145: Register 13H (Offset = 13H) [Reset = 0H]

    Reset Description Page select for TxCalib 0- txCalibA0 1- txCalibA1 2- txCalibB0 TXCALIB 3- txCalibB1 4- txCalibC0 5- txCalibC1 6- txCalibD0 7- txCalibD1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 146: Register 15H (Offset = 15H) [Reset = 0H]

    R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 147: Register 19H (Offset = 19H) [Reset = 0H]

    6 = alarm SPI streaming roll over SPI-A. 7= alarm SPI streaming roll over SPI-B1. 8 = alarm SPI streaming roll over SPI-B2. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 148: Register 1Ch (Offset = 1Ch) [Reset = 0H]

    6 = alarm SPI streaming roll over SPI-A. 7= alarm SPI streaming roll over SPI-B1. 8 = alarm SPI streaming roll over SPI-B2. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 149: Register 1Eh (Offset = 1Eh) [Reset = 0H]

    6 = alarm SPI streaming roll over SPI-A. 7= alarm SPI streaming roll over SPI-B1. 8 = alarm SPI streaming roll over SPI-B2. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 150: Pll Register Map

    CTL_REFCLK_BU 00 -> scale = 1 F_CONST_300U 01 -> scale = 0.8 10 -> scale = 1.4 11 -> scale = 1.2 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 151: Register 3Fh (Offset = 3Fh) [Reset = 8H]

    Figure 2-27. Register 41h reserved reserved CTL_CP_BIAS reserved R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 152: Register 43H (Offset = 43H) [Reset = 18H]

    3 : 40p DELAY 4 : T/2+40p 5 : 60p 6 : T/2+60p 7 : 80p Where T is the time period of the clock Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 153: Register 63H (Offset = 63H) [Reset = 0H]

    1 -> enabled. Register to calibrate PLL. A rising edge(0 to 1 transition on EN_CAL this register) is required to calibrate the PLL. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 154: Register 68H (Offset = 68H) [Reset = 0H]

    2.2.12 Register 6Dh (offset = 6Dh) [reset = 0h] Figure 2-35. Register 6Dh LCMGEN_DIV[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 155: Register 6Eh (Offset = 6Eh) [Reset = 0H]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-40. Register 70 Field Descriptions Field Type Reset Description LCMGEN_DIV[7:0] Number of sysref pulses to leak to RX. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 156: Register 71H (Offset = 71H) [Reset = 0H]

    > vol(3) > vol(0) > vol(1) LDOVCO_FORCE force PLL_LDO_OUT to AVDD_1P8V_VCO _OUTTOVDD reserved reserved reserved Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 157: Jesd_Subchip Register Map

    MUX_SEL_FBAB_I1_FOR_2R1F_C MUX_SEL_FBAB_Q0_FOR_2R1F_ MUX_SEL_FBAB_I0_FOR_2R1F_C MUX_SEL_FBCD_Q1_FOR_2R1F_ MUX_SEL_FBCD_I1_FOR_2R1F_C MUX_SEL_FBCD_Q0_FOR_2R1F_ MUX_SEL_FBCD_I0_FOR_2R1F_C TXOCTETPATH1_SEL TXOCTETPATH0_SEL TXOCTETPATH3_SEL TXOCTETPATH2_SEL TXOCTETPATH5_SEL TXOCTETPATH4_SEL TXOCTETPATH7_SEL TXOCTETPATH6_SEL TXOCTETPATH1_CLK_SEL TXOCTETPATH0_CLK_SEL TXOCTETPATH3_CLK_SEL TXOCTETPATH2_CLK_SEL TXOCTETPATH5_CLK_SEL TXOCTETPATH4_CLK_SEL TXOCTETPATH7_CLK_SEL TXOCTETPATH6_CLK_SEL SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 158 LOAD_SLOW_CLK_CNT_SEED_VAL[7:0] LOAD_SLOW_CLK_CNT_SEED_VAL[15:8] CFG_CLK_COMP_SLOW_CNT_OBS_SEL CFG_CLK_COMP_FAST_CNT_OBS_SEL CFG_CLK_COM PARATOR_INST _SEL CLK_OBS_DON E_INTR FAST_CLK_CNT[7:0] FAST_CLK_CNT[15:8] SLOW_CLK_CNT[7:0] SLOW_CLK_CNT[15:8] RX_CLK_LFSR_ RX_CLK_SYSR RX_CLK_SYSR RX_CLK_DITHE RX_CLK_DISAB RX_CLK_SYSREF_DELAY SEED_LOAD EF_VAL EF_SEL RED_MODE_EN Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 159 APB_CLK_LFSR _CODE_OVR_V M_MCU_CLK_E _LOAD APB_CLK_LFSR_SEED_VAL[7:0] APB_CLK_LFSR_SEED_VAL[15:8] APB_CLK_LFSR_SEED_VAL[23:16] DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY DAC_JESD_SY NC_N3_SPI_OV NC_N3_SPI_VA NC_N2_SPI_OV NC_N2_SPI_VA NC_N1_SPI_OV NC_N1_SPI_VA NC_N0_SPI_OV NC_N0_SPI_VA SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 160 FO_SYS_REF_ FO_SYS_REF_ 176h OGGLE_STICKY OGGLE_STICKY RD_STICKY WR_STICKY OGGLE_STICKY OGGLE_STICKY RD_STICKY WR_STICKY 180h ADC_SYNC_N_FROM_PIN 181h ADC_SYNC_N_POST_MUX 182h DAC_SYNC_N_TO_PIN 183h DAC_SYNC_N_PRE_MUX 188h DBG_RX_READ_OUT_REG1[7:0] 189h DBG_RX_READ_OUT_REG1[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 161: Register 20H (Offset = 20H) [Reset = 12H]

    SerdesAB APB interface through different modes SERDESAB_APB_ 0 : SPI2APB PIN_INTF_EN 1 : GPIO 2 : CM4 AHB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 162: Register 21H (Offset = 21H) [Reset = 12H]

    (0 -no inversion, 1 - invert) SERDESCD_RXB [3] = SRX8 rxbclk invert CLK_INV_ENA [2] = SRX7 rxbclk invert [1] = SRX6 rxbclk invert [0] = SRX5 rxbclk invert Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 163: Register 25H (Offset = 25H) [Reset = Ffh]

    (0 -disable, 1 - enable) SERDESAB_RXBC [3] = SRX4 rxbclk enable LK_ENA [2] = SRX3 rxbclk enable [1] = SRX2 rxbclk enable [0] = SRX1 rxbclk enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 164: Register 27H (Offset = 27H) [Reset = Ffh]

    DDC_RD_CLK _FBCD_FBAB_ _RXD_RXB_CL _RXC_RXA_CL CLK_SYSREF_ K_SYSREF_M K_SYSREF_M R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 165: Register 2Bh (Offset = 2Bh) [Reset = 0H]

    ALID_RD_OVR ALID_RD_VAL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 166: Register 2Dh (Offset = 2Dh) [Reset = 0H]

    FBCD_SIG_INVALI When FBCD_SIG_INVALID_RD_OVR is 1, D_RD_VAL setting this register val = 0, gates the data setting to val = 1, ungates the data Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 167: Register 2Eh (Offset = 2Eh) [Reset = 0H]

    4-lanes of 2T-AB instance).Use this mux b-pin UC_TXA_TO_TXB value along with 'mux_ovr_for_duc_clk'. _CLK Use of LATTE configuration is recommended to set these registers. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 168: Register 30H (Offset = 30H) [Reset = 88H]

    2.3.16 Register 32h (offset = 32h) [reset = 88h] Figure 2-57. Register 32h FBCD_AFIFO_OFFSET FBAB_AFIFO_OFFSET R/W-8h R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 169: Register 33H (Offset = 33H) [Reset = 0H]

    2.3.18 Register 34h (offset = 34h) [reset = 0h] Figure 2-59. Register 34h MUX_SEL_RXA_B1_Q_FOR_2R1F_AB MUX_SEL_RXA_B1_I_FOR_2R1F_AB R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 170 3 : b2_rxb_q/rxb_q_s1 4 : b1_rxc_q/rxc_q_s0 5 : b2_rxc_q/rxc_q_s1 6 : b1_rxd_q/rxd_q_s0 7 : b2_rxd_q/rxd_q_s1 Using LATTE to configure this register is recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 171 2.3.21 Register 37h (offset = 37h) [reset = 66h] Figure 2-62. Register 37h MUX_SEL_RXB_B2_Q_FOR_2R1F_AB MUX_SEL_RXB_B2_I_FOR_2R1F_AB R/W-6h R/W-6h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 172 3 : b2_rxb_q/rxb_q_s1 4 : b1_rxc_q/rxc_q_s0 5 : b2_rxc_q/rxc_q_s1 6 : b1_rxd_q/rxd_q_s0 7 : b2_rxd_q/rxd_q_s1 Using LATTE to configure this register is recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 173 2.3.24 Register 3Ah (offset = 3Ah) [reset = 66h] Figure 2-65. Register 3Ah MUX_SEL_RXD_B1_Q_FOR_2R1F_AB MUX_SEL_RXD_B1_I_FOR_2R1F_AB R/W-6h R/W-6h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 174 3 : b2_rxb_q/rxb_q_s1 4 : b1_rxc_q/rxc_q_s0 5 : b2_rxc_q/rxc_q_s1 6 : b1_rxd_q/rxd_q_s0 7 : b2_rxd_q/rxd_q_s1 Using LATTE to configure this register is recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 175 2.3.27 Register 41h (offset = 41h) [reset = 22h] Figure 2-68. Register 41h MUX_SEL_RXC_B2_Q_FOR_2R1F_CD MUX_SEL_RXC_B2_I_FOR_2R1F_CD R/W-2h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 176 3 : b2_rxd_q/rxd_q_s1 4 : b1_rxa_q/rxa_q_s0 5 : b2_rxa_q/rxa_q_s1 6 : b1_rxb_q/rxb_q_s0 7 : b2_rxb_q/rxb_q_s1 Using LATTE to configure this register is recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 177 3 : b2_rxd_i/rxd_i_s1 4 : b1_rxa_i/rxa_i_s0 5 : b2_rxa_i/rxa_i_s1 6 : b1_rxb_i/rxb_i_s0 7 : b2_rxb_i/rxb_i_s1 Using LATTE to configure this register is recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 178 MUX_SEL_FBCD_Q0_FOR_2R1 MUX_SEL_FBCD_I0_FOR_2R1 F_AB F_AB F_AB F_AB R/W-3h R/W-3h R/W-2h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 179 Q1_FOR_2R1F_C 0 : fbcd_q_s0 1 : fbcd_q_s1 2 : fbab_q_s0 3 : fbab_q_s1 Using LATTE to configure this register is recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 180 MUX_SEL_FBCD_I 0 : fbcd_i_s0 1_FOR_2R1F_CD 1 : fbcd_i_s1 2 : fbab_i_s0 3 : fbab_i_s1 Using LATTE to configure this register is recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 181 2.3.35 Register 49h (offset = 49h) [reset = 32h] Figure 2-76. Register 49h TXOCTETPATH3_SEL TXOCTETPATH2_SEL R/W-3h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 182 2.3.37 Register 4Bh (offset = 4Bh) [reset = 76h] Figure 2-78. Register 4Bh TXOCTETPATH7_SEL TXOCTETPATH6_SEL R/W-7h R/W-6h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 183 2.3.39 Register 4Dh (offset = 4Dh) [reset = 32h] Figure 2-80. Register 4Dh TXOCTETPATH3_CLK_SEL TXOCTETPATH2_CLK_SEL R/W-3h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 184 2.3.41 Register 4Fh (offset = 4Fh) [reset = 76h] Figure 2-82. Register 4Fh TXOCTETPATH7_CLK_SEL TXOCTETPATH6_CLK_SEL R/W-7h R/W-6h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 185 TA_NEGATION A_NEGATION R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 186 Determines whether the data is to be negated or not. TXC_B0_Q_DATA 0 : Normal data (No negation) _NEGATION 1 : 2's complement (negation) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 187 ADC_JESD_SYNC funcationlity. _N2_MUX_SEL This register is used for change the sync_n pin order. Using LATTE to configure this register is recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 188 To invert polarity of sync_n[1] ADC_JESD_SYNC 0 : No-invert _N1_INV 1 : Invert To invert polarity of sync_n[0] ADC_JESD_SYNC 0 : No-invert _N0_INV 1 : Invert Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 189 0 : No override. _N1_SPI_OVR 1: override Determines whether to override the sync_n[0] with spi. ADC_JESD_SYNC 0 : No override. _N0_SPI_OVR 1: override SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 190 2.3.53 Register 5Eh (offset = 5Eh) [reset = 54h] Figure 2-94. Register 5Eh ADC_JESD_SYNC_N5_REORDER ADC_JESD_SYNC_N4_REORDER R/W-5h R/W-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 191 2.3.55 Register 61h (offset = 61h) [reset = 32h] Figure 2-96. Register 61h MUX_SEL_FOR_TXD_CTRL MUX_SEL_FOR_TXC_CTRL R/W-3h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 192 3 : sel lane3 data 4 : sel lane4 data 5 : sel lane5 data 6 : sel lane6 data 7 : sel lane7 data Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 193 3 : sel lane3 data 4 : sel lane4 data 5 : sel lane5 data 6 : sel lane6 data 7 : sel lane7 data SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 194 3 : sel lane3 clk 4 : sel lane4 clk 5 : sel lane5 clk 6 : sel lane6 clk 7 : sel lane7 clk Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 195 3 : sel lane3 clk 4 : sel lane4 clk 5 : sel lane5 clk 6 : sel lane6 clk 7 : sel lane7 clk SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 196 0 - enable data gating of RXD data based on Rx_ON/FB_ON ADC_DATA_GATI signals NG_DIS_RXD 1 - disable data gating of RXD data based on Rx_ON/FB_ON signals Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 197 RxD is OFF since these LSBs might carry OVR data BIT_MASKDIS_RX 0001 - LSB0 0010 - LSB1 0100 - LSB4 1000 - LSB5 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 198 1111 - Uses ored rx_on d,c,b,a 0111 - Uses or'ed rx_on c,b,a 0011 - Uses or'ed rx_on b,a 0001 - Uses or'ed rx_on a 0000 - Uses zero Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 199 Figure 2-111. Register 7Eh LP_FB_ON_C_SEL_2R1F_AB_ LP_FB_ON_A_SEL_2R1F_AB_ MASK MASK R/W-2h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 200 Figure 2-113. Register 82h LP_FB_ON_C_SEL_2R1F_CD_ LP_FB_ON_A_SEL_2R1F_CD_ MASK MASK R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 201 2.3.74 Register 91h (offset = 91h) [reset = 0h] Figure 2-115. Register 91h CFG_SLOW_CLK_SEL CFG_FAST_CLK_SEL R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 202 13 : Jesd-clk for fbcd 14 : Direct GPIO clean clock 15 : APB clock used in spi2apb and as clock_bus to serdes Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 203 2.3.76 Register 93h (offset = 93h) [reset = 64h] Figure 2-117. Register 93h LOAD_SLOW_CLK_CNT_SEED_VAL[15:8] R/W-64h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 204 2.3.79 Register 97h (offset = 97h) [reset = 0h] Figure 2-120. Register 97h CLK_OBS_DO NE_INTR R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 205 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-126. Register 9A Field Descriptions Field Type Reset Description SLOW_CLK_CNT[ Slow clock count value. MSB bit is ignored. 7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 206 ABLE ABLE _DISABLE R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 207 0 : Disable clk dither D_MODE_EN 1 : Enable clk dither Disable clk-generation from this module FB_CLK_DISABLE 0 : Enable 1 : Disable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 208 'tx_clk_lfsr_seed_val' register ED_LOAD 0 : Use default LFSR seed value 1 : Load LFSR seed value from register TX_CLK_SYSREF spi-based sysref _VAL Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 209 2.3.90 Register A4h (offset = A4h) [reset = 10h] Figure 2-131. Register A4h RX_CLK_DIV_VAL_ACC_THRESH R/W-10h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 210 Table 2-137. Register A7 Field Descriptions Field Type Reset Description RX_CLK_LFSR_S lfsr seed value. Need to be used along with EED_VAL[23:16] 'rx_clk_lfsr_seed_load' register Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 211 2.3.97 Register ABh (offset = ABh) [reset = EFh] Figure 2-138. Register ABh FB_CLK_LFSR_SEED_VAL[23:16] R/W-EFh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 212 Table 2-144. Register AE Field Descriptions Field Type Reset Description TX_CLK_LFSR_SE lfsr seed value. Need to be used along with ED_VAL[15:8] 'tx_clk_lfsr_seed_load' register Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 213 1 : swap When 1, swap data on pins p0 and p1 IQ_SWAP_RXA_P Used for IQ swap 0 : No swap 1 : swap SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 214 2R1F_AB instance TDD_RX_ON_D_2 If the rx data has rxd information then set the register to 1 R1F_AB_MASK 0 : mask 1 : rx_on_d Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 215 2R1F_CD instance TDD_FB_ON_C_2 If the fb data has fbcd information then set the register to 1 R1F_CD_MASK 0 : mask 1 : fb_on_c SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 216 Figure 2-149. Register BCh TDD_TX_ON_D_2T_AB_MUX_S TDD_TX_ON_C_2T_AB_MUX_S TDD_TX_ON_B_2T_AB_MUX_S TDD_TX_ON_A_2T_AB_MUX_S R/W-3h R/W-2h R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 217 TDD mask-value for tx_on_a to be set if TXD data comes from TDD_TX_ON_D_2 2T_AB instance and link0 T_AB_LINK0_MAS 0 : mask 1 : tx_on_d SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 218 TXA data comes from 2T_CD instance TDD_TX_ON_A_2 0 : tx_on_a T_CD_MUX_SEL 1 : tx_on_b 2 : tx_on_c 3 : tx_on_d Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 219 REF_VAL REF_SEL HERED_MODE ABLE R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 220 If apb_clk_div_factor = 0, and apb_clk_div_factor_odd=0, the the divide ratio is (15,16) If apb_clk_divide_factor = 0, and apb_clk_div_factor_odd=1, the the divide ratio is 15 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 221 If apb_clk_div_factor = 0, and apb_clk_div_factor_odd=0, the the divide ratio is (15,16) If apb_clk_divide_factor = 0, and apb_clk_div_factor_odd=1, the the divide ratio is 15 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 222 Loads the LFSR seed value when this is set to 1. Need to be APB_CLK_LFSR_L used along with 'apb_clk_lfsr_seed_val' register 0 : Use default LFSR seed value 1 : Load LFSR seed value from register Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 223 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-161. Register C7 Field Descriptions Field Type Reset Description APB_CLK_LFSR_ LFSR load. Need to be used along with 'apb_clk_lfsr_load' SEED_VAL[23:16] register SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 224 Invert dac_jesd sync_n1 output DAC_JESD_SYNC 0 : No-invert _N1_INV 1 : Invert Invert dac_jesd sync_n0 output DAC_JESD_SYNC 0 : No-invert _N0_INV 1 : Invert Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 225 2.3.121 Register CCh (offset = CCh) [reset = 0h] Figure 2-162. Register CCh MUX_SEL_FOR_TXA_B0_Q MUX_SEL_FOR_TXA_B0_I R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 226 2.3.122 Register CDh (offset = CDh) [reset = 11h] Figure 2-163. Register CDh MUX_SEL_FOR_TXA_B1_Q MUX_SEL_FOR_TXA_B1_I R/W-1h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 227 2.3.123 Register CEh (offset = CEh) [reset = 22h] Figure 2-164. Register CEh MUX_SEL_FOR_TXB_B0_Q MUX_SEL_FOR_TXB_B0_I R/W-2h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 228 2.3.124 Register CFh (offset = CFh) [reset = 33h] Figure 2-165. Register CFh MUX_SEL_FOR_TXB_B1_Q MUX_SEL_FOR_TXB_B1_I R/W-3h R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 229 2.3.125 Register D0h (offset = D0h) [reset = 44h] Figure 2-166. Register D0h MUX_SEL_FOR_TXC_B0_Q MUX_SEL_FOR_TXC_B0_I R/W-4h R/W-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 230 2.3.126 Register D1h (offset = D1h) [reset = 55h] Figure 2-167. Register D1h MUX_SEL_FOR_TXC_B1_Q MUX_SEL_FOR_TXC_B1_I R/W-5h R/W-5h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 231 2.3.127 Register D2h (offset = D2h) [reset = 66h] Figure 2-168. Register D2h MUX_SEL_FOR_TXD_B0_Q MUX_SEL_FOR_TXD_B0_I R/W-6h R/W-6h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 232 2.3.128 Register D3h (offset = D3h) [reset = 77h] Figure 2-169. Register D3h MUX_SEL_FOR_TXD_B1_Q MUX_SEL_FOR_TXD_B1_I R/W-7h R/W-7h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 233 0 : No swap 1 : swap When 1, swap iq data of TXC_B1 IQ_SWAP_TXC_B Used for IQ swap 0 : No swap 1 : swap SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 234 2.3.131 Register 156h (offset = 156h) [reset = FFh] Figure 2-172. Register 156h TXB_DAC_CLK_EN_VAL TXA_DAC_CLK_EN_VAL R/W-Fh R/W-Fh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 235 [3] = mask SRX4 LOS indicator INDICATOR_MAS [2] = mask SRX3 LOS indicator [1] = mask SRX2 LOS indicator [0] = mask SRX1 LOS indicator SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 236 [3] = clear SRX8 LOS indicator INDICATOR_CLEA [2] = clear SRX7 LOS indicator [1] = clear SRX6 LOS indicator [0] = clear SRX5 LOS indicator Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 237 2.3.138 Register 15Dh (offset = 15Dh) [reset = 0h] Figure 2-179. Register 15Dh SERDESAB_PHY_READY SERDESAB_LOS_INDICATOR R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 238 Table 2-184. Register 15F Field Descriptions Field Type Reset Description SERDESCD_PLL_ register indicating SerdesCD PLL loss-of-lock LOSS_OF_LOCK SERDESAB_PLL_ register indicating SerdesAB PLL loss-of-lock LOSS_OF_LOCK Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 239 3 : RX D 4 : FB A 5 : FB C DBG_CFG_FIFO_ When 1, pointers are sampled and saved in registers PTR_SAMPLE dbg_fifo_sampled_*_ptr SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 240 RXD to JESD Async-FIFO debug alarm. Only bit0 is C_FIFO_ALARM_ valid. DBG_RXC_ASYN clear for RXC to JESD Async-FIFO debug alarm. Only bit0 is C_FIFO_ALARM_ valid. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 241 RXD to JESD Async-FIFO debug alarm. Only bit0 is C_FIFO_ALARM_ valid. MASK DBG_RXC_ASYN mask for RXC to JESD Async-FIFO debug alarm. Only bit0 is C_FIFO_ALARM_ valid. MASK SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 242 RX-D to JESD Async fifo. Only bit0 C_FIFO_ALARM is valid. DBG_RXC_ASYN overflow/underflow flag for RX-C to JESD Async fifo. Only bit0 C_FIFO_ALARM is valid. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 243 Table 2-198. Register 171 Field Descriptions Field Type Reset Description DBG_RXD_AFIFO Debug: _SYSREF_SPACI For async fifo sysref spacing DBG_RXC_AFIFO Debug: _SYSREF_SPACI For async fifo sysref spacing SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 244 RXA to JESD Async FIFO wr-clk monitor E_STICKY DBG_RXA_AFIFO _SYS_REF_RD_S RXA to JESD Async FIFO rd-sysref monitor TICKY DBG_RXA_AFIFO _SYS_REF_WR_S RXA to JESD Async FIFO wr-sysref monitor TICKY Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 245 Type Reset Description DBG_FBCD_AFIF O_RD_CLK_TOGG FBCD to JESD Async FIFO rd-clk monitor LE_STICKY DBG_FBCD_AFIF O_WR_CLK_TOG FBCD to JESD Async FIFO wr-clk monitor GLE_STICKY SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 246 Field Type Reset Description ADC_SYNC_N_PO Spi monitor of adc_sync_n values post sync_n mux. 8 bits ST_MUX correspond to sync going to 8 lanes Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 247 2.3.164 Register 189h (offset = 189h) [reset = 0h] Figure 2-205. Register 189h DBG_RX_READ_OUT_REG1[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 248 2.3.167 Register 18Ch (offset = 18Ch) [reset = 0h] Figure 2-208. Register 18Ch DBG_FB_READ_OUT_REG1[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 249 2.3.170 Register 18Fh (offset = 18Fh) [reset = 0h] Figure 2-211. Register 18Fh DBG_FB_READ_OUT_REG2[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 250 Data from first 4T mux output, is sent to this status register, to DBG_TX_READ_O check for data toggling. UT_REG2[7:0] dbg_tx_read_out_reg1 and dbg_tx_read_out_reg2 has two consecutive samples Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 251 Table 2-220. Register 195 Field Descriptions Field Type Reset Description Sig-valid from TDD controller is assigned to this status DBG_TX_ON_D register, post synchronizer SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 252 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-223. Register 19E Field Descriptions Field Type Reset Description SPARE_OUT_REG spare registers out Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 253 2.3.183 Register 1A2h (offset = 1A2h) [reset = 0h] Figure 2-224. Register 1A2h SPARE_OUT_REG6 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 254 2.3.187 Register 1A6h (offset = 1A6h) [reset = 0h] Figure 2-228. Register 1A6h SPARE_IN[23:16] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 255 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-232. Register 1A7 Field Descriptions Field Type Reset Description SPARE_IN[31:24] spare registers in SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 256 LINK0_COMMA_ COMMA_ALIGN LINK1_COMMA_ LINK0_COMMA_ _REALIGN_MAS ALIGN_LOCK_R ALIGN_LOCK_R _TIMER_EN ALIGN_RESET ALIGN_RESET ESET_DISABLE ESET_DISABLE COMMA_ALIGN_BIT_COUNTER_INIT COMMA_ALIGN_VALID_THRESH COMMA_ALIGN_INVALID_THRESH LINK0_DID LINK0_BID LINK0_ADJCNT LINK0_ADJDIR LINK0_PHADJ LINK0_SCR LINK0_ILA_L_M1 LINK0_ILA_F_M1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 257 LINK1_INIT_F_COUNTER LINK1_AUTOLO LINK0_AUTOLO LINK1_SYNC_E LINK0_SYNC_E AD_JESD_ERR AD_JESD_ERR RROR_CNT_CL RROR_CNT_CL MATCH_SPECIF DISABLE_ERR_ NO_LANE_SYN MIN_LATENCY_ MATCH_CTRL JESD_TEST_SEQ MP_LINK_ENA REPORT MATCH_DATA SYNC_REQUEST_PULSE_EXPANSION_COUNT LINK0_SYNC_REQUEST_ENA LINK1_SYNC_REQUEST_ENA LINK0_ERROR_ENA LINK1_ERROR_ENA SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 258 GN_RESET GN_RESET ET_DISABLE ET_DISABLE EMB_ALIGN_INVALID_THRESH EMB_ALIGN_VALID_THRESH DATA_BITS_RE DATA_BYTES_ DATA_BITS_RE DATA_BYTES_ JESDC_CRC_M JESDC_80B_M JESDC_ENCODING_MODE ORDER_AFTER REORDER_AFT ORDER_BEFOR REORDER_BEF ODE_EN _CRC ER_CRC E_CRC ORE_CRC JESDC_CMD_DATA[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 259 CLEAR_JESD_CLK_FLAG CLEAR_JESD_SYSREF_DIV2_FLAG CLEAR_JESD_CLK_DIV2_FLAG CLEAR_DUC_SYSREF_FLAG CLEAR_DUC_CLK_FLAG EMB_ALIGN_LOCK_FLAG COMMA_ALIGN_LOCK_FLAG SERDES_RXBCLK_FLAG VALID_DATA_OUT_FLAG TX_DAC_SYSREF_FLAG TX_DAC_CLK_FLAG JESD_SYSREF_TX1_FLAG JESD_CLK_TX1_FLAG JESD_SYSREF_DIV2_TX1_FLAG JESD_CLK_DIV2_TX1_FLAG DUC_SYSREF_TX1_FLAG DUC_CLK_TX1_FLAG JESD_SYSREF_TX2_FLAG JESD_CLK_TX2_FLAG JESD_SYSREF_DIV2_TX2_FLAG JESD_CLK_DIV2_TX2_FLAG DUC_SYSREF_TX2_FLAG DUC_CLK_TX2_FLAG SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 260 _ERRORS_TO_ RMS_TO_PAP ARMS_TO_PAP ARMS 128h PAP_EN PAP_EN PAP_EN PAP_EN 12Ah LANE_ERRORS_PULSE_EXPANSION_COUNT_LANE01 12Bh LANE_ERRORS_PULSE_EXPANSION_COUNT_LANE23 12Ch TXB_LANE_ALARMS_TO_PAP_EN TXA_LANE_ALARMS_TO_PAP_EN 12Dh TXD_LANE_ALARMS_TO_PAP_EN TXC_LANE_ALARMS_TO_PAP_EN 138h LINK0_SYNC_RELEASE_RBD_M1[7:0] 139h LINK0_SYNC_RELEASE_RBD_M1[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 261 2.4.2 Register 21h (offset = 21h) [reset = 1h] Figure 2-231. Register 21h SYSREF_MODE R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 262 Defines the number of parallel samples to be given out in duc_clk to tx_top from lanes[0:1]/[4:5] LINK0_JESD_SAM 0 : DB,S=1 PLE_MODE 1 : SB,S=1 2 : SB,S=2 3 : SB,S=4 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 263 2.4.4 Register 23h (offset = 23h) [reset = 45h] Figure 2-233. Register 23h LINK1_JESD_SAMPLE_MODE LINK1_JESD_MODE R/W-1h R/W-5h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 264 41 : NA 42 : NA 43 : NA 44 : NA 45 : NA 46 : NA 47 : NA 48 : NA Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 265 Override lane3/7 sysref based serdesfifo init_state with spi- SERDESFIFO_INI based init_state. To be used along with T_STATE_LANE3_ serdesfifo_init_state_ovr. 0 : no override 1 : override SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 266 Table 2-240. Register 26 Field Descriptions Field Type Reset Description MAPPER_SYNC_F TESTMODE IFO_EN_OVR MAPPER_SYNC_F IFO_DATA_SWAP TESTMODE _VAL MAPPER_SYNC_F IFO_DATA_SWAP TESTMODE _OVR PHASE_MODE UNUSED Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 267 OFFSET_OVR OFFSET_OVR R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 268 Figure 2-240. Register 2Ah MAPPER_SYNC_FIFO_TX4_OF MAPPER_SYNC_FIFO_TX3_OF FSET_VAL FSET_VAL R/W-2h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 269 DAC_JESD from 48x clock. All DIV_M the other internal clocks like DUC_WR_CLK and JESD_RX_CLK are derieved from this root clock SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 270 DAC_JESD from 48x clock. All DIV_N_M1 the other internal clocks like DUC_WR_CLK and JESD_RX_CLK are derieved from this root clock Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 271 2.4.20 Register 33h (offset = 33h) [reset = 0h] Figure 2-249. Register 33h DUC_CLK_TX2_DIV_N_M1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 272 Table 2-256. Register 36 Field Descriptions Field Type Reset Description For lanes[2:3]/[6:7], M-value in Divide ratio of M/N for JESD_CLK_TX2_D generating the JESD_RX_CLK for DAC_JESD from IV_M ROOT_CLK. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 273 0 : Dither Disable THER_EN 1 : Dither Enable DUC_CLK_IO_DIV UNUSED _DITHER_EN ROOT_CLK dither-en TX_ROOT_CLK_DI 0 : Dither Disable V_DITHER_EN 1 : Dither Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 274 2.4.29 Register 3Ch (offset = 3Ch) [reset = 88h] Figure 2-258. Register 3Ch SERDES_FIFO_OFFSET_LANE1 SERDES_FIFO_OFFSET_LANE0 R/W-8h R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 275 SYNC_FIFO_33TO66_OFFSET_ SYNC_FIFO_33TO66_OFFSET_ LANE23 LANE01 LANE23 LANE01 R/W-0h R/W-0h R/W-2h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 276 LIGN_LOCK_RES JESDC: Any lane error will reset the sync-header alignment ET_DISABLE search. Setting this will will override the reset of those state machines Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 277 Reset Description JESDB: UNUSED COMMA_ALIGN_I JESDC: Minimum number of continous sync-header invalid NVALID_THRESH pattern needed to jump from lock state to hunt state SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 278 2.4.40 Register 47h (offset = 47h) [reset = 1h] Figure 2-269. Register 47h LINK0_SCR LINK0_ILA_L_M1 R/W-0h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 279 Field Type Reset Description JESD M-1 configuration value used only for ILA checking; may LINK0_ILA_M_M1 be set independently of the actual JESD mode SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 280 Selects the version of JESD support LINK0_JESDV JESD S-1 configuration value used only for ILA checking; may LINK0_ILA_S_M1 be set independently of the actual JESD mode Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 281 2.4.50 Register 51h (offset = 51h) [reset = FFh] Figure 2-279. Register 51h COMMA_ALIGN_DLY_THRESH R/W-FFh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 282 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-286. Register 54 Field Descriptions Field Type Reset Description LINK1_ADJDIR Lane configuration LINK1_PHADJ Lane configuration Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 283: Register 55H (Offset = 55H) [Reset = 1H]

    2.4.57 Register 58h (offset = 58h) [reset = 1h] Figure 2-286. Register 58h LINK1_ILA_M_M1 R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 284: Register 59H (Offset = 59H) [Reset = Fh]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-293. Register 5B Field Descriptions Field Type Reset Description Selects the version of JESD support LINK1_JESDV Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 285: Register 5Ch (Offset = 5Ch) [Reset = 80H]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-296. Register 5E Field Descriptions Field Type Reset Description LINK1_RES2 Lane configuration SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 286: Register 5Fh (Offset = 5Fh) [Reset = 0H]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-299. Register 61 Field Descriptions Field Type Reset Description LID1 JESD Lane ID for lane1/5 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 287: Register 62H (Offset = 62H) [Reset = 2H]

    2.4.70 Register 65h (offset = 65h) [reset = 4h] Figure 2-299. Register 65h K_COUNTER_THRESH R/W-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 288: Register 66H (Offset = 66H) [Reset = 4H]

    LINK0_RBD_M1[7: characters(JESDB) or EMB lock(JESDC) across the used lanes have arrived for lanes[0:1]/lanes[4:5]. JESDB: Max value is F*K/4-1 JESDC: Max value is 64*E-1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 289: Register 69H (Offset = 69H) [Reset = Fh]

    LINK1_RBD_M1[15 characters(JESDB) or EMB lock(JESDC) across the used lanes have arrived for lanes[2:3]/lanes[6:7]. JESDB: Max value is F*K/4-1 JESDC: Max value is 64*E-1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 290: Register 6Ch (Offset = 6Ch) [Reset = 1Fh]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-312. Register 6E Field Descriptions Field Type Reset Description LINK0_BUFFER_R EAD_PTR_OFFSE UNUSED LINK0_BUFFER_D elastic buffer depth for lanes[0:1]/[4:5] EPTH Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 291: Register 6Fh (Offset = 6Fh) [Reset = 1Fh]

    2.4.83 Register 72h (offset = 72h) [reset = 0h] Figure 2-312. Register 72h LINK1_INIT_O_COUNTER R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 292: Register 73H (Offset = 73H) [Reset = 0H]

    MIN_LATENCY _REPORT _ENA R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 293: Register 76H (Offset = 76H) [Reset = 1Ch]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-321. Register 77 Field Descriptions Field Type Reset Description SYNC_REQUEST_ PULSE_EXPANSI TESTMODE ON_COUNT SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 294: Register 78H (Offset = 78H) [Reset = Ffh]

    2.4.90 Register 79h (offset = 79h) [reset = FFh] Figure 2-319. Register 79h LINK1_SYNC_REQUEST_ENA R/W-FFh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 295 = JESDC: extended multiblock alignment error bit1 = JESDC: sync-header invalid error ('11' or '00' received in expected sync header location) Bit0 = JESDC: sync-header CRC error SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 296 JESDB : To clear error counter caused due to frame sync NC_ERR_CNT_CL error. JESDC : To clear error counter caused due to fixed-ones error. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 297 Table 2-328. Register 7E Field Descriptions Field Type Reset Description LINK1_LANE_ERR These bits clear the error_counter for each of the errors OR_CNT_CLR mentioned in sync_request_ena register for lanes[2:3]/[6:7]. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 298 R_CNT_THRESH JESDC:error count threshold for cmd error in CRC mode after which it will pull the syncz signal and reset the links. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 299 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-334. Register 84 Field Descriptions Field Type Reset Description LANE0_SYNC_ER lane0/4 sync error count value read R_CNT SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 300 2.4.105 Register 88h (offset = 88h) [reset = 0h] Figure 2-334. Register 88h LANE0_F_COUNTER_ANY_LANE_READY[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 301 Field Type Reset Description LANE1_F_COUNT JESDB: Measured rbd_counter value when lane1/5 is ready ER_ANY_LANE_R JESDC: Measured rbd_counter value when lane1/5 is ready EADY[15:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 302 2.4.112 Register 8Fh (offset = 8Fh) [reset = 0h] Figure 2-341. Register 8Fh LANE3_F_COUNTER_ANY_LANE_READY[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 303 JESDB: Measured rbd_counter value when all enabled lanes LANE1_F_COUNT are ready ER_ALL_LANES_ JESDC: Measured rbd_counter value when all enabled lanes READY[7:0] are ready SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 304 JESDB: Measured rbd_counter value when all enabled lanes LANE2_F_COUNT are ready ER_ALL_LANES_ JESDC: Measured rbd_counter value when all enabled lanes READY[15:8] are ready Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 305 2.4.121 Register 98h (offset = 98h) [reset = 0h] Figure 2-350. Register 98h LINK1_SYSREF_CNT_ON_RELEASE_OPPORTUNITY LINK0_SYSREF_CNT_ON_RELEASE_OPPORTUNITY R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 306 Step-6 Now if you read back the register ' link0_sysref_cnt_on_release_opportunity', it should read back as 0 Note: Refer to TI App Note for detail on RBD optimization. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 307 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-355. Register 99 Field Descriptions Field Type Reset Description LINK0_MAPPER_ TESTMODE CNT_MAX_OVR LINK0_MAPPER_ TESTMODE CNT_MAX_VAL LINK0_MAPPER_S TESTMODE YSREF_CNT_OVR LINK0_MAPPER_S TESTMODE YSREF_CNT_VAL SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 308 LINK1_RELEA LINK1_MAPPE LINK1_RELEASE_OPPORTUNITY_PIPE_DLY_VAL SE_OPPORTU R_RESET NITY_PIPE_DL Y_OVR R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 309 For stable link, the bits for each lane enabled should read as "01" Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 310 2.4.130 Register A4h (offset = A4h) [reset = 0h] Figure 2-359. Register A4h JESD_FS_STATE R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 311 For stable link, the bits for each lane enabled should read as "11" Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 312 JESDC: reset emb_align search and start again for LINK1_EMB_ALIG lanes[2:3]/[6:7] N_RESET JESDB : UNUSED JESDC: reset emb_align search and start again for LINK0_EMB_ALIG lanes[0:1]/[4:5] N_RESET JESDB : UNUSED Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 313 JESDB : UNUSED E_EN 0 : 66b 1 : 80b DATA_BITS_REO RDER_AFTER_CR UNUSED DATA_BYTES_RE ORDER_AFTER_C UNUSED DATA_BITS_REO RDER_BEFORE_C UNUSED DATA_BYTES_RE ORDER_BEFORE UNUSED _CRC SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 314 A[17:16] data stream from JESD 204C Tx IP of FPGA or ASIC. JESDB : UNUSED Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 315 X2_I1_Q0_SWAP_ Enables swaping of I1 and Q0 samples. Useful when S=2 LINK0_MAPPER_T X1_I1_Q0_SWAP_ Enables swaping of I1 and Q0 samples. Useful when S=2 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 316 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-377. Register B8 Field Descriptions Field Type Reset Description JESD_SHORTTES short test pattern input T_INPUT0[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 317 2.4.148 Register BCh (offset = BCh) [reset = 0h] Figure 2-377. Register BCh JESD_SHORTTEST_INPUT2[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 318 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-384. Register BF Field Descriptions Field Type Reset Description JESD_SHORTTES short test pattern input T_INPUT3[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 319 2.4.155 Register C3h (offset = C3h) [reset = 0h] Figure 2-384. Register C3h JESD_SHORTTEST_INPUT5[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 320 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-391. Register C6 Field Descriptions Field Type Reset Description JESD_SHORTTES short test pattern input T_INPUT7[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 321 2.4.162 Register CAh (offset = CAh) [reset = 0h] Figure 2-391. Register CAh JESD_SHORTTEST_INPUT9[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 322 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-398. Register CD Field Descriptions Field Type Reset Description JESD_SHORTTES short test pattern input T_INPUT10[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 323 2.4.169 Register D1h (offset = D1h) [reset = 0h] Figure 2-398. Register D1h JESD_SHORTTEST_INPUT12[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 324 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-405. Register D4 Field Descriptions Field Type Reset Description JESD_SHORTTES short test pattern input T_INPUT14[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 325 2.4.176 Register E8h (offset = E8h) [reset = 0h] Figure 2-405. Register E8h CLEAR_EMB_ALIGN_LOCK_FLAG CLEAR_COMMA_ALIGN_LOCK_FLAG R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 326 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-412. Register EB Field Descriptions Field Type Reset Description CLEAR_JESD_SY clear jesd_rx_sysref monitor flag SREF_FLAG Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 327 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-415. Register EE Field Descriptions Field Type Reset Description EMB_ALIGN_LOC JESDC:emb_align_lock_lane[0:3]/[4:7]_monitor_flag K_FLAG JESDB: UNUSED COMMA_ALIGN_L JESDB:comma_align_lock_lane[0:3]/[4:7]_monitor_flag OCK_FLAG JESDC:sync_header_align_lock_lane[0:3]/[4:7]_monitor_flag SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 328 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-418. Register F1 Field Descriptions Field Type Reset Description JESD_SYSREF_T jesd_rx_sysref monitor flag X1_FLAG JESD_CLK_TX1_F jesd_rx_clk monitor flag Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 329 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-421. Register F4 Field Descriptions Field Type Reset Description JESD_SYSREF_T jesd_rx_sysref monitor flag X2_FLAG JESD_CLK_TX2_F jesd_rx_clk monitor flag SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 330 [5] = TIED to 0 [6] = serdesab_pll_loss_of_lock [7] = serdescd_pll_loss_of_lock Note: Refer to the TI application note for details on error interpretation. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 331 2.4.194 Register FBh (offset = FBh) [reset = 0h] Figure 2-423. Register FBh ALARMS_MASK[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 332 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 333 2.4.197 Register FEh (offset = FEh) [reset = 0h] Figure 2-426. Register FEh ALARMS_MASK[55:48] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 334 2.4.198 Register FFh (offset = FFh) [reset = 0h] Figure 2-427. Register FFh ALARMS_MASK[63:56] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 335 2.4.200 Register 101h (offset = 101h) [reset = 0h] Figure 2-429. Register 101h ALARMS_CLEAR[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 336 2.4.202 Register 103h (offset = 103h) [reset = 0h] Figure 2-431. Register 103h ALARMS_CLEAR[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 337 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 338 2.4.205 Register 106h (offset = 106h) [reset = 0h] Figure 2-434. Register 106h ALARMS_CLEAR[55:48] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 339 2.4.206 Register 107h (offset = 107h) [reset = 0h] Figure 2-435. Register 107h ALARMS_CLEAR[63:56] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 340 2.4.208 Register 109h (offset = 109h) [reset = 0h] Figure 2-437. Register 109h ALARMS_TO_PAP_MASK[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 341 [31]= JESDB: SRX4/8 Frame-Sync error (Ctrl-K in middle of data) JESDC: SRX4/8 Fixed ones error Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 342 2.4.212 Register 10Dh (offset = 10Dh) [reset = 0h] Figure 2-441. Register 10Dh ALARMS_TO_PAP_MASK[47:40] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 343 2.4.213 Register 10Eh (offset = 10Eh) [reset = 0h] Figure 2-442. Register 10Eh ALARMS_TO_PAP_MASK[55:48] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 344 2.4.214 Register 10Fh (offset = 10Fh) [reset = 0h] Figure 2-443. Register 10Fh ALARMS_TO_PAP_MASK[63:56] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 345 2.4.216 Register 111h (offset = 111h) [reset = 0h] Figure 2-445. Register 111h ALARMS_TO_PAP_CLEAR[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 346 2.4.218 Register 113h (offset = 113h) [reset = 0h] Figure 2-447. Register 113h ALARMS_TO_PAP_CLEAR[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 347 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 348 2.4.221 Register 116h (offset = 116h) [reset = 0h] Figure 2-450. Register 116h ALARMS_TO_PAP_CLEAR[55:48] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 349 2.4.222 Register 117h (offset = 117h) [reset = 0h] Figure 2-451. Register 117h ALARMS_TO_PAP_CLEAR[63:56] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 350 2.4.224 Register 119h (offset = 119h) [reset = 0h] Figure 2-453. Register 119h ALARMS[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 351 [31]= JESDB: SRX4/8 Frame-Sync error (Ctrl-K in middle of data) JESDC: SRX4/8 Fixed ones error Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 352 2.4.228 Register 11Dh (offset = 11Dh) [reset = 0h] Figure 2-457. Register 11Dh ALARMS[47:40] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 353 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 354 [5] = TIED to 0 [7:0] [6] = serdesab_pll_loss_of_lock [7] = serdescd_pll_loss_of_lock Note: Refer to the TI application note for details on error interpretation. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 355 2.4.234 Register 123h (offset = 123h) [reset = 0h] Figure 2-463. Register 123h ALARMS_TO_PAP[31:24] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 356 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 357 2.4.237 Register 126h (offset = 126h) [reset = 0h] Figure 2-466. Register 126h ALARMS_TO_PAP[55:48] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 358 Bit0 = JESDC: sync-header CRC error Note: Refer to the TI application note for details on error interpretation. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 359 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-473. Register 12A Field Descriptions Field Type Reset Description LANE_ERRORS_P ULSE_EXPANSIO width of pulse-expansion of lane errors from lanes[0:1]/[4:5] N_COUNT_LANE0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 360 Table 2-476. Register 12D Field Descriptions Field Type Reset Description TXD_LANE_ALAR Enable alarms from lanes to generate alarm_to_txd_pap MS_TO_PAP_EN TXC_LANE_ALAR Enable alarms from lanes to generate alarm_to_txc_pap MS_TO_PAP_EN Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 361 We can use this register along EASE_RBD_M1[7: with the rbd_counter to time the syncz assertion. TO enable this feature, we need to set lane_test_mode[1] to 1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 362 LANE1_SKEW JESDC: Measure lane1 skew from lane1 getting emb-lock to all the lanes getting emb-locks character Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 363 - select bit[0] as clk-en _CLK_P1 bit[0] - 0:DIS, 1-EN CTRL_TX1_ROOT bit[1] - select bit[0] as clk-en _CLK_P0 bit[0] - 0:DIS, 1-EN SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 364 - select bit[0] as clk-en CLK_P3 bit[0] - 0:DIS, 1-EN CTRL_TX2_DUC_ bit[1] - select bit[0] as clk-en CLK_P2 bit[0] - 0:DIS, 1-EN Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 365 - select bit[0] as clk-en CLK_P1 bit[0] - 0:DIS, 1-EN CTRL_TX2_JESD_ bit[1] - select bit[0] as clk-en CLK_P0 bit[0] - 0:DIS, 1-EN SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 366 2.4.260 Register 148h (offset = 148h) [reset = 88h] Figure 2-489. Register 148h MAPPER_SYNC_FIFO_TX1_OFFSET_S4TO2 MAPPER_SYNC_FIFO_TX1_OFFSET_S4TO4 R/W-8h R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 367 2.4.263 Register 14Ch (offset = 14Ch) [reset = 88h] Figure 2-492. Register 14Ch MAPPER_SYNC_FIFO_TX2_OFFSET_S4TO2 MAPPER_SYNC_FIFO_TX2_OFFSET_S4TO4 R/W-8h R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 368 2.4.266 Register 150h (offset = 150h) [reset = 0h] Figure 2-495. Register 150h SERDES_FIFO _PTR_SAMPL R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 369 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-500. Register 151 Field Descriptions Field Type Reset Description SERDES_FIFO_R lane0/4 fifo rd-ptr sample D_PTR_SAMPLE SERDES_FIFO_W lane0/4 fifo wr-ptr sample R_PTR_SAMPLE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 370 DE_OVR MAPPER_SYNC MAPPER_SYNC MAPPER_SYNC_FIFO_FB_MODE_ _FIFO_FB_OFF MAPPER_SYNC_FIFO_FB_OFFSET_VAL _FIFO_FB_MOD SET_OVR E_OVR RX1_ROOT_CLK_DIV_M RX1_ROOT_CLK_DIV_N_M1 RX2_ROOT_CLK_DIV_M RX2_ROOT_CLK_DIV_N_M1 FB_ROOT_CLK_DIV_M FB_ROOT_CLK_DIV_N_M1 DDC_RD_CLK_RX1_DIV_M DDC_RD_CLK_RX1_DIV_N_M1 DDC_RD_CLK_RX2_DIV_M DDC_RD_CLK_RX2_DIV_N_M1 DDC_RD_CLK_FB_DIV_M DDC_RD_CLK_FB_DIV_N_M1 JESD_CLK_RX1_DIV_M JESD_CLK_RX1_DIV_N_M1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 371 LINK0_JESDV LINK0_ILA_S_M1 LINK0_ILA_HD LINK0_CF LINK0_RES1 LINK0_RES2 LINK0_JESD_IL A_CONFIG_OV ERRIDE LINK0_K_M1 LINK0_ENABLE LINK0_DISABLE LINK0_DISABLE LINK0_NO_LAN _F_CHAR_ON_ _F_CHAR _A_CHAR E_SYNC MFEND LINK0_SYNC_F _CTR_INCR_OV LINK0_SYNC_F_CTR_INCR_OVR_VAL R_EN SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 372 LINK2_JESD_IL A_CONFIG_OV ERRIDE LINK2_K_M1 LINK2_ENABLE LINK2_DISABLE LINK2_DISABLE LINK2_NO_LAN _F_CHAR_ON_ _F_CHAR _A_CHAR E_SYNC MFEND LINK2_SYNC_F _CTR_INCR_OV LINK2_SYNC_F_CTR_INCR_OVR_VAL R_EN LINK2_JESD_TEST_SEQ_SEL LINK2_INIT_O_MF_COUNTER[7:0] LINK2_INIT_O_MF_COUNTER[12:8] LINK2_ERR_CN T_CLR LID0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 373 JESD_SYNC_STATE_LANE3 JESD_SYNC_STATE_LANE2 JESD_SYNC_STATE_LANE1 JESD_SYNC_STATE_LANE0 JESD_PREV_SYNC_STATE_LANE JESD_PREV_SYNC_STATE_LANE JESD_PREV_SYNC_STATE_LANE JESD_PREV_SYNC_STATE_LANE 101h 102h JESD_MISC_STATUS_LANE1 JESD_MISC_STATUS_LANE0 103h JESD_MISC_STATUS_LANE3 JESD_MISC_STATUS_LANE2 104h JESD_SYNC_ERR_CNT_LANE0 105h JESD_SYNC_ERR_CNT_LANE1 106h JESD_SYNC_ERR_CNT_LANE2 107h JESD_SYNC_ERR_CNT_LANE3 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 374 MONITOR_JES MONITOR_JES MONITOR_JES MONITOR_JES D_SYSREF_RX D_SYSREF_RX D_SYSREF_DIV D_SYSREF_DIV D_SYSREF_DIV D_SYSREF_DIV D_SYSREF_FB_ D_SYSREF_FB_ 131h 2_P0_MSF_RD 1_P0_MSF_RD 2_FB_P3 2_FB_P1 2_RX2_P2 2_RX1_P0 MONITOR_JES D_SYSREF_FB_ 132h P0_MSF_RD Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 375 Figure 2-499. Register 22h SYSREF_JESD_MODE R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 376 JESD_CLEAR_DA 1'b0 - No change in lane-data bit 0 - STX1/5 bit 1 - STX2/6 bit 2 - STX3/7 bit 3 - STX4/8 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 377 When 1, polarity of the RX, FB dynamic switching signal is TDD_RX_FBZ_DY inverted. N_SWITCH_INV So, then inverted behavior 0 -> RX 1 -> FB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 378 Used to control lane 3/7 sharing for system_modes that support TDD shared TDD_SHARED_DA 0 - rx/fb shared dynamically TA_SEL_LANE3 1 - rx 2 - fb Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 379 Table 2-513. Register 31 Field Descriptions Field Type Reset Description SWAP_SAMPLES_ To be set to override internal swapping logic with SPI based FB_OVR through mem_swap_samples_fb_val SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 380 Table 2-515. Register 33 Field Descriptions Field Type Reset Description Must read or write 0 FB_USE_MAPPER Not recommended to be set by the user. Should be 1 _ALIGN_B0_OVR Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 381 2.5.15 Register 34h (offset = 34h) [reset = 0h] Figure 2-511. Register 34h RX1_JESD_MODE R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 382 ADC JESD Register Map www.ti.com Table 2-516. Register 34 Field Descriptions Field Type Reset Description Must read or write 0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 383 MODE_2S_22620_IQ = 31 MODE_2S_122420_IQ_DUP = 32 MODE_2S_121640_IQ = 33 MODE_2S_22840_IQ = 34 MODE_2S_122440_IQ = 35 MODE_2S_321230_IQ_DUP = 36 MODE_2S_32830_IQ_DUP = 37 MODE_2S_32630_IQ = 38 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 384 2.5.16 Register 35h (offset = 35h) [reset = 0h] Figure 2-512. Register 35h RX2_JESD_MODE R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 385 ADC JESD Register Map www.ti.com Table 2-517. Register 35 Field Descriptions Field Type Reset Description Must read or write 0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 386 MODE_2S_22620_IQ = 31 MODE_2S_122420_IQ_DUP = 32 MODE_2S_121640_IQ = 33 MODE_2S_22840_IQ = 34 MODE_2S_122440_IQ = 35 MODE_2S_321230_IQ_DUP = 36 MODE_2S_32830_IQ_DUP = 37 MODE_2S_32630_IQ = 38 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 387 2.5.17 Register 36h (offset = 36h) [reset = 1Eh] Figure 2-513. Register 36h FB_JESD_MODE R/W-0h R/W-0h R/W-1Eh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 388 ADC JESD Register Map www.ti.com Table 2-518. Register 36 Field Descriptions Field Type Reset Description Must read or write 0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 389 MODE_2S_22620_IQ = 31 MODE_2S_122420_IQ_DUP = 32 MODE_2S_121640_IQ = 33 MODE_2S_22840_IQ = 34 MODE_2S_122440_IQ = 35 MODE_2S_321230_IQ_DUP = 36 MODE_2S_32830_IQ_DUP = 37 MODE_2S_32630_IQ = 38 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 390 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-520. Register 38 Field Descriptions Field Type Reset Description Must read or write 0 RX1_SAMPLE_CN The ovr register for RX1_SAMPLE_CNT_MAX_OVR_VAL T_MAX_OVR Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 391 2S_OVR 2S_VAL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 392 MAPPER_SYNC_FIFO_RX2_M C_FIFO_RX2_ C_FIFO_RX2_ ODE_VAL OFFSET_OVR MODE_OVR R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 393 Must read or write 0 RX1_ROOT_CLK_ M value of root divider. DIV_M Output of this divider goes to ddc and jesd clock dividers SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 394 2.5.30 Register 44h (offset = 44h) [reset = 2h] Figure 2-526. Register 44h FB_ROOT_CLK_DIV_M R/W-0h R/W-0h R/W-0h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 395 Must read or write 0 N-1 value of ddc divider. DDC_RD_CLK_RX Output of this divider, clock frequency should match the 1_DIV_N_M1 RXA/RXC interface rate SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 396 Must read or write 0 M value of ddc divider. DDC_RD_CLK_FB Output of this divider, clock frequency should match the _DIV_M FBAB/FBCD interface rate Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 397 Must read or write 0 N-1 value of jesd divider. JESD_CLK_RX1_ Output of this divider, clock frequency should match STX1/5 DIV_N_M1 rate i.e. lane _rate/40 or lane_rate/33 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 398 Must read or write 0 M value of jesd divider. JESD_CLK_FB_DI Output of this divider, clock frequency should match STX 3,4/7,8 rates i.e. lane _rate/40 or lane_rate/33 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 399 When MSB = 1, M/N divider is enabled/disabled using spi _CLK_P0 register i.e. LSB bit. LSB = 0, M/N divider disabled LSB = 1, M/N divider enabled SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 400 When MSB = 1, M/N divider is enabled/disabled using spi LK_RX2 register i.e. LSB bit. LSB = 0, M/N divider disabled LSB = 1, M/N divider enabled Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 401 Figure 2-544. Register 59h CTRL_JESD_CLK_DIV2_RX1_P CTRL_JESD_CLK_FB_P3 CTRL_JESD_CLK_FB_P1 CTRL_JESD_CLK_FB_P0 R/W-1h R/W-1h R/W-1h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 402 When MSB = 1, M/N divider is enabled/disabled using spi DIV2_FB_P1 register i.e. LSB bit. LSB = 0, M/N divider disabled LSB = 1, M/N divider enabled Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 403 SREF_MUX 1 : use rx clk Using fb clks by default RX_ADC_CLK_SY 0 : use rx clk SREF_MUX 1 : use fb clk SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 404 CFG_RX_LFS R_LOAD R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 405 Field Type Reset Description CFG_FB_LFSR_S When cfg_fb_lfsr_load is 1, this spi value is used as LFSR EED_VAL[23:16] seed for all fb M/N dividers SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 406 Type Reset Description SERDES_FIFO_R Controls STX2/6 EAD_DLY_LANE1 Fifo offset (JESD_TX to SERDES handoff) SERDES_FIFO_R Controls STX1/5 EAD_DLY_LANE0 Fifo offset (JESD_TX to SERDES handoff) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 407 Description Must read or write 0 To control STX3,4/STX7,8 LINK2_INIT_STAT 0 : JESD in non-reset state 1 : JESD is in reset state SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 408 If 1: INIT_STATE_GEA link_fifo_init_state register is inteneded for reset RBOX_SPI_OVR else: gearbox is reset with sysref aligned link_init_state. Must read or write 0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 409 Figure 2-566. Register 77h LINK0_SCR LINK0_ILA_L_M1 R/W-0h R/W-0h R/W-0h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 410 2.5.73 Register 7Ah (offset = 7Ah) [reset = 0h] Figure 2-569. Register 7Ah LINK0_ILA_M_M1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 411: Register 7Bh (Offset = 7Bh) [Reset = 0H]

    2.5.76 Register 7Dh (offset = 7Dh) [reset = 20h] Figure 2-572. Register 7Dh LINK0_JESDV LINK0_ILA_S_M1 R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 412 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-580. Register 80 Field Descriptions Field Type Reset Description LINK0_RES2 JESD link config for STX1/5 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 413 Must read or write 0 LINK0_ENABLE_F Config for STX1/5 _CHAR_ON_MFE By default, don't send f_char on multiframe_end. When 1, f_char is sen't on multiframe_end SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 414 011=repeat initial lane alignment (ILA) sequence 100=modified random pattern (modified RPAT / CRPAT) 101=scrambled jitter pattern (JSPAT) 110=repeat /K.28.7/ low freq pattern 111=send short test pattern reg data Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 415 LINK0_ERR_C NT_CLR R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 416 Description Must read or write 0 LINK1_ADJDIR JESD link config for STX2/6 LINK1_PHADJ JESD link config for STX2/6 Must read or write 0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 417 Table 2-594. Register 91 Field Descriptions Field Type Reset Description JESD link config for STX2/6 LINK1_ILA_K_M1 Used only when link1_jesd_ila_config_override is 1. Else K derived from link1_k_m1 reg SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 418 JESD link config for STX2/6 JESD link config for STX2/6 LINK1_ILA_NPRIM Used only when link1_jesd_ila_config_override is 1. E_M1 Else Nprime derived from LMFS is used. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 419 2.5.100 Register 98h (offset = 98h) [reset = 0h] Figure 2-596. Register 98h LINK1_RES2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 420 NE_SYNC N_MFEND R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 421 Figure 2-601. Register 9Fh LINK1_JESD_TEST_SEQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 422 Value has to be multiples of 8. All values cannot be handled due to assumption of frame_end and multiframe_end in a specific pattern Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 423 LINK2_ADJDIR LINK2_PHADJ R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 424 2.5.114 Register A9h (offset = A9h) [reset = 0h] Figure 2-610. Register A9h LINK2_ILA_K_M1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 425 JESD link config for STX 3,4/7,8 JESD link config for STX 3,4/7,8 LINK2_ILA_NPRIM Used only when link2_jesd_ila_config_override is 1. E_M1 Else Nprime derived from LMFS is used. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 426 2.5.121 Register B0h (offset = B0h) [reset = 0h] Figure 2-617. Register B0h LINK2_RES2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 427 NE_SYNC N_MFEND R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 428 Figure 2-622. Register B7h LINK2_JESD_TEST_SEQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 429 Value has to be multiples of 8. All values cannot be handled due to assumption of frame_end and multiframe_end in a specific pattern SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 430 2.5.132 Register BEh (offset = BEh) [reset = 2h] Figure 2-628. Register BEh LID2 R/W-0h R/W-0h R/W-0h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 431 LINK2_SYNC_FIFO_S2_TO_S1 LINK2_SYNC_FIFO_S1_TO_S2 _OFFSET _OFFSET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 432 00 - CRC 01 - FEC JESDC_ENCODIN 10 - CMD G_MODE 11 - Invalid 0 : CRC 1 : FEC 2 : CMD Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 433 6 bits corresponding to 6 command bits used in CRC and FEC JESDC_CMD[7:0] encoding. All 18 bits are used in CMD encoding is used SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 434 FEC_MASK_EN to the correct multi-block end quickly. Once locked the receiver needs to clear this bit. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 435 2.5.147 Register D4h (offset = D4h) [reset = 0h] Figure 2-643. Register D4h SCR_64B_INITVAL[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 436 Table 2-651. Register D7 Field Descriptions Field Type Reset Description SCR_64B_INITVAL 58 bit inital value used by 64b scrambler (1+x^39+x^58) [31:24] Relevant for JESD-C Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 437 Figure 2-650. Register DBh SCR_64B_INITVAL[57:56] R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 438 1 sample per clk: SD by 2 -> M=1, N=2 SD by 3 -> M=1, N=3 SD by 4 -> M=1, N=4 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 439 Figure 2-654. Register E3h FBAB_SD_CLK_DIV_N_M1 FBAB_SD_CLK_DIV_M R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 440 Must read or write 0 ALARMS_SERDES register to mask serdes_fifo_errors alarm register _FIFO_ERRORS_ Masked alarms are ored and sent to the pin MASK Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 441 [3]=STX4/8 jesd_tx_serdes_fifo error ALARMS_SERDES [2]=STX3/7 jesd_tx_serdes_fifo error _FIFO_ERRORS [1]=STX2/6 jesd_tx_serdes_fifo error [0]=STX1/5 jesd_tx_serdes_fifo error This registers are un-affected by the mask bits SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 442 2.5.167 Register F9h (offset = F9h) [reset = 0h] Figure 2-663. Register F9h JESD_INTERNAL_CTR_ON_SYNC_DEASSERT0[12:8] R/W-0h R/W-0h R/W-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 443 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-671. Register FC Field Descriptions Field Type Reset Description JESD_INTERNAL_ CTR_ON_SYNC_D multiframe counter value on sync_n deassertion at STX3/7 EASSERT2[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 444 Table 2-674. Register FF Field Descriptions Field Type Reset Description Must read or write 0 JESD_INTERNAL_ CTR_ON_SYNC_D multiframe counter value on sync_n deassertion at STX4/8 EASSERT3[12:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 445 2.5.176 Register 102h (offset = 102h) [reset = 0h] Figure 2-672. Register 102h JESD_MISC_STATUS_LANE1 JESD_MISC_STATUS_LANE0 R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 446 2.5.179 Register 105h (offset = 105h) [reset = 0h] Figure 2-675. Register 105h JESD_SYNC_ERR_CNT_LANE1 R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 447 When 1'b1 the sync error count update is stopped and capture C_ERR HOLD_JESD_STA When 1'b1 the jesd status status update is stopped and captured SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 448 2.5.185 Register 10Bh (offset = 10Bh) [reset = 0h] Figure 2-681. Register 10Bh FB_JESD_RAMPTEST_INCR FB_JESD_TEST_SIG_GEN_MODE R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 449 2.5.188 Register 10Eh (offset = 10Eh) [reset = 0h] Figure 2-684. Register 10Eh JESD_SHORT_TEST_PATTERN_INPUT1[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 450 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-692. Register 111 Field Descriptions Field Type Reset Description JESD_SHORT_TE Used when jesd_short_test_pattern_override or ST_PATTERN_INP fb_jesd_short_test_pattern_override are set UT2[15:8] ADC sample2 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 451 2.5.195 Register 115h (offset = 115h) [reset = 0h] Figure 2-691. Register 115h JESD_SHORT_TEST_PATTERN_INPUT4[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 452 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-699. Register 118 Field Descriptions Field Type Reset Description JESD_SHORT_TE Used when jesd_short_test_pattern_override or ST_PATTERN_INP fb_jesd_short_test_pattern_override are set UT6[7:0] ADC sample6 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 453 CTRL_FB_MAPPER_CLK_GATI CTRL_RX2_MAPPER_CLK_GA CTRL_RX1_MAPPER_CLK_GA TING TING R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 454 Figure 2-701. Register 120h CTRL_RX3_RX4_MSF_SIG_INV CTRL_RX2_MSF_SIG_INVALID CTRL_RX1_MSF_SIG_INVALID ALID R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 455 MAPPER_SIG_INV for rx2 mapper ALID CTRL_TDD_RX1_ When set to 2'b10, all functional data invalid is forced to zero MAPPER_SIG_INV for rx1 mapper ALID SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 456 K_DIV2_FB_P1 MONITOR_JESD_CLK_DIV2_FB_P1 register CLEAR_JESD_CL when set to 1, clears the K_DIV2_RX2_P2 MONITOR_JESD_CLK_DIV2_RX2_P2 register CLEAR_JESD_CL when set to 1, clears the K_DIV2_RX1_P0 MONITOR_JESD_CLK_DIV2_RX1_P0 register Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 457 SREF_RX2_P0 MONITOR_JESD_SYSREF_RX2_P0 register CLEAR_JESD_SY when set to 1, clears the SREF_RX1_P2 MONITOR_JESD_SYSREF_RX1_P2 register CLEAR_JESD_SY when set to 1, clears the SREF_RX1_P0 MONITOR_JESD_SYSREF_RX1_P0 register SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 458 C_RD_CLK_R C_RD_CLK_R R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 459 1 Monitors the phase 1 JESD clock of FB. MONITOR_JESD_ Can be cleared by setting the CLEAR_JESD_CLK_FB_P1 CLK_FB_P1 register to 1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 460 SYSREF_RX1_P2 CLEAR_JESD_SYSREF_RX1_P2 register to 1 Monitors the internal sysref for Rx. MONITOR_JESD_ Can be cleared by setting the SYSREF_RX1_P0 CLEAR_JESD_SYSREF_RX1_P0 register to 1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 461 SYSREF_FB_P3 CLEAR_JESD_SYSREF_FB_P3 register to 1 Monitors the internal sysref of FB. MONITOR_JESD_ Can be cleared by setting the SYSREF_FB_P1 CLEAR_JESD_SYSREF_FB_P1 register to 1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 462 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-719. Register 132 Field Descriptions Field Type Reset Description Must read or write 0 MONITOR_JESD_ SYSREF_FB_P0_ UNUSED MSF_RD Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 463 LINK_INIT_VAL_2[10:8] 407Ah LINK_INIT_VAL_3[7:0] 407Bh LINK_INIT_VAL_3[10:8] 407Ch LINK_INIT_VAL_4[7:0] 407Dh LINK_INIT_VAL_4[10:8] 4082h TIMING_UPDN_MOD_EN[1:0] 4083h TUD_UP_RATIO TUD_DN_RATIO TIMING_UPDN_MOD_EN[3:2] RX_PRBS_COU RX_PRBS_CHE RX_POLARITY_ RX_PRBS_MODE 4084h NT_RESET CK_EN FLIP SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 464 41ECh MAIN_CURSOR 41EDh POST_CURSOR PRE_CURSOR TESTMODE_RX ENTSTPGROUP VTSTGRPU_RX 41EEh 41EFh TESTMODE_RX[2:1] 41F0h RX_CTLE_BIAS0 PU_RX_ADC_L RX_CLOCKING_BIAS[4:0] 41F6h 41F7h VREF1P3VCODIV VREFVCODIV RX_CLOCKING_BIAS[6:5] 41FAh VREF_DELAY_DAC_TOP VREF_DELAY_DAC_BOT Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 465 49E9h TX_PLL_VCO_RANGE_LSB 49EAh PU_TX_PLL TX_CHARGE_PUMP_CUR TX_VCO_CURRENT 49EBh TX_PLL_N TX_REFCLK_SE 49ECh PU_TX_BANDG EN_RVDDVCO_ TX_PLL_BIAS4 PU_RVDD_TX 49EDh TEST_MUX_SE 49EEh L_B[0] 49EFh TEST_MUX_SEL_B[8:1] PU_RX_INTP_L 49F0h ANE3 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 466 FIRMWARE_DATA0[15:8] 7E02h FIRMWARE_DATA1[7:0] 7E03h FIRMWARE_DATA1[15:8] 7E04h FIRMWARE_DATA2[7:0] 7E05h FIRMWARE_DATA2[15:8] 7E06h FIRMWARE_DATA3[7:0] 7E07h FIRMWARE_DATA3[15:8] 7E08h FIRMWARE_DATA4[7:0] 7E09h FIRMWARE_DATA4[15:8] 7E0Ah FIRMWARE_DATA5[7:0] 7E0Bh FIRMWARE_DATA5[15:8] 7E0Ch FIRMWARE_DATA6[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 467 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-721. Register 4000 Field Descriptions Field Type Reset Description RX DFE Mode selector DFE_MODE 0h: 1 Tap DFE 1h: Disable DFE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 468 2.6.5 Register 4004h (offset = 4004h) [reset = 20h] Figure 2-719. Register 4004h CNTR_TARGET_PAT[7:0] R/W-20h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 469 RX_SD_THRESH_ Signal detect threshold level of format U11.11. This is an DETECT[10:8] unsigned number and each bit is equivalent to 0.4mV. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 470 2.6.12 Register 4010h (offset = 4010h) [reset = 8h] Figure 2-726. Register 4010h DFE_INIT_2[0] DFE_INIT_3 R/W-0h R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 471 2.6.16 Register 4016h (offset = 4016h) [reset = 15h] Figure 2-730. Register 4016h HF_CNTR_THRESH R/W-15h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 472 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-739. Register 4019 Field Descriptions Field Type Reset Description LF_CNTR_TARGE Low frequency component counter, MSB T_MSB[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 473 2.6.23 Register 401Dh (offset = 401Dh) [reset = 80h] Figure 2-737. Register 401Dh HF_CNTR_TARGET[15:8] R/W-80h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 474 State machine breakpoint 2 enabled when set to 1. Resume the state machine from the trapped breakpoint state: SM_CONT rising edge trigger. BP1_STATE Breakpoint 1 state number. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 475 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-749. Register 4038 Field Descriptions Field Type Reset Description OW_KP[1:0] Overwrite value for KP. Format U3.0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 476 2.6.32 Register 403Bh (offset = 403Bh) [reset = 0h] Figure 2-746. Register 403Bh OWEN_DAC_S OW_DAC_SEL R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 477 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-755. Register 4060 Field Descriptions Field Type Reset Description EYE_MARGIN_VA Eye Margin read back value. L[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 478 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-759. Register 4066 Field Descriptions Field Type Reset Description LINK_RESTART_C Readback value for the link restart counter. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 479 2.6.43 Register 4079h (offset = 4079h) [reset = 0h] Figure 2-757. Register 4079h LINK_INIT_VAL_2[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 480 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-766. Register 407C Field Descriptions Field Type Reset Description LINK_INIT_VAL_4[ Initial parameter set values 4. Used during link-up. 7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 481 Timing Loop UP direction control ratio. TUD_DN_RATIO Timing Loop DOWN direction control ratio. Timing up/down mode enable: TIMING_UPDN_M 0h: Disable OD_EN[3:2] 1h Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 482 2.6.52 Register 4087h (offset = 4087h) [reset = 0h] Figure 2-766. Register 4087h OWEN_PHASE OW_PHASE1_ACC 1_ACC R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 483 2.6.55 Register 408Eh (offset = 408Eh) [reset = 24h] Figure 2-769. Register 408Eh AGC_SETTING1[3:0] AGC_SETTING2_MSB R/W-2h R/W-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 484 Reset Description AGC_SETTING2_L 2 LSBs of the AGC setting for the third highest peaking AGC_SETTING3 The AGC setting for the fourth highest peaking Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 485 Type Reset Description RX speed select 0h: Full-rate RX_SPEED_SEL[0 4h: Half-rate 5h: Quarter-rate 6h: Eighth-rate 7h: Sixteenth-rate EDGE_THRESH Edge threshold in gray code. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 486 Field Type Reset Description PH_WAND_CLK_E Enable phase wander clock. EDGE4 Timing loop Phase 4 edge delay. EDGE3[2] Timing loop Phase 3 edge delay. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 487 2.6.68 Register 409Bh (offset = 409Bh) [reset = 0h] Figure 2-782. Register 409Bh READ_PRBS_ERR_LOW[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 488 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-791. Register 40A1 Field Descriptions Field Type Reset Description READ_PHASE Timing loop phase 1 readback value. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 489 2.6.75 Register 40A5h (offset = 40A5h) [reset = 0h] Figure 2-789. Register 40A5h READ_MRGN_CNTR[11:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 490 Read value of the RX frequency accumulator of format READ_RX_FREQ_ S11.11. Each bit represents ~0.5ppm offset error between the ERROR[7:0] incoming traffic and the PLL. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 491 SOURCE 0h: Test pattern memory 1h: PRBS generator Enables the clock source to the PRBS generator. TX_PRBS_CLOCK 0h: Disabled 1h: Enabled SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 492 2.6.84 Register 4144h (offset = 4144h) [reset = AAh] Figure 2-798. Register 4144h TX_TEST_PATTERN_LOW[7:0] R/W-AAh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 493 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-807. Register 41E9 Field Descriptions Field Type Reset Description VTSTGRPU_TX[3] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 494 Table 2-810. Register 41EC Field Descriptions Field Type Reset Description TX main-cursor setting 0h (000b) Main-cursor=MAIN-0 MAIN_CURSOR 4h (100b) Main-cursor=MAIN-0.4 2h (010b) Main-cursor=MAIN-0.8 1h (001b) Main-cursor=MAIN-1.6 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 495 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-813. Register 41EF Field Descriptions Field Type Reset Description TESTMODE_RX[2: SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 496 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-816. Register 41F7 Field Descriptions Field Type Reset Description VREF1P3VCODIV VREFVCODIV RX_CLOCKING_BI RX clocking bias. AS[6:5] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 497 Table 2-819. Register 41FC Field Descriptions Field Type Reset Description VGAVDSAT[0] Power up RX interpolator by lane. PU_RX_INTP_LAN 0h: Power down 1h: Power up SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 498 1h: Power up RX_CTLE_BIAS4 RX CTLE bias setting 4. Enables RX input. RX_INPUT_EN 0h: RX input disabled (Default) 1h: RX input enabled (Required) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 499 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-826. Register 4879 Field Descriptions Field Type Reset Description FREQ_INIT2[15:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 500 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-830. Register 487D Field Descriptions Field Type Reset Description FREQ_INIT4[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 501 2.6.114 Register 49CDh (offset = 49CDh) [reset = 80h] Figure 2-828. Register 49CDh TX_VREG_IBIAS_LANE0 TX_VREG_IBIAS_LANE1[2:1] R/W-4h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 502 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-837. Register 49D4 Field Descriptions Field Type Reset Description RX_SLICER_BIAS Controls the RX slicer bias setting for lane 3. _LANE2[0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 503 Type Reset Description RX_AGCBUFDAC_ Controls AGC output driver for lane 2. LANE1 RX_SLICER_BIAS Controls the RX slicer bias setting for lane 2. _LANE1[2:1] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 504 Mux control bit that controls the recovered clock divide. 00h: /320 (Default) REFCLK_DIV 01h: /160 (Required) 10h: Invalid. Do not use. 11h: Invalid. Do not use. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 505 Mux control bit selecting lane RX recovered clock for TX PLL. 0h: Lane 0 LANE_RCVD_CLK 1h: Lane 1 _SRC 2h: Lane 2 3h: Lane 3 OWEN_FREQ_AC C_TOP SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 506 Power up Lane 3 TX driver. PU_TX_DRV_LAN 0h: Power down 1h: Power up TEST_MODE_TX Analog test mux select bits. For Serdes debug only. VTSTPGROUP_TX Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 507 2.6.132 Register 49E8h (offset = 49E8h) [reset = 40h] Figure 2-846. Register 49E8h VRVDD_TX R/W-4h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 508 2.6.135 Register 49EBh (offset = 49EBh) [reset = 14h] Figure 2-849. Register 49EBh TX_PLL_N R/W-14h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 509 2.6.138 Register 49EEh (offset = 49EEh) [reset = 0h] Figure 2-852. Register 49EEh TEST_MUX_S EL_B[0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 510 Power up RX Lane 0 interpolator. PU_RX_INTP_LAN 0h: Power down 1h: Power up Power up RX Lane 1 interpolator. PU_RX_INTP_LAN 0h: Power down 1h: Power up Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 511 2.6.144 Register 49F6h (offset = 49F6h) [reset = 0h] Figure 2-858. Register 49F6h REFCLK_SRC _SEL R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 512 4h: 22Gbps < NRZ rate < 24Gbps 5h: 21Gbps < NRZ rate < 23Gbps 6h: 20Gbps < NRZ rate < 22Gbps 7h: 19Gbps < NRZ rate < 21Gbps Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 513 0h: PLL reference = refclk / 1 1h: PLL reference = refclk / 4 Power up RX AGC master PU_RX_AGC_MAS 0h: Power down 1h: Power up SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 514 When set, an SRAM ECC correctable error has occurred. Reading this register clears this bit. SRAM_ECC_UNC When set, an SRAM ECC uncorrectable error has occurred. Reading this register clears this bit. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 515 2.6.156 Register 701Ah (offset = 701Ah) [reset = 0h] Figure 2-870. Register 701Ah DOMAIN_RESET[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 516 0h CTLE search is not done or PHY is not up CTLE_SEARCH_D 1h CTLE search is done for lane 0 ONE_LN0 0h CTLE search is not done or PHY is not up Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 517 CTLE_SEARC CTLE_SEARC H_DISABLE_L H_DISABLE_L H_DISABLE_L H_DISABLE_L R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 518 FFF0h To reload firmware, write this register to 0xFFF0 and restart CPU by writing a value of 0xAAA and then 0x000 to the DOMAIN_RESET field in register 980D. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 519 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-886. Register 702C Field Descriptions Field Type Reset Description CMD_PARAM_OR Command Parameter / Status _STATUSB[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 520 SRAM BIST process completed. 1h: Completed. SRAM BIST passed or failed: SRAM_BIST_PAS 0h: Fail 1h: Pass ROM BIST process completed. ROM_BIST_DONE 1h: Completed. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 521 2.6.173 Register 7035h (offset = 7035h) [reset = 0h] Figure 2-887. Register 7035h ROM_BIST_OUT_LSB[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 522 When this register is used for eye diagram data, access is 0[7:0] read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 523 When this register is used for eye diagram data, access is 1[15:8] read only and the value depends on the data written to the register. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 524 When this register is used for eye diagram data, access is 3[7:0] read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 525 When this register is used for eye diagram data, access is 4[15:8] read only and the value depends on the data written to the register. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 526 When this register is used for eye diagram data, access is 6[7:0] read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 527 When this register is used for eye diagram data, access is 7[15:8] read only and the value depends on the data written to the register. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 528 When this register is used for eye diagram data, access is 9[7:0] read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 529 When this register is used for eye diagram data, access is A[15:8] read only and the value depends on the data written to the register. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 530 When this register is used for eye diagram data, access is HIGH[7:0] read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 531 When this register is used for eye diagram data, access is OW[15:8] read only and the value depends on the data written to the register. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 532 When this register is used for eye diagram data, access is read only and the value depends on the data written to the register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 533 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-927. Register 7E20 Field Descriptions Field Type Reset Description DUMMYPAGESEL dummy enables SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 534 Table 2-930. Register 10D Field Descriptions Field Type Reset Description Must read or write 0 reference divider. Need to be engaged iff ref-freq > 8X CTL_REFDIV_DIV (500Mhz). Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 535 Figure 2-927. Register 111h CTL_OUTDIV_DIV_TX R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 536 Must read or write 0 CTL_OUTDIV_MU Similar to the RX and TX. However here MSB is always 0. As X_FB the other mux already happened in tx. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 537 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-938. Register 115 Field Descriptions Field Type Reset Description Must read or write 0 CTL_OUTDIV_DIV SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 538 MACRO_OPERAND_REG7[23:16] MACRO_OPERAND_REG7[31:24] MACRO_OPERAND_REG8[7:0] MACRO_OPERAND_REG8[15:8] MACRO_OPERAND_REG8[23:16] MACRO_OPERAND_REG8[31:24] MACRO_OPERAND_REG9[7:0] MACRO_OPERAND_REG9[15:8] MACRO_OPERAND_REG9[23:16] MACRO_OPERAND_REG9[31:24] MACRO_OPERAND_REG10[7:0] MACRO_OPERAND_REG10[15:8] MACRO_OPERAND_REG10[23:16] MACRO_OPERAND_REG10[31:24] MACRO_OPERAND_REG11[7:0] MACRO_OPERAND_REG11[15:8] MACRO_OPERAND_REG11[23:16] MACRO_OPERAND_REG11[31:24] MACRO_OPERAND_REG12[7:0] MACRO_OPERAND_REG12[15:8] MACRO_OPERAND_REG12[23:16] MACRO_OPERAND_REG12[31:24] MACRO_OPERAND_REG13[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 539 MACRO_RESULT_REG2[7:0] 101h MACRO_RESULT_REG2[15:8] 102h MACRO_RESULT_REG2[23:16] 103h MACRO_RESULT_REG2[31:24] 104h MACRO_RESULT_REG3[7:0] 105h MACRO_RESULT_REG3[15:8] 106h MACRO_RESULT_REG3[23:16] 107h MACRO_RESULT_REG3[31:24] 108h MACRO_RESULT_REG4[7:0] 109h MACRO_RESULT_REG4[15:8] 10Ah MACRO_RESULT_REG4[23:16] 10Bh MACRO_RESULT_REG4[31:24] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 540 MACRO_RESULT_REG15[15:8] 136h MACRO_RESULT_REG15[23:16] 137h MACRO_RESULT_REG15[31:24] 138h MACRO_RESULT_REG16[7:0] 139h MACRO_RESULT_REG16[15:8] 13Ah MACRO_RESULT_REG16[23:16] 13Bh MACRO_RESULT_REG16[31:24] 13Ch MACRO_RESULT_REG17[7:0] 13Dh MACRO_RESULT_REG17[15:8] 13Eh MACRO_RESULT_REG17[23:16] 13Fh MACRO_RESULT_REG17[31:24] 193h MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 541 2.8.4 Register A3h (offset = A3h) [reset = 0h] Figure 2-935. Register A3h MACRO_OPERAND_REG0[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 542 Table 2-946. Register A6 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 1. Interpretation of the operand(s) in D_REG1[23:16] this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 543 2.8.11 Register AAh (offset = AAh) [reset = 0h] Figure 2-942. Register AAh MACRO_OPERAND_REG2[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 544 Table 2-953. Register AD Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 3. Interpretation of the operand(s) in D_REG3[15:8] this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 545 2.8.18 Register B1h (offset = B1h) [reset = 0h] Figure 2-949. Register B1h MACRO_OPERAND_REG4[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 546 Table 2-960. Register B4 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 5. Interpretation of the operand(s) in D_REG5[7:0] this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 547 2.8.25 Register B8h (offset = B8h) [reset = 0h] Figure 2-956. Register B8h MACRO_OPERAND_REG6[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 548 Table 2-967. Register BB Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 6. Interpretation of the operand(s) in D_REG6[31:24] this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 549 2.8.32 Register BFh (offset = BFh) [reset = 0h] Figure 2-963. Register BFh MACRO_OPERAND_REG7[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 550 Table 2-974. Register C2 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 8. Interpretation of the operand(s) in D_REG8[23:16] this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 551 2.8.39 Register C6h (offset = C6h) [reset = 0h] Figure 2-970. Register C6h MACRO_OPERAND_REG9[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 552 Table 2-981. Register C9 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 10. Interpretation of the operand(s) D_REG10[15:8] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 553 2.8.46 Register CDh (offset = CDh) [reset = 0h] Figure 2-977. Register CDh MACRO_OPERAND_REG11[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 554 Table 2-988. Register D0 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 12. Interpretation of the operand(s) D_REG12[7:0] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 555: Register D2H (Offset = D2H) [Reset = 0H]

    2.8.53 Register D4h (offset = D4h) [reset = 0h] Figure 2-984. Register D4h MACRO_OPERAND_REG13[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 556: Register D5H (Offset = D5H) [Reset = 0H]

    Table 2-995. Register D7 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 13. Interpretation of the operand(s) D_REG13[31:24] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 557: Register D9H (Offset = D9H) [Reset = 0H]

    2.8.60 Register DBh (offset = DBh) [reset = 0h] Figure 2-991. Register DBh MACRO_OPERAND_REG14[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 558 Table 2-1002. Register DE Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 15. Interpretation of the operand(s) D_REG15[23:16] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 559 2.8.67 Register E2h (offset = E2h) [reset = 0h] Figure 2-998. Register E2h MACRO_OPERAND_REG16[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 560 Table 2-1009. Register E5 Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 17. Interpretation of the operand(s) D_REG17[15:8] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 561 2.8.74 Register E9h (offset = E9h) [reset = 0h] Figure 2-1005. Register E9h MACRO_OPERAND_REG18[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 562 Table 2-1016. Register EC Field Descriptions Field Type Reset Description MACRO_OPERAN Macro operand register # 19. Interpretation of the operand(s) D_REG19[7:0] in this register are dependent on MACRO_OPCODE Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 563: Register F0H (Offset = F0H) [Reset = 0H]

    TION NOT_ALLOWE R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 564: Register F1H (Offset = F1H) [Reset = 0H]

    Field contains information about the nature of error (in case of MACRO_ERROR_ ERROR_IN_OPERAND or ERROR_IN_EXECUTION). EXTENDED_COD Interpretation of this depends on the specific E[7:0] MACRO_OPCODE that caused the error. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 565: Register F3H (Offset = F3H) [Reset = 0H]

    Field contains information about the nature of error (in case of MACRO_ERROR_ ERROR_IN_OPERAND or ERROR_IN_EXECUTION). EXTENDED_COD Interpretation of this depends on the specific E_2[15:8] MACRO_OPCODE that caused the error. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 566: Register F6H (Offset = F6H) [Reset = 0H]

    2.8.90 Register F9h (offset = F9h) [reset = 0h] Figure 2-1021. Register F9h MACRO_RESULT_REG0[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 567: Register Fah (Offset = Fah) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 1. Interpretation of the contents of this REG1[7:0] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 568: Register Fdh (Offset = Fdh) [Reset = 0H]

    2.8.97 Register 100h (offset = 100h) [reset = 0h] Figure 2-1028. Register 100h MACRO_RESULT_REG2[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 569: Register 101H (Offset = 101H) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 2. Interpretation of the contents of this REG2[31:24] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 570: Register 104H (Offset = 104H) [Reset = 0H]

    2.8.104 Register 107h (offset = 107h) [reset = 0h] Figure 2-1035. Register 107h MACRO_RESULT_REG3[31:24] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 571: Register 108H (Offset = 108H) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 4. Interpretation of the contents of this REG4[23:16] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 572: Register 10Bh (Offset = 10Bh) [Reset = 0H]

    2.8.111 Register 10Eh (offset = 10Eh) [reset = 0h] Figure 2-1042. Register 10Eh MACRO_RESULT_REG5[23:16] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 573: Register 10Fh (Offset = 10Fh) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 6. Interpretation of the contents of this REG6[15:8] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 574: Register 112H (Offset = 112H) [Reset = 0H]

    2.8.118 Register 115h (offset = 115h) [reset = 0h] Figure 2-1049. Register 115h MACRO_RESULT_REG7[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 575: Register 116H (Offset = 116H) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 8. Interpretation of the contents of this REG8[7:0] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 576: Register 119H (Offset = 119H) [Reset = 0H]

    2.8.125 Register 11Ch (offset = 11Ch) [reset = 0h] Figure 2-1056. Register 11Ch MACRO_RESULT_REG9[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 577: Register 11Dh (Offset = 11Dh) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 9. Interpretation of the contents of this REG9[31:24] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 578: Register 120H (Offset = 120H) [Reset = 0H]

    2.8.132 Register 123h (offset = 123h) [reset = 0h] Figure 2-1063. Register 123h MACRO_RESULT_REG10[31:24] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 579: Register 124H (Offset = 124H) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 11. Interpretation of the contents of this REG11[23:16] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 580: Register 128H (Offset = 128H) [Reset = 0H]

    2.8.139 Register 12Ah (offset = 12Ah) [reset = 0h] Figure 2-1070. Register 12Ah MACRO_RESULT_REG12[23:16] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 581: Register 12Ch (Offset = 12Ch) [Reset = 0H]

    Type Reset Description MACRO_RESULT_ Macro result register # 13. Interpretation of the contents of this REG13[15:8] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 582: Register 12Eh (Offset = 12Eh) [Reset = 0H]

    2.8.146 Register 131h (offset = 131h) [reset = 0h] Figure 2-1077. Register 131h MACRO_RESULT_REG14[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 583 Type Reset Description MACRO_RESULT_ Macro result register # 15. Interpretation of the contents of this REG15[7:0] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 584 2.8.153 Register 138h (offset = 138h) [reset = 0h] Figure 2-1084. Register 138h MACRO_RESULT_REG16[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 585 Type Reset Description MACRO_RESULT_ Macro result register # 16. Interpretation of the contents of this REG16[31:24] register depend on the last macro command SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 586 2.8.160 Register 13Fh (offset = 13Fh) [reset = 0h] Figure 2-1091. Register 13Fh MACRO_RESULT_REG17[31:24] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 587 The 8-bit value indicates the type of the macro MACRO_OPCODE (i.e. macro op-code). This register should be written to after all macro operand registers are written. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 588 DSA gain, so that both may be changed together LNA_BYP_EN_FB normally. In case LNA should not take effect, ext_lna_con_en_fb may be written B"00" Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 589 2.9.6 Register 7Ch (offset = 7Ch) [reset = 0h] Figure 2-1098. Register 7Ch SPI_AGC_DSA_FB_1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 590 The mask registers are in spiA page. By deault all masks are disabled. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 591 2.9.13 Register D8h (offset = D8h) [reset = 18h] Figure 2-1105. Register D8h TXA_DSA_DIG1_GAIN R/W-18h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 592 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1115. Register DC Field Descriptions Field Type Reset Description TXB_DSA_DIG1_G for band1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 593 174h SPI_AGC_DSA_B 175h LNA_BYP_EN_RXB 17Ch FDSA_OFFSET_VAL_B 17Dh FDSA_INIT_VAL_B 180h RX_SWAP_SETTING_B_1 181h RX_SWAP_SETTING_B_2 182h RX_SWAP_SETTING_B_3 SWAP_PIN_GA 183h TE_B 184h LNA_BYP_SETTING_1_RXB 185h LNA_BYP_SETTING_2_RXB 186h LNA_BYP_SETTING_3_RXB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 594 2.10.2 Register 88h (offset = 88h) [reset = 0h] Figure 2-1108. Register 88h FB_SWAP_SETTING_1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 595 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1121. Register 8C Field Descriptions Field Type Reset Description LNA_BYP_SETTIN FB LNA bypass setting for swap select of 01 G_1_FB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 596: Register D0H (Offset = D0H) [Reset = 3H]

    2.10.9 Register D0h (offset = D0h) [reset = 3h] Figure 2-1115. Register D0h GAIN_CTRL R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 597 2.10.12 Register D8h (offset = D8h) [reset = 0h] Figure 2-1118. Register D8h DSA_LNA_SW _MODE R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 598 Field Type Reset Description Enables the 0.5dB step for 8-pin mode. If not set the PIN_AGC_G6_EN resolution for 8-pin agc mode is 1dB. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 599 2.10.19 Register E4h (offset = E4h) [reset = 8h] Figure 2-1125. Register E4h TM_PKDET_CUST_EXTEND_TIME R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 600 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1138. Register ED Field Descriptions Field Type Reset Description TM_GPIO_EXIT_E enable GPIO based exit condition for absolute reliability Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 601 2.10.26 Register 125h (offset = 125h) [reset = 0h] Figure 2-1132. Register 125h LNA_BYP_EN_RXA R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 602 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1145. Register 130 Field Descriptions Field Type Reset Description RX_SWAP_SETTI Swap setting for swap select of 01 for RxA NG_A_1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 603: Register 131H (Offset = 131H) [Reset = 0H]

    2.10.33 Register 134h (offset = 134h) [reset = 0h] Figure 2-1139. Register 134h LNA_BYP_SETTING_1_RXA R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 604: Register 135H (Offset = 135H) [Reset = 0H]

    LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1152. Register 170 Field Descriptions Field Type Reset Description USE_INTAGC_FO Use the value from internal AGC for LNA bypass. R_LNA_RXB Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 605: Register 17Ch (Offset = 17Ch) [Reset = 0H]

    2.10.40 Register 17Dh (offset = 17Dh) [reset = 0h] Figure 2-1146. Register 17Dh FDSA_INIT_VAL_B R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 606 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1159. Register 182 Field Descriptions Field Type Reset Description RX_SWAP_SETTI Swap setting for swap select of 11 for RxB. NG_B_3 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 607: Register 184H (Offset = 184H) [Reset = 0H]

    2.10.47 Register 186h (offset = 186h) [reset = 0h] Figure 2-1153. Register 186h LNA_BYP_SETTING_3_RXB R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 608: Register 1Bch (Offset = 1Bch) [Reset = 0H]

    With such a configuration only a write to the register will cause change pulse generation. Mask registers apply even during gain swap. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 609: Register 1C1H (Offset = 1C1H) [Reset = 0H]

    2.10.54 Register 1C4h (offset = 1C4h) [reset = 0h] Figure 2-1160. Register 1C4h TXA_SW0_FINE TXA_DSA_INDEX_SWAP0 R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 610: Register 1C8H (Offset = 1C8H) [Reset = 0H]

    Type Reset Description TXA_SW1_FINE TxA fine gain value during swap select of 10. TXA_DSA_INDEX_ Tx DSA value during swap select of 10. SWAP1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

  • Page 611: Register 1D4H (Offset = 1D4H) [Reset = 0H]

    2.10.61 Register 211h (offset = 211h) [reset = 0h] Figure 2-1167. Register 211h MASK_DIG0_T R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 612 Reset Description TXB_SW0_FINE Fine gain value for TxB during swap select of 01. TXB_DSA_INDEX_ TxB DSA value during swap select of 01. SWAP0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 613 2.10.68 Register 224h (offset = 224h) [reset = 0h] Figure 2-1174. Register 224h TXB_DSA_DIG0_GAIN_SWAP1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 614 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1185. Register 228 Field Descriptions Field Type Reset Description TXB_DSA_DIG1_G TxB diggain1 value for swap select 10. AIN_SWAP1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 615 2.11.1 Register 100h (offset = 100h) [reset = 0h] Figure 2-1176. Register 100h ALARM_MASK_LSB_FOR_ALARM0[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 616 2.11.4 Register 103h (offset = 103h) [reset = 80h] Figure 2-1179. Register 103h ALARM_MASK_MSB_FOR_ALARM0[15:8] R/W-80h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 617 2.11.7 Register 106h (offset = 106h) [reset = 0h] Figure 2-1182. Register 106h ALARM_MASK_MSB_FOR_ALARM1[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 618 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1196. Register 110 Field Descriptions Field Type Reset Description SPI_READ_ALAR Reads the value of 32 alarms prior to mask. M_PREMASK[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 619 2.11.14 Register 114h (offset = 114h) [reset = 0h] Figure 2-1189. Register 114h SPI_READ_ALARM_BUS0[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 620 Table 2-1203. Register 117 Field Descriptions Field Type Reset Description SPI_READ_ALAR Reads the value of 32 alarms after the mask corresponding to M_BUS0[31:24] Alarm0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 621 2.11.21 Register 11Bh (offset = 11Bh) [reset = 0h] Figure 2-1196. Register 11Bh SPI_READ_ALARM_BUS1[31:24] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 622 2.11.24 Register 160h (offset = 160h) [reset = 0h] Figure 2-1199. Register 160h OBS_FUNC_SPI_CHAIN_AUTOLOAD_ERROR OBS_FUNC_SPI_CHAIN_AUTOLOAD_DONE R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 623 2.11.27 Register 171h (offset = 171h) [reset = 0h] Figure 2-1202. Register 171h PLL_REG_SPI _A_ACK R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 624 The value of the register indicates whether the global PDN pin MISC_SPI_GLOBA is overriden or not with a register L_PDN_CTRL 0 : No override with register 1 : Override with a register. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 625 _RELOAD TX_DUC_BAND 0_MIXER1_FRA 142h C_CORR_EN 200h TX_DUC_BAND1_MIXER1_NCO0_FCW[7:0] 201h TX_DUC_BAND1_MIXER1_NCO0_FCW[15:8] 202h TX_DUC_BAND1_MIXER1_NCO0_FCW[23:16] 203h TX_DUC_BAND1_MIXER1_NCO0_FCW[31:24] 204h TX_DUC_BAND1_MIXER1_NCO1_FCW[7:0] 205h TX_DUC_BAND1_MIXER1_NCO1_FCW[15:8] 206h TX_DUC_BAND1_MIXER1_NCO1_FCW[23:16] 207h TX_DUC_BAND1_MIXER1_NCO1_FCW[31:24] 210h TX_DUC_BAND1_MIXER1_NCO0_PHASE_OFFSET[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 626 TX_DUC_MIXER2_NCO0_FMULT[21:16] 3C4h TX_DUC_MIXER2_NCO1_FMULT[7:0] 3C5h TX_DUC_MIXER2_NCO1_FMULT[15:8] 3C6h TX_DUC_MIXER2_NCO1_FMULT[21:16] 400h TX_DUC_MIXER2_NCO0_FRAC_FCW_NUM[7:0] 401h TX_DUC_MIXER2_NCO0_FRAC_FCW_NUM[15:8] 402h TX_DUC_MIXER2_NCO0_FRAC_FCW_DEN[7:0] 403h TX_DUC_MIXER2_NCO0_FRAC_FCW_DEN[15:8] 404h TX_DUC_MIXER2_NCO1_FRAC_FCW_NUM[7:0] 405h TX_DUC_MIXER2_NCO1_FRAC_FCW_NUM[15:8] 406h TX_DUC_MIXER2_NCO1_FRAC_FCW_DEN[7:0] 407h TX_DUC_MIXER2_NCO1_FRAC_FCW_DEN[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 627 TX_DUAL_BAN D_COMBINER_ PAP_PWR_MET 51Dh ER_CAPTURE 51Eh TX_DUAL_BAND_COMBINER_PAP_POWER_BIAS 520h TX_DUAL_BAND_COMBINER_PAP_PWR_METER_WINDOW_COUNTER[7:0] TX_DUAL_BAND_COMBINER_PAP_PWR_METER_WINDOW_COUNTER[ 521h 11:8] TX_DUAL_BAN D_COMBINER_ 524h PAP_EN TX_PAP_DUAL_ BAND_SINGLE_ 525h BAND_EN TX_PAP_SINGLE_BAND_DUAL_BA 526h ND_DISABLE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 628 564h TX_IP_PAP_MOVING_AVERAGE_ERROR_THRESHOLD[7:0] 565h TX_IP_PAP_MOVING_AVERAGE_ERROR_THRESHOLD[11:8] TX_IP_PAP_MO 568h DE_HPF_EN TX_IP_PAP_HP F_MODE_NO_A 569h 56Ah TX_IP_PAP_HPF_SAMPLES TX_IP_PAP_PW 56Ch R_METER_EN TX_IP_PAP_PW R_METER_CAP 56Dh TURE 56Eh TX_IP_PAP_POWER_BIAS 570h TX_IP_PAP_MOVING_AVERAGE_PWR_COUNTER[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 629 _PAP_MA_PWR _AVG_BAND0[1 5AAh 5B0h TX_IP_PAP_MA_PWR_AVG_BAND1[7:0] 5B1h TX_IP_PAP_MA_PWR_AVG_BAND1[15:8] TX_IP_PAP_MA _PWR_AVG_BA 5B2h ND1[16] 5B4h TX_IP_PAP_MA_ACCU_TH_BAND1[7:0] TX_IP_PAP_MA _ACCU_TH_BA 5B5h ND1[8] 5B6h TX_IP_PAP_HPF_ACCU_TH_BAND1[7:0] TX_IP_PAP_HP F_ACCU_TH_B 5B7h AND1[8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 630 It is highly recommended that the System Configuration Macros be used. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 631 2.12.5 Register 47h (offset = 47h) [reset = 0h] Figure 2-1208. Register 47h TX_DUC_MIXE R1_MODE_CO NFIG2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 632 2.12.7 Register 60h (offset = 60h) [reset = 0h] Figure 2-1210. Register 60h TX_DUC_ASYNC_FIFO_CONFIG0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 633 TX DUC FIFO Configuration1. Value dependent on TX_DUC_FIFO_C interplation factor, DAC rate, etc. ONFIG1 Optimal value automatically determined if System Configuration Macros are used. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 634 TX DUC FIFO Configuration4. Value dependent on TX_DUC_FIFO_C interplation factor, DAC rate, etc. ONFIG4 Optimal value automatically determined if System Configuration Macros are used. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 635 The System Configuration Macros automatically and optimally MIXER1_NCO0_F partition the overall center frequency between Mixer1 and CW[15:8] Mixer2, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 636 The System Configuration Macros automatically and optimally MIXER1_NCO1_F partition the overall center frequency between Mixer1 and CW[7:0] Mixer2, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 637 The System Configuration Macros automatically and optimally MIXER1_NCO1_F partition the overall center frequency between Mixer1 and CW[31:24] Mixer2, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 638 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1240. Register 114 Field Descriptions Field Type Reset Description TX_DUC_BAND0_ MIXER1_NCO1_P Offset phase for nco1 of band0 in Mixer 1 HASE_OFFSET[7: Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 639 Type Reset Description TX_DUC_BAND0_ MIXER1_NCO0_F Numerator of the fractional fequency control word for nco0 of RAC_FCW_NUM[1 band0 in Mixer 1. Signed number. 5:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 640 Field Type Reset Description TX_DUC_BAND0_ MIXER1_NCO1_F Numerator of the fractional fequency control word for nco1 of RAC_FCW_NUM[7 band0 in Mixer 1. Signed number. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 641 Field Type Reset Description TX_DUC_BAND0_ MIXER1_NCO1_F Denominator of the fractional fequency control word for nco1 RAC_FCW_DEN[1 of band0 in Mixer1. Unsigned number. 5:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 642 Table 2-1252. Register 142 Field Descriptions Field Type Reset Description TX_DUC_BAND0_ Enable fractional FCW mode in the Mixer1 Band0 NCO MIXER1_FRAC_C 0 : Disabled ORR_EN 1 : Enabled Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 643 The System Configuration Macros automatically and optimally MIXER1_NCO0_F partition the overall center frequency between Mixer1 and CW[23:16] Mixer2, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 644 The System Configuration Macros automatically and optimally MIXER1_NCO1_F partition the overall center frequency between Mixer1 and CW[15:8] Mixer2, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 645 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1261. Register 210 Field Descriptions Field Type Reset Description TX_DUC_BAND1_ MIXER1_NCO0_P Offset phase for nco0 of Band1 in Mixer 1 HASE_OFFSET[7: SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 646 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1264. Register 215 Field Descriptions Field Type Reset Description TX_DUC_BAND1_ MIXER1_NCO1_P Offset phase for nco1 of Band1 in Mixer 1 HASE_OFFSET[15 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 647 Table 2-1267. Register 222 Field Descriptions Field Type Reset Description TX_DUC_BAND1_ MIXER1_NCO0_F Denominator of the fractional fequency control word for nco0 RAC_FCW_DEN[7: of Band1 in Mixer1. Unsigned number. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 648 Type Reset Description TX_DUC_BAND1_ MIXER1_NCO1_F Numerator of the fractional fequency control word for nco1 of RAC_FCW_NUM[1 Band1 in Mixer 1. Signed number. 5:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 649 A 0-1-0 sequence on this bit can be used to force a re-load of MIXER1_NCO0_F the FCW in the Band1 nco0 in Mixer1. Will break phase CW_FORCE_REL coherence. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 650 Table 2-1276. Register 30C Field Descriptions Field Type Reset Description Nyquist select (even/odd) for the Inverse SINC filter. TX_DUC_ISINC_N 0: Nyquist 2 YQ_SEL 1: Nyquist 1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 651 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1279. Register 31C Field Descriptions Field Type Reset Description Enable DAC data dither addition TX_DUC_DAC_DI 0: Disable THER_CONFIG0 1: Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 652 Frequency shift control for the DAC data dither signal. Valid TX_DUC_DAC_DI range of values 0 to 8. THER_FCW0 Value of k: frequency shift of k*Fdac/16 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 653 TX_DUC_MIXER2 The System Configuration Macros automatically and optimally _NCO0_FCW[23:1 partition the overall center frequency between Mixer1 and Mixer2, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 654 TX_DUC_MIXER2 The System Configuration Macros automatically and optimally _NCO1_FCW[15:8] partition the overall center frequency between Mixer1 and Mixer2, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 655 2.12.77 Register 391h (offset = 391h) [reset = 0h] Figure 2-1280. Register 391h TX_DUC_MIXER2_NCO0_PHASE_OFFSET[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 656 0 and Fdac/16. The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 657 0 and Fdac/16. The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 658 Table 2-1301. Register 400 Field Descriptions Field Type Reset Description TX_DUC_MIXER2 Numerator of the fractional fequency control word for nco0 in _NCO0_FRAC_FC Mixer 2. Signed number. W_NUM[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 659 2.12.90 Register 404h (offset = 404h) [reset = 0h] Figure 2-1293. Register 404h TX_DUC_MIXER2_NCO1_FRAC_FCW_NUM[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 660 Table 2-1308. Register 407 Field Descriptions Field Type Reset Description TX_DUC_MIXER2 Denominator of the fractional fequency control word for nco1 _NCO1_FRAC_FC in Mixer2. Unsigned number. W_DEN[15:8] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 661 1: Power down _PDN The System Configuration Macros optimally power down different unused sections of the DUC, hence their use is strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 662 Table 2-1314. Register 501 Field Descriptions Field Type Reset Description Disable multiplication of the data by ramp when PA Protection TX_PAP_RAMP_D triggers. ISABLE 0: Don't disable 1: Disable Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 663 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1317. Register 504 Field Descriptions Field Type Reset Description TX_PAP_RAMP_M Data input to PA protection ramp multiplier on selecting ULT_DATA[7:0] tx_pap_ramp_mult_data_mode==0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 664 The averaging count is in the range 16 to 128 samples TX_DUAL_BAND_ according to the configuration: COMBINER_PAP_ 0:16: MOVING_AVERAG 1:32: E_SAMPLES 2:64: 3:128: Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 665 2.12.108 Register 514h (offset = 514h) [reset = 0h] Figure 2-1311. Register 514h TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ERROR_THRESHOLD[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 666 1,1). The threshold can be programmed in the range 0 to 512. R_THRESHOLD[7: The threshold is interpreted as programmed_value/256. For example, value of 256 implies the envelope threshold = 1. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 667 2.12.113 Register 519h (offset = 519h) [reset = 0h] Figure 2-1316. Register 519h TX_DUAL_BAN D_COMBINER _PAP_MODE_ HPF_NO_AVG R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 668 2.12.115 Register 51Ch (offset = 51Ch) [reset = 0h] Figure 2-1318. Register 51Ch TX_DUAL_BAN D_COMBINER _PAP_PWR_M ETER_EN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 669 2.12.118 Register 520h (offset = 520h) [reset = 0h] Figure 2-1321. Register 520h TX_DUAL_BAND_COMBINER_PAP_PWR_METER_WINDOW_COUNTER[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 670 2.12.121 Register 525h (offset = 525h) [reset = 0h] Figure 2-1324. Register 525h TX_PAP_DUAL _BAND_SINGL E_BAND_EN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 671 2.12.124 Register 52Ch (offset = 52Ch) [reset = 0h] Figure 2-1327. Register 52Ch TX_PAP_ALARM_CLR R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 672 2.12.127 Register 531h (offset = 531h) [reset = 0h] Figure 2-1330. Register 531h TX_PAP_RAMP_AMPLITUDE_UPDATE_CYCLES R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 673 Table 2-1345. Register 536 Field Descriptions Field Type Reset Description TX_PAP_ATTENU Ramp down step size ranges from 1 to 127 in both cosine and ATION_STEP_SIZ linear mode. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 674 2.12.134 Register 53Bh (offset = 53Bh) [reset = 0h] Figure 2-1337. Register 53Bh TX_PAP_CHAIN_DELAY_RAMP_UP[11:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 675 Field Type Reset Description TX_PAP_GAIN_ST Ramp up step size ranges from 1 to 127 in both cosine and EP_SIZE linear ramp up modes. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 676 2.12.141 Register 548h (offset = 548h) [reset = 0h] Figure 2-1344. Register 548h TX_PAP_AMPL ITUDE_MODE_ R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 677 2.12.144 Register 54Eh (offset = 54Eh) [reset = 1Bh] Figure 2-1347. Register 54Eh TX_PAP_OTHER_TX_PAP_ALARM_MASK[7:0] R/W-1Bh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 678 PAP can also be triggered based on saturation of signal in the TX_PAP_EN_OVE Tx digital datapath. Enable saturation or overranging based R_RANGE_WIND_ PAP trigger. COUNTER 0:Disable: 1:Enable: Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 679 2.12.150 Register 557h (offset = 557h) [reset = 0h] Figure 2-1353. Register 557h TX_PAP_OVER_RANGE_ERROR_THRESHOLD[11:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 680 2.12.153 Register 55Ch (offset = 55Ch) [reset = 0h] Figure 2-1356. Register 55Ch TX_PAP_OTHER_TX_PAP_ALARM_STATUS[7:0] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 681 [7]: Saturation Overflow Alarm _STATUS[7:0] bit [8]: Dual/Single band Alarm bit [9]: PAP dual band combiner alarm bit[10]: FW/SPI triggered alarm Remaining: Unused SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 682 2.12.158 Register 561h (offset = 561h) [reset = 0h] Figure 2-1361. Register 561h TX_IP_PAP_MOVING_AVERAG E_SAMPLES R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 683 2.12.161 Register 564h (offset = 564h) [reset = 0h] Figure 2-1364. Register 564h TX_IP_PAP_MOVING_AVERAGE_ERROR_THRESHOLD[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 684 2.12.164 Register 569h (offset = 569h) [reset = 0h] Figure 2-1367. Register 569h TX_IP_PAP_H PF_MODE_NO _AVG R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 685 The length of the window is programmed in the TX_IP_PAP_PWR_ register tx_ip_pap_moving_average_pwr_counter. This METER_EN regsiter controls the TX-JESD interface power meter enable. 0 : Disable 1 : Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 686 2.12.170 Register 571h (offset = 571h) [reset = 0h] Figure 2-1373. Register 571h TX_IP_PAP_MOVING_AVERAGE_PWR_COUNTER[11:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 687 2.12.173 Register 576h (offset = 576h) [reset = 0h] Figure 2-1376. Register 576h TX_PAP_HPF_ERROR_THRESHOLD[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 688 0 to 512. The 7:0] threshold is interpreted as programmed_value/256. For example, value of 256 implies the envelope threshold = 1. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 689 2.12.178 Register 57Dh (offset = 57Dh) [reset = 0h] Figure 2-1381. Register 57Dh TX_IP_PAP_HPF_WINDOW_COUNTER[11:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 690 0 to 2^12-1. The error accumulation counter is programmable with value in the range 1 to 2^12-1. The error window counter is programmed in the register tx_ip_pap_hpf_window_counter Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 691 In dual band combiner PAP high pass filter mode, averaging AND_COMBINER_ samples update pulse. A 0->1->0 transition will update the HPF_UPDATE_SA sample config. MPLES SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 692 Value 1 = trigger, 0 = notrigger. AND_COMBINER_ bit [0] = Moving average mode DET_UNMASK_ST bit [1] = High pass filter mode ATUS bit [2] = Reserved Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 693 0 = nomask. TX_IP_PAP_DET_ bit [0] = Moving average mode ALARM_MASK bit [1] = High pass filter mode bit [2] = Reserved SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 694 2.12.191 Register 591h (offset = 591h) [reset = 0h] Figure 2-1394. Register 591h TX_IP_PAP_DET_UNMASK_STATUS R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 695 2.12.194 Register 597h (offset = 597h) [reset = 2Ch] Figure 2-1397. Register 597h TX_PAP_DYN_OUT_PULSE_EXTENSION[15:8] R/W-2Ch LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 696 Field Type Reset Description TX_IP_PAP_MA_P Input PAP band0 power detection module average power WR_AVG_BAND0[ output. The linear scale value is interpreted as read_value/2^16 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 697 2.12.201 Register 5A9h (offset = 5A9h) [reset = 0h] Figure 2-1404. Register 5A9h TX_PAP_MEMIN_PAP_MA_PWR_AVG_BAND0[15:8] R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 698 Type Reset Description TX_IP_PAP_MA_P Input PAP band1 power detection module average power WR_AVG_BAND1[ output. The linear scale value is interpreted as 15:8] read_value/2^16 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 699 TX_IP_PAP_MA_A Input PAP band1 moving average accumulator threshold for CCU_TH_BAND1[8 the envelope of the signal (sqrt(I^2+Q^2)). The linear value is interpreted as programmed_value/2^8 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 700 Table 2-1424. Register 5B7 Field Descriptions Field Type Reset Description TX_IP_PAP_HPF_ Input PAP band1 high pass filter accumulator threshold. The ACCU_TH_BAND1 linear value is interpreted as programmed_value/2^8. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 701 RX_DDC_BAND0_DIG_GAIN_INDEX 1A0h RX_DDC_BAND1_NCO0_FCW[7:0] 1A1h RX_DDC_BAND1_NCO0_FCW[15:8] 1A2h RX_DDC_BAND1_NCO0_FCW[23:16] 1A3h RX_DDC_BAND1_NCO0_FCW[31:24] 1A4h RX_DDC_BAND1_NCO1_FCW[7:0] 1A5h RX_DDC_BAND1_NCO1_FCW[15:8] 1A6h RX_DDC_BAND1_NCO1_FCW[23:16] 1A7h RX_DDC_BAND1_NCO1_FCW[31:24] 1E0h RX_DDC_BAND1_NCO0_PHASE_OFFSET[7:0] 1E1h RX_DDC_BAND1_NCO0_PHASE_OFFSET[15:8] 1E2h RX_DDC_BAND1_NCO1_PHASE_OFFSET[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 702 RX_AGC_SMALL_STEP_DECAY_WIN_LEN[15:8] 422h RX_AGC_SMALL_STEP_DECAY_WIN_LEN[23:16] 424h RX_AGC_PWR_DET_ATTACK_WIN_LEN 425h RX_AGC_PWRDET_DECAY_WIN_LEN 428h RX_AGC_LNA_RF_DET_ATTACK_WIN_LEN[7:0] 429h RX_AGC_LNA_RF_DET_ATTACK_WIN_LEN[15:8] 42Ah RX_AGC_LNA_RF_DET_ATTACK_WIN_LEN[23:16] 42Ch RX_AGC_BIG_STEP_ATTACK_SIG_TH[7:0] 42Dh RX_AGC_BIG_STEP_ATTACK_SIG_TH[11:8] 430h RX_AGC_SMALL_STEP_ATTACK_SIG_TH[7:0] 431h RX_AGC_SMALL_STEP_ATTACK_SIG_TH[11:8] 434h RX_AGC_BIG_STEP_DECAY_SIG_TH[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 703 RX_AGC_DEF_ LNA_BYP_VAL_ 49Eh 49Fh RX_AGC_DEF_DVGA_ATTN 4A0h RX_AGC_MAX_ATTN 4A1h RX_AGC_MIN_ATTN 4A2h RX_AGC_MAX_DVGA_ATTN 4A3h RX_AGC_MIN_DVGA_ATTN RX_AGC_RESE RX_AGC_DECA RX_AGC_ATTA T_LOOP_AT_SI Y_DETS_RESE CK_DETS_RES 4A4h G_INVALID T_AT_RX_ON ET_AT_RX_ON SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 704 RX_AGC_BAND0_LNA_GAIN12[10:8] 4D6h RX_AGC_BAND0_LNA_GAIN13[7:0] 4D7h RX_AGC_BAND0_LNA_GAIN13[10:8] 4D8h RX_AGC_BAND0_LNA_GAIN14[7:0] 4D9h RX_AGC_BAND0_LNA_GAIN14[10:8] 4DAh RX_AGC_BAND0_LNA_GAIN15[7:0] 4DBh RX_AGC_BAND0_LNA_GAIN15[10:8] 4DCh RX_AGC_BAND0_LNA_GAIN16[7:0] 4DDh RX_AGC_BAND0_LNA_GAIN16[10:8] 4DEh RX_AGC_BAND0_LNA_GAIN17[7:0] 4DFh RX_AGC_BAND0_LNA_GAIN17[10:8] 4E0h RX_AGC_BAND0_LNA_GAIN18[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 705 RX_AGC_BAND1_LNA_GAIN8[10:8] 50Eh RX_AGC_BAND1_LNA_GAIN9[7:0] 50Fh RX_AGC_BAND1_LNA_GAIN9[10:8] 510h RX_AGC_BAND1_LNA_GAIN10[7:0] 511h RX_AGC_BAND1_LNA_GAIN10[10:8] 512h RX_AGC_BAND1_LNA_GAIN11[7:0] 513h RX_AGC_BAND1_LNA_GAIN11[10:8] 514h RX_AGC_BAND1_LNA_GAIN12[7:0] 515h RX_AGC_BAND1_LNA_GAIN12[10:8] 516h RX_AGC_BAND1_LNA_GAIN13[7:0] 517h RX_AGC_BAND1_LNA_GAIN13[10:8] 518h RX_AGC_BAND1_LNA_GAIN14[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 706 RX_AGC_BAND0_LNA_PHASE2[7:0] RX_AGC_BAND0_LNA_PHASE2[9: 541h 542h RX_AGC_BAND0_LNA_PHASE3[7:0] RX_AGC_BAND0_LNA_PHASE3[9: 543h 544h RX_AGC_BAND0_LNA_PHASE4[7:0] RX_AGC_BAND0_LNA_PHASE4[9: 545h 546h RX_AGC_BAND0_LNA_PHASE5[7:0] RX_AGC_BAND0_LNA_PHASE5[9: 547h 548h RX_AGC_BAND0_LNA_PHASE6[7:0] RX_AGC_BAND0_LNA_PHASE6[9: 549h 54Ah RX_AGC_BAND0_LNA_PHASE7[7:0] RX_AGC_BAND0_LNA_PHASE7[9: 54Bh Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 707 56Bh 56Ch RX_AGC_BAND0_LNA_PHASE24[7:0] RX_AGC_BAND0_LNA_PHASE24[9 56Dh 56Eh RX_AGC_BAND0_LNA_PHASE25[7:0] RX_AGC_BAND0_LNA_PHASE25[9 56Fh 570h RX_AGC_BAND0_LNA_PHASE26[7:0] RX_AGC_BAND0_LNA_PHASE26[9 571h 572h RX_AGC_BAND0_LNA_PHASE27[7:0] RX_AGC_BAND0_LNA_PHASE27[9 573h 574h RX_AGC_BAND0_LNA_PHASE28[7:0] RX_AGC_BAND0_LNA_PHASE28[9 575h 576h RX_AGC_BAND0_LNA_PHASE29[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 708 595h 596h RX_AGC_BAND1_LNA_PHASE13[7:0] RX_AGC_BAND1_LNA_PHASE13[9 597h 598h RX_AGC_BAND1_LNA_PHASE14[7:0] RX_AGC_BAND1_LNA_PHASE14[9 599h 59Ah RX_AGC_BAND1_LNA_PHASE15[7:0] RX_AGC_BAND1_LNA_PHASE15[9 59Bh 59Ch RX_AGC_BAND1_LNA_PHASE16[7:0] RX_AGC_BAND1_LNA_PHASE16[9 59Dh 59Eh RX_AGC_BAND1_LNA_PHASE17[7:0] RX_AGC_BAND1_LNA_PHASE17[9 59Fh 5A0h RX_AGC_BAND1_LNA_PHASE18[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 709 TE_DET_STATU 5C4h 5D0h RX_AGC_AVG_PWR_DET_SEEN[7:0] 5D1h RX_AGC_AVG_PWR_DET_SEEN[15:8] 5D4h RX_AGC_DIG_DET_NUM_HITS_SEEN[7:0] 5D5h RX_AGC_DIG_DET_NUM_HITS_SEEN[15:8] 5D6h RX_AGC_DIG_DET_NUM_HITS_SEEN[23:16] RX_AGC_USE_ ALL_DETECTO RS_AS_ATTAC 5DCh RX_AGC_REST 5E0h ART_MAX_MIN 5E4h RX_AGC_MAX_ATTN_USED 5E5h RX_AGC_MIN_ATTN_USED SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 710 6D5h RX_ALC_DEC_ RX_ALC_DEC_SHIFT_FORCE_VAL 6D6h SHIFT_FORCE 710h RX_DDC_PROG_DELAY RX_DDC_PROG _DELAY_BYPAS 711h RX_DDC_ROOT 740h _CLOCK_GATE 770h RX_DDC_PDN RX_DDC_PRE_ 771h DECIM_PDN RX_DDC_DECI 772h M_PDN 773h RX_AGC_PDN Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 711 2.13.3 Register 42h (offset = 42h) [reset = 0h] Figure 2-1415. Register 42h RX_DDC_BAN DS_CONFIG R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 712 Reset Description RX DDC FIFO Configuration0. Value dependent on RX_DDC_FIFO_C decimation factor. Optimal value automatically determined if ONFIG0 System Configuration Macros are used. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 713 2.13.10 Register 60h (offset = 60h) [reset = 44h] Figure 2-1422. Register 60h RX_DDC_ASYNC_FIFO_CONFIG0 R/W-44h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 714 Table 2-1438. Register A0 Field Descriptions Field Type Reset Description RX_DDC_BAND0_ Frequency control word (FCW) for nco0 of band0. NCO0_FCW[7:0] The System Configuration Macros automatically configure this. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 715 2.13.17 Register A4h (offset = A4h) [reset = 0h] Figure 2-1429. Register A4h RX_DDC_BAND0_NCO1_FCW[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 716 Table 2-1445. Register A7 Field Descriptions Field Type Reset Description RX_DDC_BAND0_ Frequency control word (FCW) for nco1 of band0. NCO1_FCW[31:24] The System Configuration Macros automatically configure this. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 717 2.13.24 Register E3h (offset = E3h) [reset = 0h] Figure 2-1436. Register E3h RX_DDC_BAND0_NCO1_PHASE_OFFSET[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 718 2.13.27 Register 102h (offset = 102h) [reset = 0h] Figure 2-1439. Register 102h RX_DDC_BAND0_NCO0_FMULT[21:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 719 2.13.30 Register 106h (offset = 106h) [reset = 0h] Figure 2-1442. Register 106h RX_DDC_BAND0_NCO1_FMULT[21:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 720 2.13.33 Register 142h (offset = 142h) [reset = 0h] Figure 2-1445. Register 142h RX_DDC_BAND0_NCO0_FRAC_FCW_DEN[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 721 Numerator of the fractional fequency control word for nco1of RX_DDC_BAND0_ band0. Signed number. NCO1_FRAC_FC System Configuration macros compute and configure this W_NUM[15:8] automatically and hence are strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 722 A value of G maps to a gain of (0.5G - 2.5) dB, yielding a range from -2.5 dB to +21 dB in 0.5 dB steps. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 723 2.13.43 Register 1A3h (offset = 1A3h) [reset = 0h] Figure 2-1455. Register 1A3h RX_DDC_BAND1_NCO0_FCW[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 724 Table 2-1471. Register 1A6 Field Descriptions Field Type Reset Description RX_DDC_BAND1_ Frequency control word (FCW) for nco1 of band1. NCO1_FCW[23:16] The System Configuration Macros automatically configure this. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 725 2.13.50 Register 1E2h (offset = 1E2h) [reset = 0h] Figure 2-1462. Register 1E2h RX_DDC_BAND1_NCO1_PHASE_OFFSET[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 726 2.13.53 Register 201h (offset = 201h) [reset = 0h] Figure 2-1465. Register 201h RX_DDC_BAND1_NCO0_FMULT[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 727 2.13.56 Register 205h (offset = 205h) [reset = 0h] Figure 2-1468. Register 205h RX_DDC_BAND1_NCO1_FMULT[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 728 2.13.59 Register 241h (offset = 241h) [reset = 0h] Figure 2-1471. Register 241h RX_DDC_BAND1_NCO0_FRAC_FCW_NUM[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 729 Numerator of the fractional fequency control word for nco1of RX_DDC_BAND1_ band1. Signed number. NCO1_FRAC_FC System Configuration macros compute and configure this W_NUM[7:0] automatically and hence are strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 730 Denominator of the fractional fequency control word for nco1 RX_DDC_BAND1_ of band1. Unsigned number. NCO1_FRAC_FC System Configuration macros compute and configure this W_DEN[15:8] automatically and hence are strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 731 0 : Disable 1 : Enable Use digital bigstep attack detector for AGC control loop RX_AGC_BIG_ST 0 : Disable EP_ATTACK_EN 1 : Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 732 _DET_EN ACK_DET_EN _DET_EN R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 733 Table 2-1497. Register 408 Field Descriptions Field Type Reset Description RX_AGC_BIG_ST Gain step when Digital big step attack is triggered. 0.5 dB step EP_ATTACK_STE size. P_SIZE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 734 2.13.76 Register 40Ch (offset = 40Ch) [reset = 2h] Figure 2-1488. Register 40Ch RX_AGC_PWR_ATTACK_STEP_SIZE R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 735 Table 2-1504. Register 414 Field Descriptions Field Type Reset Description RX_AGC_BIG_ST Digital big step attack det window length. Max supported EP_ATTACK_WIN length is 2^24 - 2. _LEN[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 736 2.13.83 Register 419h (offset = 419h) [reset = 0h] Figure 2-1495. Register 419h RX_AGC_SMALL_STEP_ATTACK_WIN_LEN[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 737 Table 2-1511. Register 41D Field Descriptions Field Type Reset Description RX_AGC_BIG_ST Digital big step decay det window length. Max supported EP_DECAY_WIN_ length is 2^24 - 2. LEN[15:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 738 2.13.90 Register 422h (offset = 422h) [reset = 0h] Figure 2-1502. Register 422h RX_AGC_SMALL_STEP_DECAY_WIN_LEN[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 739 Table 2-1518. Register 428 Field Descriptions Field Type Reset Description RX_AGC_LNA_RF LNA RF attack det window length. Max supported length is _DET_ATTACK_W 2^24 - 2. IN_LEN[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 740 2.13.97 Register 42Dh (offset = 42Dh) [reset = 3h] Figure 2-1509. Register 42Dh RX_AGC_BIG_STEP_ATTACK_SIG_TH[11:8] R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 741 Table 2-1525. Register 434 Field Descriptions Field Type Reset Description RX_AGC_BIG_ST Signal threshold for digital big step decay detector, in 0.12 EP_DECAY_SIG_T unsigned format H[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 742 2.13.104 Register 43Ch (offset = 43Ch) [reset = 10h] Figure 2-1516. Register 43Ch RX_AGC_PWR_DET_ATTACK_TH[7:0] R/W-10h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 743 Threshold for power decay detector, in 0.16 unsigned format. ET_DECAY_TH[15 Power threshold in dB will be 10*log (Th/2^16). A full scale sine-wave corresponds to -3 dB power. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 744 2.13.111 Register 454h (offset = 454h) [reset = 0h] Figure 2-1523. Register 454h RX_AGC_SMALL_STEP_ATTACK_NUM_HITS[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 745 Table 2-1539. Register 458 Field Descriptions Field Type Reset Description RX_AGC_BIG_ST EP_DECAY_NUM_ Number of Hits threshold for digital big step decay detector. HITS[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 746 2.13.118 Register 45Dh (offset = 45Dh) [reset = 0h] Figure 2-1530. Register 45Dh RX_AGC_SMALL_STEP_DECAY_NUM_HITS[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 747 LNA RF attack det threshold. If Number of hits is greater than _DET_ATTACK_N this, detector is triggered. Note that per clock we may get up UM_HITS[15:8] to 8 hits. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 748 2.13.125 Register 471h (offset = 471h) [reset = 0h] Figure 2-1537. Register 471h RX_AGC_BAND0_DECAY_NUM_HITS[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 749 Table 2-1553. Register 479 Field Descriptions Field Type Reset Description RX_AGC_BAND1_ Number of Hits threshold digital band1 detector in decay DECAY_NUM_HIT mode. S[15:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 750 Max supported length is 2^24 - 2. Y_WIN_LEN[15:8] Window length is defined in terms of band detector tap-off point clock rate. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 751 2^23. Supported length is only upto 2^23. Y_WIN_LEN Window length is defined in terms of band detector tap-off point clock rate. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 752 Table 2-1562. Register 494 Field Descriptions Field Type Reset Description Dual Band AGC feature enable RX_AGC_DUALBA 0 : Disable ND_EN 1 : Enable Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 753 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1565. Register 49A Field Descriptions Field Type Reset Description Freeze AGC RX_AGC_FREEZE 0 : Disable 1 : Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 754 Default LNA bypass value for Band1. Applicable only if RX_AGC_DEF_LN rx_agc_dualband_en is made high A_BYP_VAL_B1 0 : LNA enabled 1 : LNA bypassed Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 755 2.13.147 Register 4A2h (offset = 4A2h) [reset = 3Eh] Figure 2-1559. Register 4A2h RX_AGC_MAX_DVGA_ATTN R/W-3Eh LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 756 2.13.150 Register 4A6h (offset = 4A6h) [reset = 1h] Figure 2-1562. Register 4A6h RX_AGC_RES ET_DETS_GAI N_CHANGE R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 757 LNA gain margin to be used for reenabling the LNA. Provides RX_AGC_EXT_LN additional hysterisis on top of the attack and decay hysterisis. A_GAIN_MARGIN Resolution in 0.5 dB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 758 2.13.156 Register 4AEh (offset = 4AEh) [reset = 40h] Figure 2-1568. Register 4AEh RX_AGC_PIN_2_SELECT_BITS[7:0] R/W-40h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 759 Bit 5 --> Bigstep decay Bit 4 --> Small step decay Bit 3 --> Dig pwr attack Bit 2 --> Dig pwr decay Bit 1 --> Absolute reliability Bit 0 --> Relative reliability SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 760 2.13.161 Register 4B3h (offset = 4B3h) [reset = 10h] Figure 2-1573. Register 4B3h RX_AGC_PIN_4_SELECT_BITS[15:8] R/W-10h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 761 Number of clock cycles (in terms of Fs/8) by which a high(one) EXPANSION_COU should be extended before being sent on the pins. NT[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 762 2.13.168 Register 4BCh (offset = 4BCh) [reset = 0h] Figure 2-1580. Register 4BCh RX_AGC_BAND0_LNA_GAIN0[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 763 LNA Gain for Band0 for temp index 1 in case of External LNA RX_AGC_BAND0_ Control , Gain for DVGA Index 1 in case of External DVGA LNA_GAIN1[10:8] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 764 2.13.175 Register 4C3h (offset = 4C3h) [reset = 0h] Figure 2-1587. Register 4C3h RX_AGC_BAND0_LNA_GAIN3[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 765 LNA Gain for Band0 for temp index 5 in case of External LNA RX_AGC_BAND0_ Control , Gain for DVGA Index 5 in case of External DVGA LNA_GAIN5[7:0] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 766 2.13.182 Register 4CAh (offset = 4CAh) [reset = 0h] Figure 2-1594. Register 4CAh RX_AGC_BAND0_LNA_GAIN7[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 767 LNA Gain for Band0 for temp index 8 in case of External LNA RX_AGC_BAND0_ Control , Gain for DVGA Index 8 in case of External DVGA LNA_GAIN8[10:8] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 768 2.13.189 Register 4D1h (offset = 4D1h) [reset = 0h] Figure 2-1601. Register 4D1h RX_AGC_BAND0_LNA_GAIN10[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 769 LNA Gain for Band0 for temp index 12 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 12 in case of External LNA_GAIN12[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 770 2.13.196 Register 4D8h (offset = 4D8h) [reset = 0h] Figure 2-1608. Register 4D8h RX_AGC_BAND0_LNA_GAIN14[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 771 LNA Gain for Band0 for temp index 15 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 15 in case of External LNA_GAIN15[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 772 2.13.203 Register 4DFh (offset = 4DFh) [reset = 0h] Figure 2-1615. Register 4DFh RX_AGC_BAND0_LNA_GAIN17[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 773 LNA Gain for Band0 for temp index 19 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 19 in case of External LNA_GAIN19[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 774 2.13.210 Register 4E6h (offset = 4E6h) [reset = 0h] Figure 2-1622. Register 4E6h RX_AGC_BAND0_LNA_GAIN21[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 775 LNA Gain for Band0 for temp index 22 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 22 in case of External LNA_GAIN22[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 776 2.13.217 Register 4EDh (offset = 4EDh) [reset = 0h] Figure 2-1629. Register 4EDh RX_AGC_BAND0_LNA_GAIN24[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 777 LNA Gain for Band0 for temp index 26 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 26 in case of External LNA_GAIN26[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 778 2.13.224 Register 4F4h (offset = 4F4h) [reset = 0h] Figure 2-1636. Register 4F4h RX_AGC_BAND0_LNA_GAIN28[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 779 LNA Gain for Band0 for temp index 29 in case of External RX_AGC_BAND0_ LNA Control , Gain for DVGA Index 29 in case of External LNA_GAIN29[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 780 2.13.231 Register 4FBh (offset = 4FBh) [reset = 0h] Figure 2-1643. Register 4FBh RX_AGC_BAND0_LNA_GAIN31[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 781 LNA Gain for Band1 for temp index 1 in case of External LNA RX_AGC_BAND1_ Control , Gain for DVGA Index 33 in case of External DVGA LNA_GAIN1[7:0] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 782 2.13.238 Register 502h (offset = 502h) [reset = 0h] Figure 2-1650. Register 502h RX_AGC_BAND1_LNA_GAIN3[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 783 LNA Gain for Band1 for temp index 4 in case of External LNA RX_AGC_BAND1_ Control , Gain for DVGA Index 36 in case of External DVGA LNA_GAIN4[10:8] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 784 2.13.245 Register 509h (offset = 509h) [reset = 0h] Figure 2-1657. Register 509h RX_AGC_BAND1_LNA_GAIN6[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 785 LNA Gain for Band1 for temp index 8 in case of External LNA RX_AGC_BAND1_ Control , Gain for DVGA Index 40 in case of External DVGA LNA_GAIN8[7:0] control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 786 2.13.252 Register 510h (offset = 510h) [reset = 0h] Figure 2-1664. Register 510h RX_AGC_BAND1_LNA_GAIN10[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 787 LNA Gain for Band1 for temp index 11 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 43 in case of External LNA_GAIN11[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 788 2.13.259 Register 517h (offset = 517h) [reset = 0h] Figure 2-1671. Register 517h RX_AGC_BAND1_LNA_GAIN13[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 789 LNA Gain for Band1 for temp index 15 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 47 in case of External LNA_GAIN15[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 790 2.13.266 Register 51Eh (offset = 51Eh) [reset = 0h] Figure 2-1678. Register 51Eh RX_AGC_BAND1_LNA_GAIN17[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 791 LNA Gain for Band1 for temp index 18 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 50 in case of External LNA_GAIN18[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 792 2.13.273 Register 525h (offset = 525h) [reset = 0h] Figure 2-1685. Register 525h RX_AGC_BAND1_LNA_GAIN20[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 793 LNA Gain for Band1 for temp index 22 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 54 in case of External LNA_GAIN22[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 794 2.13.280 Register 52Ch (offset = 52Ch) [reset = 0h] Figure 2-1692. Register 52Ch RX_AGC_BAND1_LNA_GAIN24[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 795 LNA Gain for Band1 for temp index 25 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 57 in case of External LNA_GAIN25[10:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 796 2.13.287 Register 533h (offset = 533h) [reset = 0h] Figure 2-1699. Register 533h RX_AGC_BAND1_LNA_GAIN27[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 797 LNA Gain for Band1 for temp index 29 in case of External RX_AGC_BAND1_ LNA Control , Gain for DVGA Index 61 in case of External LNA_GAIN29[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 798 2.13.294 Register 53Ah (offset = 53Ah) [reset = 0h] Figure 2-1706. Register 53Ah RX_AGC_BAND1_LNA_GAIN31[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 799 LNA Control , Phase for DVGA Index 0 in case of External LNA_PHASE0[9:8] DVGA control. A value of 1024 corresponds to 360 degrees. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 800 2.13.301 Register 541h (offset = 541h) [reset = 0h] Figure 2-1713. Register 541h RX_AGC_BAND0_LNA_PHASE 2[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 801 LNA Phase for Band0 for temp index 4 in case of External RX_AGC_BAND0_ LNA Control , Phase for DVGA Index 4 in case of External LNA_PHASE4[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 802 2.13.308 Register 548h (offset = 548h) [reset = 0h] Figure 2-1720. Register 548h RX_AGC_BAND0_LNA_PHASE6[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 803 LNA Phase for Band0 for temp index 7 in case of External RX_AGC_BAND0_ LNA Control , Phase for DVGA Index 7 in case of External LNA_PHASE7[9:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 804 2.13.315 Register 54Fh (offset = 54Fh) [reset = 0h] Figure 2-1727. Register 54Fh RX_AGC_BAND0_LNA_PHASE 9[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 805 LNA Phase for Band0 for temp index 11 in case of External LNA_PHASE11[7:0 LNA Control , Phase for DVGA Index 11 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 806 2.13.322 Register 556h (offset = 556h) [reset = 0h] Figure 2-1734. Register 556h RX_AGC_BAND0_LNA_PHASE13[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 807 LNA Phase for Band0 for temp index 14 in case of External LNA_PHASE14[9:8 LNA Control , Phase for DVGA Index 14 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 808 2.13.329 Register 55Dh (offset = 55Dh) [reset = 0h] Figure 2-1741. Register 55Dh RX_AGC_BAND0_LNA_PHASE 16[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 809 LNA Phase for Band0 for temp index 18 in case of External LNA_PHASE18[7:0 LNA Control , Phase for DVGA Index 18 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 810 2.13.336 Register 564h (offset = 564h) [reset = 0h] Figure 2-1748. Register 564h RX_AGC_BAND0_LNA_PHASE20[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 811 LNA Phase for Band0 for temp index 21 in case of External LNA_PHASE21[9:8 LNA Control , Phase for DVGA Index 21 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 812 2.13.343 Register 56Bh (offset = 56Bh) [reset = 0h] Figure 2-1755. Register 56Bh RX_AGC_BAND0_LNA_PHASE 23[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 813 LNA Phase for Band0 for temp index 25 in case of External LNA_PHASE25[7:0 LNA Control , Phase for DVGA Index 25 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 814 2.13.350 Register 572h (offset = 572h) [reset = 0h] Figure 2-1762. Register 572h RX_AGC_BAND0_LNA_PHASE27[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 815 LNA Phase for Band0 for temp index 28 in case of External LNA_PHASE28[9:8 LNA Control , Phase for DVGA Index 28 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 816 2.13.357 Register 579h (offset = 579h) [reset = 0h] Figure 2-1769. Register 579h RX_AGC_BAND0_LNA_PHASE 30[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 817 LNA Phase for Band1 for temp index 0 in case of External RX_AGC_BAND1_ LNA Control , Phase for DVGA Index 32 in case of External LNA_PHASE0[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 818 2.13.364 Register 580h (offset = 580h) [reset = 0h] Figure 2-1776. Register 580h RX_AGC_BAND1_LNA_PHASE2[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 819 LNA Phase for Band1 for temp index 3 in case of External RX_AGC_BAND1_ LNA Control , Phase for DVGA Index 35 in case of External LNA_PHASE3[9:8] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 820 2.13.371 Register 587h (offset = 587h) [reset = 0h] Figure 2-1783. Register 587h RX_AGC_BAND1_LNA_PHASE 5[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 821 LNA Phase for Band1 for temp index 7 in case of External RX_AGC_BAND1_ LNA Control , Phase for DVGA Index 39 in case of External LNA_PHASE7[7:0] DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 822 2.13.378 Register 58Eh (offset = 58Eh) [reset = 0h] Figure 2-1790. Register 58Eh RX_AGC_BAND1_LNA_PHASE9[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 823 LNA Phase for Band1 for temp index 10 in case of External LNA_PHASE10[9:8 LNA Control , Phase for DVGA Index 42 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 824 2.13.385 Register 595h (offset = 595h) [reset = 0h] Figure 2-1797. Register 595h RX_AGC_BAND1_LNA_PHASE 12[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 825 LNA Phase for Band1 for temp index 14 in case of External LNA_PHASE14[7:0 LNA Control , Phase for DVGA Index 46 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 826 2.13.392 Register 59Ch (offset = 59Ch) [reset = 0h] Figure 2-1804. Register 59Ch RX_AGC_BAND1_LNA_PHASE16[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 827 LNA Phase for Band1 for temp index 17 in case of External LNA_PHASE17[9:8 LNA Control , Phase for DVGA Index 49 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 828 2.13.399 Register 5A3h (offset = 5A3h) [reset = 0h] Figure 2-1811. Register 5A3h RX_AGC_BAND1_LNA_PHASE 19[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 829 LNA Phase for Band1 for temp index 21 in case of External LNA_PHASE21[7:0 LNA Control , Phase for DVGA Index 53 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 830 2.13.406 Register 5AAh (offset = 5AAh) [reset = 0h] Figure 2-1818. Register 5AAh RX_AGC_BAND1_LNA_PHASE23[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 831 LNA Phase for Band1 for temp index 24 in case of External LNA_PHASE24[9:8 LNA Control , Phase for DVGA Index 56 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 832 2.13.413 Register 5B1h (offset = 5B1h) [reset = 0h] Figure 2-1825. Register 5B1h RX_AGC_BAND1_LNA_PHASE 26[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 833 LNA Phase for Band1 for temp index 28 in case of External LNA_PHASE28[7:0 LNA Control , Phase for DVGA Index 60 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 834 2.13.420 Register 5B8h (offset = 5B8h) [reset = 0h] Figure 2-1832. Register 5B8h RX_AGC_BAND1_LNA_PHASE30[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 835 LNA Phase for Band1 for temp index 31 in case of External LNA_PHASE31[9:8 LNA Control , Phase for DVGA Index 63 in case of External DVGA control SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 836 Should be _CTRL[10:8] programmed such that the output clock is <25 MHz. dvga_spi_clock = Fs/8/(clk_div_factor_dvga_ctrl+1) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 837 WR_DET_SEEN[7: selected. Update pulse needs to be provided for reading this. Power read will be equal to 10 * log (value read/65535) SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 838 This will get updated only when update pulse is EN[15:8] given.. Running accum mode should not be used when interpreting this. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 839 When high it continous updates the statistics status based on loop operation. For statistics to be working clk_en_agc_stat to be made high SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 840 2.13.439 Register 5E7h (offset = 5E7h) [reset = 0h] Figure 2-1851. Register 5E7h RX_AGC_MIN_DVGA_ATTN_USED R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 841 RX_AGC_BAN N_CHANGED D1_LNA_BYPA D0_LNA_BYPA SS_CHANGED SS_CHANGED R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 842 1 : Enable Digital Gain Compensation enabled. Can be enabled irrespective of whether Internal AGC is enabled/disabled RX_ALC_ENABLE 0 : disable 1 : enable Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 843 LSB of I contains detector selected by B_BIT_FOR_CON rx_agc_pin_1_select_bits. LSB of Q contains detector TROL selected by rx_agc_pin_2_select_bits 0 : Disable 1 : Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 844 Used in coarse/fine mode (both pin and LSB) only RX_ALC_SIG_BAC when coarse/fine range is lower than required total gain range. KOFF_DB This should be in sync with FineExpOffset. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 845 2.13.452 Register 63Eh (offset = 63Eh) [reset = 3h] Figure 2-1864. Register 63Eh RX_ALC_FINE_EXP_OFFSET RX_ALC_FINE_OFFSET R/W-0h R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 846 2.13.455 Register 648h (offset = 648h) [reset = 0h] Figure 2-1867. Register 648h RX_ALC_MIN_ATTN_DSA R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 847 2.13.458 Register 650h (offset = 650h) [reset = 0h] Figure 2-1870. Register 650h RX_ALC_BAND0_EXT_COMP_MIN_ATTN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 848 2.13.461 Register 6A5h (offset = 6A5h) [reset = 0h] Figure 2-1873. Register 6A5h RX_ALC_DUAL BAND_AGC_E R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 849 2.13.464 Register 6D6h (offset = 6D6h) [reset = 0h] Figure 2-1876. Register 6D6h RX_ALC_DEC_SHIFT_FORCE_VAL RX_ALC_DEC_ SHIFT_FORCE R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 850 2.13.467 Register 740h (offset = 740h) [reset = 1h] Figure 2-1879. Register 740h RX_DDC_ROO T_CLOCK_GA R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 851 Power down the DDC section of RX channel RX_DDC_DECIM_ 1 : Power down the Dec Chain blocks of the RX channel 0 : Normal mode of operation SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 852 Reset Description Power down the AGC RX_AGC_PDN 1 : Power down the AGC of the RX channel 0 : Normal mode of operation Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 853 FB_DDC_NCO2_FMULT[15:8] 10Ah FB_DDC_NCO2_FMULT[21:16] 10Ch FB_DDC_NCO3_FMULT[7:0] 10Dh FB_DDC_NCO3_FMULT[15:8] 10Eh FB_DDC_NCO3_FMULT[21:16] 140h FB_DDC_NCO0_FRAC_FCW_NUM[7:0] 141h FB_DDC_NCO0_FRAC_FCW_NUM[15:8] 142h FB_DDC_NCO0_FRAC_FCW_DEN[7:0] 143h FB_DDC_NCO0_FRAC_FCW_DEN[15:8] 144h FB_DDC_NCO1_FRAC_FCW_NUM[7:0] 145h FB_DDC_NCO1_FRAC_FCW_NUM[15:8] 146h FB_DDC_NCO1_FRAC_FCW_DEN[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 854 FB_AGC_LNA_RF_DET_ATTACK_WIN_LEN[23:16] 42Ch FB_AGC_BIG_STEP_ATTACK_SIG_TH[7:0] 42Dh FB_AGC_BIG_STEP_ATTACK_SIG_TH[11:8] 430h FB_AGC_SMALL_STEP_ATTACK_SIG_TH[7:0] 431h FB_AGC_SMALL_STEP_ATTACK_SIG_TH[11:8] 434h FB_AGC_BIG_STEP_DECAY_SIG_TH[7:0] 435h FB_AGC_BIG_STEP_DECAY_SIG_TH[11:8] 438h FB_AGC_SMALL_STEP_DECAY_SIG_TH[7:0] 439h FB_AGC_SMALL_STEP_DECAY_SIG_TH[11:8] 43Ch FB_AGC_PWR_DET_ATTACK_TH[7:0] 43Dh FB_AGC_PWR_DET_ATTACK_TH[15:8] 43Eh FB_AGC_PWR_DET_DECAY_TH[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 855 FB_AGC_PIN_3_SELECT_BITS[7:0] 4B1h FB_AGC_PIN_3_SELECT_BITS[15:8] 4B2h FB_AGC_PIN_4_SELECT_BITS[7:0] 4B3h FB_AGC_PIN_4_SELECT_BITS[15:8] 4B4h FB_AGC_GAIN_CHG_PULSE_EXPN_COUNT[7:0] 4B5h FB_AGC_GAIN_CHG_PULSE_EXPN_COUNT[11:8] 4B6h FB_AGC_PULSE_EXPANSION_COUNT[7:0] 4B7h FB_AGC_PULSE_EXPANSION_COUNT[11:8] 4B8h FB_AGC_BAND0_TEMP_IDX 4BCh FB_AGC_BAND0_LNA_GAIN0[7:0] 4BDh FB_AGC_BAND0_LNA_GAIN0[10:8] 4BEh FB_AGC_BAND0_LNA_GAIN1[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 856 FB_AGC_BAND0_LNA_GAIN23[10:8] 4ECh FB_AGC_BAND0_LNA_GAIN24[7:0] 4EDh FB_AGC_BAND0_LNA_GAIN24[10:8] 4EEh FB_AGC_BAND0_LNA_GAIN25[7:0] 4EFh FB_AGC_BAND0_LNA_GAIN25[10:8] 4F0h FB_AGC_BAND0_LNA_GAIN26[7:0] 4F1h FB_AGC_BAND0_LNA_GAIN26[10:8] 4F2h FB_AGC_BAND0_LNA_GAIN27[7:0] 4F3h FB_AGC_BAND0_LNA_GAIN27[10:8] 4F4h FB_AGC_BAND0_LNA_GAIN28[7:0] 4F5h FB_AGC_BAND0_LNA_GAIN28[10:8] 4F6h FB_AGC_BAND0_LNA_GAIN29[7:0] Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 857 557h 558h FB_AGC_BAND0_LNA_PHASE14[7:0] FB_AGC_BAND0_LNA_PHASE14[9 559h 55Ah FB_AGC_BAND0_LNA_PHASE15[7:0] FB_AGC_BAND0_LNA_PHASE15[9 55Bh 55Ch FB_AGC_BAND0_LNA_PHASE16[7:0] FB_AGC_BAND0_LNA_PHASE16[9 55Dh 55Eh FB_AGC_BAND0_LNA_PHASE17[7:0] FB_AGC_BAND0_LNA_PHASE17[9 55Fh 560h FB_AGC_BAND0_LNA_PHASE18[7:0] FB_AGC_BAND0_LNA_PHASE18[9 561h 562h FB_AGC_BAND0_LNA_PHASE19[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 858 5D1h FB_AGC_AVG_PWR_DET_SEEN[15:8] 5D4h FB_AGC_DIG_DET_NUM_HITS_SEEN[7:0] 5D5h FB_AGC_DIG_DET_NUM_HITS_SEEN[15:8] 5D6h FB_AGC_DIG_DET_NUM_HITS_SEEN[23:16] FB_AGC_USE_ ALL_DETECTO RS_AS_ATTAC 5DCh FB_AGC_REST 5E0h ART_MAX_MIN 5E4h FB_AGC_MAX_ATTN_USED 5E5h FB_AGC_MIN_ATTN_USED 5E6h FB_AGC_MAX_DVGA_ATTN_USED 5E7h FB_AGC_MIN_DVGA_ATTN_USED Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 859 650h FB_ALC_BAND0_EXT_COMP_MIN_ATTN 712h FB_DDC_PROG_DELAY FB_DDC_PROG _DELAY_BYPAS 713h FB_DDC_ROOT 740h _CLOCK_GATE FB_DDC_USE_ RX_ROOT_CLO 741h 770h FB_DDC_PDN FB_DDC_PRE_ 771h DECIM_PDN FB_DDC_DECI 772h M_PDN 773h FB_AGC_PDN SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 860 2.14.3 Register 44h (offset = 44h) [reset = 0h] Figure 2-1886. Register 44h FB_DDC_REA L_MODE_CON R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 861 Type Reset Description Latency-matching delay controls in different FB DDC sections. FB_DDC_MISC_D Optimal value automatically determined if System LY_CONFIG Configuration Macros are used. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 862 2.14.10 Register A0h (offset = A0h) [reset = 0h] Figure 2-1893. Register A0h FB_DDC_NCO0_FCW[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 863 Table 2-1910. Register A3 Field Descriptions Field Type Reset Description FB_DDC_NCO0_F Frequency control word (FCW) for nco0. CW[31:24] The System Configuration Macros automatically configure this. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 864 2.14.17 Register A7h (offset = A7h) [reset = 0h] Figure 2-1900. Register A7h FB_DDC_NCO1_FCW[31:24] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 865 Table 2-1917. Register AA Field Descriptions Field Type Reset Description FB_DDC_NCO2_F Frequency control word (FCW) for nco2. CW[23:16] The System Configuration Macros automatically configure this. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 866 2.14.24 Register AEh (offset = AEh) [reset = 0h] Figure 2-1907. Register AEh FB_DDC_NCO3_FCW[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 867 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-1924. Register E1 Field Descriptions Field Type Reset Description FB_DDC_NCO0_P HASE_OFFSET[15 Offset phase for nco0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 868 2.14.31 Register E5h (offset = E5h) [reset = 0h] Figure 2-1914. Register E5h FB_DDC_NCO2_PHASE_OFFSET[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 869 [0 MULT[7:0] and Fadc/16]. The System Configuration Macros automatically compute and configure this, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 870 [0 MULT[7:0] and Fadc/16]. The System Configuration Macros automatically compute and configure this, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 871 [0 MULT[7:0] and Fadc/16]. The System Configuration Macros automatically compute and configure this, and are hence strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 872 [0 MULT[7:0] and Fadc/16]. The System Configuration Macros automatically compute and configure this, and are hence strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 873 Numerator of the fractional fequency control word for nco0. FB_DDC_NCO0_F Signed number. RAC_FCW_NUM[7 System Configuration macros compute and configure this automatically and hence are strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 874 Denominator of the fractional fequency control word for nco0. FB_DDC_NCO0_F Unsigned number. RAC_FCW_DEN[1 System Configuration macros compute and configure this 5:8] automatically and hence are strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 875 Denominator of the fractional fequency control word for nco1. FB_DDC_NCO1_F Unsigned number. RAC_FCW_DEN[7: System Configuration macros compute and configure this automatically and hence are strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 876 Numerator of the fractional fequency control word for nco2. FB_DDC_NCO2_F Signed number. RAC_FCW_NUM[1 System Configuration macros compute and configure this 5:8] automatically and hence are strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 877 Numerator of the fractional fequency control word for nco3. FB_DDC_NCO3_F Signed number. RAC_FCW_NUM[7 System Configuration macros compute and configure this automatically and hence are strongly recommended. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 878 Denominator of the fractional fequency control word for nco3. FB_DDC_NCO3_F Unsigned number. RAC_FCW_DEN[1 System Configuration macros compute and configure this 5:8] automatically and hence are strongly recommended. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 879 0 : Disable 1 : Enable Use digital bigstep attack detector for AGC control loop FB_AGC_BIG_STE 0 : Disable P_ATTACK_EN 1 : Enable SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 880 _DET_EN ACK_DET_EN _DET_EN R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 881 Table 2-1965. Register 408 Field Descriptions Field Type Reset Description FB_AGC_BIG_STE Gain step when Digital big step attack is triggered. 0.5 dB step P_ATTACK_STEP size. _SIZE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 882 2.14.72 Register 40Ch (offset = 40Ch) [reset = 2h] Figure 2-1955. Register 40Ch FB_AGC_PWR_ATTACK_STEP_SIZE R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 883 Table 2-1972. Register 414 Field Descriptions Field Type Reset Description FB_AGC_BIG_STE Digital big step attack det window length. Max supported P_ATTACK_WIN_L length is 2^24 - 2. EN[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 884 2.14.79 Register 419h (offset = 419h) [reset = 0h] Figure 2-1962. Register 419h FB_AGC_SMALL_STEP_ATTACK_WIN_LEN[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 885 Table 2-1979. Register 41D Field Descriptions Field Type Reset Description FB_AGC_BIG_STE Digital big step decay det window length. Max supported P_DECAY_WIN_L length is 2^24 - 2. EN[15:8] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 886 2.14.86 Register 422h (offset = 422h) [reset = 0h] Figure 2-1969. Register 422h FB_AGC_SMALL_STEP_DECAY_WIN_LEN[23:16] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 887 Table 2-1986. Register 428 Field Descriptions Field Type Reset Description FB_AGC_LNA_RF LNA RF attack det window length. Max supported length is _DET_ATTACK_W 2^24 - 2. IN_LEN[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 888 2.14.93 Register 42Dh (offset = 42Dh) [reset = 3h] Figure 2-1976. Register 42Dh FB_AGC_BIG_STEP_ATTACK_SIG_TH[11:8] R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 889 Table 2-1993. Register 434 Field Descriptions Field Type Reset Description FB_AGC_BIG_STE Signal threshold for digital big step decay detector, in 0.12 P_DECAY_SIG_T unsigned format H[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 890 2.14.100 Register 43Ch (offset = 43Ch) [reset = 10h] Figure 2-1983. Register 43Ch FB_AGC_PWR_DET_ATTACK_TH[7:0] R/W-10h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 891 Threshold for power decay detector, in 0.16 unsigned format. ET_DECAY_TH[15 Power threshold in dB will be 10*log (Th/2^16). A full scale sine-wave corresponds to -3 dB power. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 892 2.14.107 Register 454h (offset = 454h) [reset = 0h] Figure 2-1990. Register 454h FB_AGC_SMALL_STEP_ATTACK_NUM_HITS[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 893 Table 2-2007. Register 458 Field Descriptions Field Type Reset Description FB_AGC_BIG_STE P_DECAY_NUM_H Number of Hits threshold for digital big step decay detector. ITS[7:0] SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 894 2.14.114 Register 45Dh (offset = 45Dh) [reset = 0h] Figure 2-1997. Register 45Dh FB_AGC_SMALL_STEP_DECAY_NUM_HITS[15:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 895 LNA RF attack det threshold. If Number of hits is greater than _DET_ATTACK_N this, detector is triggered. Note that per clock we may get up UM_HITS[15:8] to 8 hits. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 896 0 : Internal AGC Mode 1 : External AGC Mode Internal AGC control loop enable FB_AGC_INTERN 0 : Use Default attn AL_EN 1 : Internal AGC enabled Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 897 Reset Description FB_AGC_DEF_AT Default DSA attn. value when "rx_agc_internal_en" is 0 and hence it will be starting value when the AGC is enabled SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 898 2.14.127 Register 4A0h (offset = 4A0h) [reset = 32h] Figure 2-2010. Register 4A0h FB_AGC_MAX_ATTN R/W-32h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 899 Table 2-2027. Register 4A3 Field Descriptions Field Type Reset Description FB_AGC_MIN_DV Max attn Ext DVGA can go to. Resolution is 0.5 dB. GA_ATTN SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 900 Table 2-2030. Register 4A8 Field Descriptions Field Type Reset Description FB_AGC_BLANK_ TIME_FOR_EXT_ When Ext Component Gain Changes, this blanking time is COMP_CHANGE[7 used for all the detectors Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 901 Bit 5 --> Bigstep decay Bit 4 --> Small step decay Bit 3 --> Dig pwr attack Bit 2 --> Dig pwr decay Bit 1 --> Absolute reliability Bit 0 --> Relative reliability SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 902 2.14.139 Register 4AFh (offset = 4AFh) [reset = 30h] Figure 2-2022. Register 4AFh FB_AGC_PIN_2_SELECT_BITS[15:8] R/W-30h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 903 Bit 5 --> Bigstep decay Bit 4 --> Small step decay Bit 3 --> Dig pwr attack Bit 2 --> Dig pwr decay Bit 1 --> Absolute reliability Bit 0 --> Relative reliability SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 904 Number of clock cycles (in terms of Fs/8) by which a high(one) HG_PULSE_EXPN should be extended before being sent on the pins for gain _COUNT[7:0] change indication pin. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 905 2.14.148 Register 4B8h (offset = 4B8h) [reset = 0h] Figure 2-2031. Register 4B8h FB_AGC_BAND0_TEMP_IDX R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 906 LNA Gain for Band0 for temp index 1 in case of External LNA FB_AGC_BAND0_ Control , Gain for DVGA Index 1 in case of External DVGA LNA_GAIN1[7:0] control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 907 2.14.155 Register 4C2h (offset = 4C2h) [reset = 0h] Figure 2-2038. Register 4C2h FB_AGC_BAND0_LNA_GAIN3[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 908 LNA Gain for Band0 for temp index 4 in case of External LNA FB_AGC_BAND0_ Control , Gain for DVGA Index 4 in case of External DVGA LNA_GAIN4[10:8] control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 909 2.14.162 Register 4C9h (offset = 4C9h) [reset = 0h] Figure 2-2045. Register 4C9h FB_AGC_BAND0_LNA_GAIN6[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 910 LNA Gain for Band0 for temp index 8 in case of External LNA FB_AGC_BAND0_ Control , Gain for DVGA Index 8 in case of External DVGA LNA_GAIN8[7:0] control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 911 2.14.169 Register 4D0h (offset = 4D0h) [reset = 0h] Figure 2-2052. Register 4D0h FB_AGC_BAND0_LNA_GAIN10[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 912 LNA Gain for Band0 for temp index 11 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 11 in case of External LNA_GAIN11[10:8] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 913 2.14.176 Register 4D7h (offset = 4D7h) [reset = 0h] Figure 2-2059. Register 4D7h FB_AGC_BAND0_LNA_GAIN13[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 914 LNA Gain for Band0 for temp index 15 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 15 in case of External LNA_GAIN15[7:0] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 915 2.14.183 Register 4DEh (offset = 4DEh) [reset = 0h] Figure 2-2066. Register 4DEh FB_AGC_BAND0_LNA_GAIN17[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 916 LNA Gain for Band0 for temp index 18 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 18 in case of External LNA_GAIN18[10:8] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 917 2.14.190 Register 4E5h (offset = 4E5h) [reset = 0h] Figure 2-2073. Register 4E5h FB_AGC_BAND0_LNA_GAIN20[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 918 LNA Gain for Band0 for temp index 22 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 22 in case of External LNA_GAIN22[7:0] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 919 2.14.197 Register 4ECh (offset = 4ECh) [reset = 0h] Figure 2-2080. Register 4ECh FB_AGC_BAND0_LNA_GAIN24[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 920 LNA Gain for Band0 for temp index 25 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 25 in case of External LNA_GAIN25[10:8] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 921 2.14.204 Register 4F3h (offset = 4F3h) [reset = 0h] Figure 2-2087. Register 4F3h FB_AGC_BAND0_LNA_GAIN27[10:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 922 LNA Gain for Band0 for temp index 29 in case of External FB_AGC_BAND0_ LNA Control , Gain for DVGA Index 29 in case of External LNA_GAIN29[7:0] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 923 2.14.211 Register 4FAh (offset = 4FAh) [reset = 0h] Figure 2-2094. Register 4FAh FB_AGC_BAND0_LNA_GAIN31[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 924 LNA Control , Phase for DVGA Index 0 in case of External LNA_PHASE0[9:8] DVGA control. A value of 1024 corresponds to 360 degrees. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 925 2.14.218 Register 541h (offset = 541h) [reset = 0h] Figure 2-2101. Register 541h FB_AGC_BAND0_LNA_PHASE2 [9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 926 LNA Phase for Band0 for temp index 4 in case of External FB_AGC_BAND0_ LNA Control , Phase for DVGA Index 4 in case of External LNA_PHASE4[7:0] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 927 2.14.225 Register 548h (offset = 548h) [reset = 0h] Figure 2-2108. Register 548h FB_AGC_BAND0_LNA_PHASE6[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 928 LNA Phase for Band0 for temp index 7 in case of External FB_AGC_BAND0_ LNA Control , Phase for DVGA Index 7 in case of External LNA_PHASE7[9:8] DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 929 2.14.232 Register 54Fh (offset = 54Fh) [reset = 0h] Figure 2-2115. Register 54Fh FB_AGC_BAND0_LNA_PHASE9 [9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 930 LNA Phase for Band0 for temp index 11 in case of External LNA_PHASE11[7:0 LNA Control , Phase for DVGA Index 11 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 931 2.14.239 Register 556h (offset = 556h) [reset = 0h] Figure 2-2122. Register 556h FB_AGC_BAND0_LNA_PHASE13[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 932 LNA Phase for Band0 for temp index 14 in case of External LNA_PHASE14[9:8 LNA Control , Phase for DVGA Index 14 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 933 2.14.246 Register 55Dh (offset = 55Dh) [reset = 0h] Figure 2-2129. Register 55Dh FB_AGC_BAND0_LNA_PHASE1 6[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 934 LNA Phase for Band0 for temp index 18 in case of External LNA_PHASE18[7:0 LNA Control , Phase for DVGA Index 18 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 935 2.14.253 Register 564h (offset = 564h) [reset = 0h] Figure 2-2136. Register 564h FB_AGC_BAND0_LNA_PHASE20[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 936 LNA Phase for Band0 for temp index 21 in case of External LNA_PHASE21[9:8 LNA Control , Phase for DVGA Index 21 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 937 2.14.260 Register 56Bh (offset = 56Bh) [reset = 0h] Figure 2-2143. Register 56Bh FB_AGC_BAND0_LNA_PHASE2 3[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 938 LNA Phase for Band0 for temp index 25 in case of External LNA_PHASE25[7:0 LNA Control , Phase for DVGA Index 25 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 939 2.14.267 Register 572h (offset = 572h) [reset = 0h] Figure 2-2150. Register 572h FB_AGC_BAND0_LNA_PHASE27[7:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 940 LNA Phase for Band0 for temp index 28 in case of External LNA_PHASE28[9:8 LNA Control , Phase for DVGA Index 28 in case of External DVGA control Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 941 2.14.274 Register 579h (offset = 579h) [reset = 0h] Figure 2-2157. Register 579h FB_AGC_BAND0_LNA_PHASE3 0[9:8] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 942 Enables Control of peak detector reset using GPIO. Used in FB_AGC_ENABLE only External AGC Mode. _GPIO_RESET_FE 0 : Disable ATURE 1 : Enable Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 943 DVGA transaction. If low information is DVGA gain of RXCHA VGA_SPI_ORDER followed by RXCHB. If made high DVGA gain of RXCHB followed by RXCHA SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 944 WR_DET_SEEN[1 selected. Update pulse needs to be provided for reading this. 5:8] Power read will be equal to 10 * log (value read/65535) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 945 This will get updated only when update pulse is EN[23:16] given.. Running accum mode should not be used when interpreting this. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 946 Table 2-2186. Register 5E4 Field Descriptions Field Type Reset Description FB_AGC_MAX_AT Max attenuation seen by stat module. This is in 0.5 dB TN_USED resolution. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 947 Figure 2-2176. Register 5E8h reserved FB_AGC_BAN FB_AGC_CURR_DVGA_ATTN D0_CURR_EX T_LNA_BYPAS R-0h R-0h R-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 948 1 : Overall attn setting changed, includes DSA as well as ext reserved FB_AGC_BAND0_ Whether LNA gain was changed for Band 0 as seen by LNA_BYPASS_CH statistics module ANGED Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 949 2.14.298 Register 635h (offset = 635h) [reset = 3h] Figure 2-2181. Register 635h FB_ALC_MODE R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 950 2.14.300 Register 637h (offset = 637h) [reset = 0h] Figure 2-2183. Register 637h FB_ALC_USE_ 12BIT_SEL R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 951 Field Type Reset Description FB_ALC_GAIN_OF Offset to be added to gain compensation if required. Can be FSET_INPUT_ALC used for optimization. Units is dB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 952 2.14.306 Register 63Eh (offset = 63Eh) [reset = 3h] Figure 2-2189. Register 63Eh FB_ALC_FINE_EXP_OFFSET FB_ALC_FINE_OFFSET R/W-0h R/W-3h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 953 2.14.309 Register 642h (offset = 642h) [reset = 8h] Figure 2-2192. Register 642h FB_ALC_INPUT_DELAY_CODE R/W-8h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 954 Reset Description FB_ALC_MIN_ATT DSA min attenuation. DGC will compensate for gain changes N_DSA over and above this value only. 0.5 dB step size Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 955 1 : Enable Use 12bit mode of operation when the channel is in FB mode. FB_ALC_USE_12B 0 : 16bit IT_SEL_FB 1 : 12bit SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 956 Reset Description Bypass the programmable delay block. FB_DDC_PROG_D 1 : Bypass Enable in FB Mode ELAY_BYPASS 0 : Bypass Disable in FB Mode Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 957 Table 2-2218. Register 770 Field Descriptions Field Type Reset Description Power down the complete FB channel FB_DDC_PDN 1 : Power Down FB 0 : Enable FB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 958 Table 2-2221. Register 773 Field Descriptions Field Type Reset Description Power down the AGC FB_AGC_PDN 1 : Turn off FB AGC clock 0 : Enable FB AGC clock Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 959 RXGSWAP_MO DE_AB RXGSWAP_MO DE_CD ENABLE_RX_GAIN_SWAP_A ENABLE_RX_GAIN_SWAP_B ENABLE_RX_GAIN_SWAP_C ENABLE_RX_GAIN_SWAP_D BROADCAST_S WAP_RX BROADCAST_R XNCOSEL RXNCOSEL_MODE_AB RXNCOSEL_MODE_CD ENABLE_RXNCOSEL_A ENABLE_RXNCOSEL_B ENABLE_RXNCOSEL_C ENABLE_RXNCOSEL_D ENABLE_FB_GAIN_SWAP_AB ENABLE_FB_GAIN_SWAP_CD BROADCAST_F BNCOSEL FORCE_FBNCOSEL_AB SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 960 Allows Rx and Fb chains to be shared and in that case rxa/b/c/d_fb_shr should be programmed appropriately System normally comes up with fdd_mode=0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 961 2.15.5 Register 88h (offset = 88h) [reset = 1h] Figure 2-2212. Register 88h RXA_FB_SHR R/W-1h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 962 2.15.9 Register 8Ch (offset = 8Ch) [reset = 0h] Figure 2-2216. Register 8Ch USE_PER_CH _TXAB_TDD R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 963 0 of the input and chD gets bit1of the input, in the LSB to each of the channels. MSB will be zero. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 964 2.15.16 Register 93h (offset = 93h) [reset = 0h] Figure 2-2223. Register 93h ENABLE_TX_GAIN_SWAP_D R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 965 Table 2-2241. Register 98 Field Descriptions Field Type Reset Description BROADCAST_TXN Setting this to '1' broadcasts to both TxAB and TxCD the COSEL same ncosel. SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 966 If enable == 0 then the corresponding bit in txncosel for that EL_A channel is made 0, else ncosel is sent as it is Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 967 2.15.26 Register A0h (offset = A0h) [reset = 0h] Figure 2-2233. Register A0h USE_PER_CH _RXAB_TDD R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 968 0 of the input and chD gets bit1of the input, in the LSB to each of the channels. MSB will be zero. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 969 2.15.33 Register A7h (offset = A7h) [reset = 0h] Figure 2-2240. Register A7h ENABLE_RX_GAIN_SWAP_D R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 970 (NCOsel for (band1), (band0)) RXNCOSEL_MOD 00 -> (b0),(b0,b0.b0,b0) E_AB 01 -> (b1),(b1,b0,b1,b0) 02 -> (0),(b3,b2,b1,b0) 03 -> (0),(0,0,0,0) Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 971 If enable == 0 then the corresponding bit in rxncosel for that EL_B channel is made 0, else ncosel is sent as it is SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 972 2.15.43 Register B6h (offset = B6h) [reset = 0h] Figure 2-2250. Register B6h ENABLE_FB_GAIN_SWAP_CD R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 973 2.15.46 Register BAh (offset = BAh) [reset = 0h] Figure 2-2253. Register BAh FORCE_FBNCOSEL_CD R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 974 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-2271. Register C0 Field Descriptions Field Type Reset Description DUAL_FBMODE Choses whether single fb or dual fb Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 975 2.15.53 Register C4h (offset = C4h) [reset = 2h] Figure 2-2260. Register C4h CH0_MSB_FBMUXSEL R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 976 Reset Description First 3-lsb bits for fbab next three for fbcd. OVERRIDE_VAL_ This is directly overriding the fbmuxsel going to each FBMUXSEL channels. Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 977 ODRIV_DS_GPIO_13 238h PULL_CTRL_GPIO_14 239h IBUF_ST_GPIO_14 23Ah ODRIV_DS_GPIO_14 23Ch PULL_CTRL_GPIO_15 23Dh IBUF_ST_GPIO_15 23Eh ODRIV_DS_GPIO_15 240h PULL_CTRL_GPIO_16 241h IBUF_ST_GPIO_16 242h ODRIV_DS_GPIO_16 244h PULL_CTRL_GPIO_17 245h IBUF_ST_GPIO_17 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 978 IBUF_ST_GPIO_32 282h ODRIV_DS_GPIO_32 284h PULL_CTRL_GPIO_33 285h IBUF_ST_GPIO_33 286h ODRIV_DS_GPIO_33 288h PULL_CTRL_GPIO_34 289h IBUF_ST_GPIO_34 28Ah ODRIV_DS_GPIO_34 28Ch PULL_CTRL_GPIO_35 28Dh IBUF_ST_GPIO_35 28Eh ODRIV_DS_GPIO_35 290h PULL_CTRL_GPIO_36 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 979 PULL_CTRL_GPIO_51 2CDh IBUF_ST_GPIO_51 2CEh ODRIV_DS_GPIO_51 2D0h PULL_CTRL_GPIO_52 2D1h IBUF_ST_GPIO_52 2D2h ODRIV_DS_GPIO_52 2D4h PULL_CTRL_GPIO_53 2D5h IBUF_ST_GPIO_53 2D6h ODRIV_DS_GPIO_53 2D8h PULL_CTRL_GPIO_54 2D9h IBUF_ST_GPIO_54 2DAh ODRIV_DS_GPIO_54 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 980 ODRIV_DS_GPIO_69 318h PULL_CTRL_GPIO_70 319h IBUF_ST_GPIO_70 31Ah ODRIV_DS_GPIO_70 31Ch PULL_CTRL_GPIO_71 31Dh IBUF_ST_GPIO_71 31Eh ODRIV_DS_GPIO_71 320h PULL_CTRL_GPIO_72 321h IBUF_ST_GPIO_72 322h ODRIV_DS_GPIO_72 324h PULL_CTRL_GPIO_73 325h IBUF_ST_GPIO_73 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 981 BUF_DIR_CTRL_GPIO_15 43Fh ACTIV_BIR_DIR_CTRL_GPIO_15 reserved 440h reserved reserved BUF_DIR_CTRL_GPIO_16 443h ACTIV_BIR_DIR_CTRL_GPIO_16 reserved 444h reserved reserved BUF_DIR_CTRL_GPIO_17 447h ACTIV_BIR_DIR_CTRL_GPIO_17 reserved 448h reserved reserved BUF_DIR_CTRL_GPIO_18 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 982 BUF_DIR_CTRL_GPIO_43 4AFh ACTIV_BIR_DIR_CTRL_GPIO_43 reserved 4B0h reserved reserved BUF_DIR_CTRL_GPIO_44 4B3h ACTIV_BIR_DIR_CTRL_GPIO_44 reserved 4B4h reserved reserved BUF_DIR_CTRL_GPIO_45 4B7h ACTIV_BIR_DIR_CTRL_GPIO_45 reserved 4B8h reserved reserved BUF_DIR_CTRL_GPIO_46 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 983 BUF_DIR_CTRL_GPIO_71 51Fh ACTIV_BIR_DIR_CTRL_GPIO_71 reserved 520h reserved reserved BUF_DIR_CTRL_GPIO_72 523h ACTIV_BIR_DIR_CTRL_GPIO_72 reserved 524h reserved reserved BUF_DIR_CTRL_GPIO_73 527h ACTIV_BIR_DIR_CTRL_GPIO_73 reserved 528h reserved reserved BUF_DIR_CTRL_GPIO_74 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 984 SEL_INTPI_RXAB_DSA_GAIN_4 828h B_DSA_GAIN_4 OVR_SEL_INTPI OVR_INTPI_RX _RXAB_DSA_G AB_DSA_GAIN_ 829h AIN_4 POL_INTPI_RXA SEL_INTPI_RXAB_DSA_GAIN_5 82Ch B_DSA_GAIN_5 OVR_SEL_INTPI OVR_INTPI_RX _RXAB_DSA_G AB_DSA_GAIN_ 82Dh AIN_5 POL_INTPI_RXA SEL_INTPI_RXAB_DSA_GAINSEL B_DSA_GAINSE 830h Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 985 859h POL_INTPI_RXA SEL_INTPI_RXA_DSA_GAIN_1 85Ch _DSA_GAIN_1 OVR_SEL_INTPI OVR_INTPI_RX _RXA_DSA_GAI A_DSA_GAIN_1 85Dh POL_INTPI_RXA SEL_INTPI_RXA_DSA_GAIN_2 860h _DSA_GAIN_2 OVR_SEL_INTPI OVR_INTPI_RX _RXA_DSA_GAI A_DSA_GAIN_2 861h POL_INTPI_RXB SEL_INTPI_RXB_DSA_GAIN_0 864h _DSA_GAIN_0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 986 SEL_INTPI_ADC_SYNC_N_AB_1 C_SYNC_N_AB 8A4h OVR_SEL_INTPI OVR_INTPI_AD _ADC_SYNC_N C_SYNC_N_AB 8A5h _AB_1 POL_INTPI_AD SEL_INTPI_ADC_SYNC_N_AB_2 C_SYNC_N_AB 8A8h OVR_SEL_INTPI OVR_INTPI_AD _ADC_SYNC_N C_SYNC_N_AB 8A9h _AB_2 POL_INTPI_AD SEL_INTPI_ADC_SYNC_N_CD_0 C_SYNC_N_CD 8ACh Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 987 _TX_FB_LOOP_ FB_LOOP_2 911h POL_INTPI_TX_ SEL_INTPI_TX_FB_LOOP_3 914h FB_LOOP_3 OVR_SEL_INTPI OVR_INTPI_TX_ _TX_FB_LOOP_ FB_LOOP_3 915h POL_INTPI_RXA SEL_INTPI_RXA_AGC_PIN_FREEZ _AGC_PIN_FRE 954h OVR_SEL_INTPI OVR_INTPI_RX _RXA_AGC_PIN A_AGC_PIN_FR 955h _FREEZE EEZE SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 988 OVR_SEL_INTPI OVR_INTPI_RX _RX_GAIN_SW_ _GAIN_SW_2 9EDh POL_INTPI_RX_ SEL_INTPI_RX_GAIN_SW_3 9F0h GAIN_SW_3 OVR_SEL_INTPI OVR_INTPI_RX _RX_GAIN_SW_ _GAIN_SW_3 9F1h POL_INTPI_TX_ SEL_INTPI_TX_GAIN_SW_0 A0Ch GAIN_SW_0 OVR_SEL_INTPI OVR_INTPI_TX_ _TX_GAIN_SW_ GAIN_SW_0 A0Dh Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 989 POL_INTPI_TX_ SEL_INTPI_TX_NCOSEL_3 A48h NCOSEL_3 OVR_SEL_INTPI OVR_INTPI_TX_ A49h _TX_NCOSEL_3 NCOSEL_3 USE_SERIAL_G reserved reserved reserved reserved F00h POL_INTPO_SP 1004h IB1_SDO OVR_SEL_INTP OVR_INTPO_SP 1005h O_SPIB1_SDO IB1_SDO SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 990 OVR_INTPO_RX O_RXC_PKDET C_PKDET_2 1095h POL_INTPO_RX 1098h C_PKDET_3 OVR_SEL_INTP OVR_INTPO_RX O_RXC_PKDET C_PKDET_3 1099h POL_INTPO_RX 109Ch D_PKDET_0 OVR_SEL_INTP OVR_INTPO_RX O_RXD_PKDET D_PKDET_0 109Dh POL_INTPO_RX 10A0h D_PKDET_1 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 991 OVR_INTPO_FB O_FBAB_PKDE AB_PKDET_2 11ADh POL_INTPO_FB 11B0h AB_PKDET_3 OVR_SEL_INTP OVR_INTPO_FB O_FBAB_PKDE AB_PKDET_3 11B1h POL_INTPO_FB 11B4h CD_PKDET_0 OVR_SEL_INTP OVR_INTPO_FB O_FBCD_PKDE CD_PKDET_0 11B5h POL_INTPO_FB 11B8h CD_PKDET_1 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 992 LARM_1 READ_INTPO_A 1418h LARM_2 READ_INTPO_D AC_SYNC_N_A 1419h READ_INTPO_D AC_SYNC_N_A 141Ah READ_INTPO_A PI_DONE_INTE 141Fh RRUPT READ_INTPO_D AC_SYNC_N_C 1424h READ_INTPO_D AC_SYNC_N_C 1425h READ_INTPO_G 1433h EN_INTR0 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 993 XAB_DSA_GAIN 17DDh READ_INTPI_R XCD_DSA_GAIN 17DEh READ_INTPI_R XCD_DSA_GAIN 17DFh READ_INTPI_R XCD_DSA_GAIN 17E0h READ_INTPI_R XCD_DSA_GAIN 17E1h READ_INTPI_R XCD_DSA_GAIN 17E2h READ_INTPI_R XCD_DSA_GAIN 17E3h READ_INTPI_R XCD_DSA_GAIN 17E4h SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 994 DC_SYNC_N_C 17FCh READ_INTPI_A DC_SYNC_N_C 17FDh READ_INTPI_T 17FEh DD_EN_TXA READ_INTPI_T 17FFh DD_EN_TXB READ_INTPI_T 1800h DD_EN_TXC READ_INTPI_T 1801h DD_EN_TXD READ_INTPI_T 1802h DD_EN_FBAB READ_INTPI_T 1803h DD_EN_FBCD Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 995 XC_ALC_INPUT 181Dh _3_B0 READ_INTPI_R XD_ALC_INPUT 181Eh _3_B0 READ_INTPI_IN TERRUPT0_TO 181Fh PMCU READ_INTPI_IN TERRUPT1_TO 1820h PMCU READ_INTPI_IN TERRUPT2_TO 1821h PMCU READ_INTPI_IN TERRUPT3_TO 1822h PMCU SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 996 READ_INTPI_R XD_ALC_INPUT 1836h _2_B1 READ_INTPI_R XA_ALC_INPUT 1837h _3_B1 READ_INTPI_R XB_ALC_INPUT 1838h _3_B1 READ_INTPI_R XC_ALC_INPUT 1839h _3_B1 READ_INTPI_R XD_ALC_INPUT 183Ah _3_B1 READ_INTPI_FB AB_ALC_INPUT 183Bh Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 997 READ_INTPI_G PIO_PKDET_WI 1851h N_FBAB READ_INTPI_G PIO_PKDET_WI 1852h N_FBCD READ_INTPI_TX 1853h _GAIN_SW_0 READ_INTPI_TX 1854h _GAIN_SW_1 READ_INTPI_TX 1855h _GAIN_SW_2 READ_INTPI_TX 1856h _GAIN_SW_3 READ_INTPI_FB 1857h _NCOSEL_0 SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 998 2.16.2 Register 201h (offset = 201h) [reset = 2h] Figure 2-2265. Register 201h IBUF_ST_GPIO_0 R/W-2h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 999 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 2-2284. Register 205 Field Descriptions Field Type Reset Description IBUF_ST_GPIO_1 Input buffer signal strength SBAU337 – May 2020 Serial Interface Register Maps Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...
  • Page 1000 2.16.9 Register 20Ah (offset = 20Ah) [reset = 0h] Figure 2-2272. Register 20Ah ODRIV_DS_GPIO_2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset 1000 Serial Interface Register Maps SBAU337 – May 2020 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated...

Table of Contents