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2.16.391 Register 52Ch (offset = 52Ch) [reset = 1h]
7
6
reserved
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
reserved
4-2
reserved
BUF_DIR_CTRL_G
1-0
PIO_75
2.16.392 Register 52Fh (offset = 52Fh) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
ACTIV_BIR_DIR_C
3-1
TRL_GPIO_75
0-0
reserved
2.16.393 Register 530h (offset = 530h) [reset = 1h]
7
6
reserved
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
reserved
4-2
reserved
SBAU337 – May 2020
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Figure 2-2654. Register 52Ch
5
4
Table 2-2670. Register 52C Field Descriptions
Type
Reset
R/W
0h
R/W
0h
R/W
1h
Figure 2-2655. Register 52Fh
5
4
Table 2-2671. Register 52F Field Descriptions
Type
Reset
R/W
0h
R/W
0h
Figure 2-2656. Register 530h
5
4
Table 2-2672. Register 530 Field Descriptions
Type
Reset
R/W
0h
R/W
0h
Copyright © 2020, Texas Instruments Incorporated
3
2
reserved
R/W-0h
Description
Controls the direction of GPIO
0 both input and output are not selected.. can be used for
analog
1 input mode
2 output mode
3 shouldnt be used
3
2
ACTIV_BIR_DIR_CTRL_GPIO_75
R/W-0h
Description
Control to indicate whether the GPIO_75 needs dynamic
ouptu t enabling.
0 to 3 --> Static direction
4 --> Use the IO for 3 pin SPI B2 SDIO.
5 --> Use the IO for 4 pin SPI B2 SDO
6 --> Use the IO for 3 pin SPI B1 SDIO.
7 --> use the IO for 4 pin SPI B1 SDO.
3
2
reserved
R/W-0h
Description
Serial Interface Register Maps
IO Wrap Register Map
1
0
BUF_DIR_CTRL_GPIO_75
R/W-1h
1
0
reserved
R/W-0h
1
0
BUF_DIR_CTRL_GPIO_76
R/W-1h
1127
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