Texas Instruments AFE79 Series Programming & User Manual page 1266

The serial port of the AFE79xx is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to
define the operating modes of the AFE79xx. It is compatible with most synchronous transfer formats and
can be configured as a 3 or 4 terminal interface through register field GLOBAL_4PIN in global register
GLOBAL0. In both configurations, SCLK is the serial interface input clock and SDEN\ is serial interface
enable. For 3 terminal configuration, SDIO is a bidirectional terminal for both data in and data out. For 4
terminal configuration, SDIO is bidirectional and SDO is data out only. Data is input into the device with
the rising edge of SCLK. Data is output from the device on the falling edge of SCLK. The SPI registers
except for global register GLOBAL0 and GLOBAL1 are reset by writing a "1" to GLOBAL_SOFT_RESET
in global register GLOBAL0.
Each read/write operation is framed by signal SDEN\ (Serial Data Enable Bar) asserted low. The first two
bytes is the instruction cycle which identifies the following data transfer cycle as read or write as well as
the 15-bit address to be accessed. The data transfer cycle consists of one byte. There are 64 pages of
registers in the AFE79xx and address 0x00h-0x1Fh are assigned for global registers in every page. The
particular register page is selected by writing "1" to the corresponding page selection bits through field
GLOBAL_PAGE_SEL in global register GLOBAL_PAGE_SEL0-GLOBAL_PAGE_SEL7 (address 0x10h-
0x15h).
Both SPI-A and SPI-B of the AFE79xx also support streaming reads/writes and broadcasting as shown
below. The address automatically increments or decrements depends on the setting of register field
GLOBAL_ASCEND. The streaming addressing formation depends on the setting of register field
GLOBAL_ADDRESSING_TYPE.
read cycle. Figure A-3
Figure A-6 show the timing diagram of SPI write and read.
SDEN\
1 2 3 4
SCLK
SDI
R/W A14 A13 A12
SDO
SDEN\
1 2 3 4
SCLK
SDI
R/W A14 A13 A12
SDO
1266
Appendix: SPI Interface
Figure A-1
and Figure A-4 show an example of SPI streaming write and read.
5 6 7 8 9 10 11
A11 A10 A9 A8 A7 A6 A5
Figure A-1. SPI Write Bus Cycle
5 6 7 8 9 10 11
A11 A10 A9 A8 A7 A6 A5
Figure A-2. SPI Read Bus Cycle
Copyright © 2020, Texas Instruments Incorporated
Appendix: SPI Interface
and Figure A-2 show the timing of a regular SPI write and
12 13 14 15 16 17
A4 A3 A2 A1 A0 D7
12 13 14 15 16 17
A4 A3 A2 A1 A0
D7
Appendix A
SBAU337 – May 2020
Figure A-5
18 19 20 21 22 23 24
D6 D5 D4 D3 D2 D1 D0
18 19 20 21 22 23 24
D6 D5 D4 D3 D2 D1 D0
SBAU337 – May 2020
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