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2.16.341 Register 4C8h (offset = 4C8h) [reset = 1h]
7
6
reserved
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
reserved
4-2
reserved
BUF_DIR_CTRL_G
1-0
PIO_50
2.16.342 Register 4CBh (offset = 4CBh) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
ACTIV_BIR_DIR_C
3-1
TRL_GPIO_50
0-0
reserved
2.16.343 Register 4CCh (offset = 4CCh) [reset = 1h]
7
6
reserved
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
7-5
reserved
4-2
reserved
SBAU337 – May 2020
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Figure 2-2604. Register 4C8h
5
4
Table 2-2620. Register 4C8 Field Descriptions
Type
Reset
R/W
0h
R/W
0h
R/W
1h
Figure 2-2605. Register 4CBh
5
4
Table 2-2621. Register 4CB Field Descriptions
Type
Reset
R/W
0h
R/W
0h
Figure 2-2606. Register 4CCh
5
4
Table 2-2622. Register 4CC Field Descriptions
Type
Reset
R/W
0h
R/W
0h
Copyright © 2020, Texas Instruments Incorporated
3
2
reserved
R/W-0h
Description
Controls the direction of GPIO
0 both input and output are not selected.. can be used for
analog
1 input mode
2 output mode
3 shouldnt be used
3
2
ACTIV_BIR_DIR_CTRL_GPIO_50
R/W-0h
Description
Control to indicate whether the GPIO_50 needs dynamic
ouptu t enabling.
0 to 3 --> Static direction
4 --> Use the IO for 3 pin SPI B2 SDIO.
5 --> Use the IO for 4 pin SPI B2 SDO
6 --> Use the IO for 3 pin SPI B1 SDIO.
7 --> use the IO for 4 pin SPI B1 SDO.
3
2
reserved
R/W-0h
Description
Serial Interface Register Maps
IO Wrap Register Map
1
0
BUF_DIR_CTRL_GPIO_50
R/W-1h
1
0
reserved
R/W-0h
1
0
BUF_DIR_CTRL_GPIO_51
R/W-1h
1107
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