Omron SYSMAC CS Series Operation Manual page 122

AR Area
Address Bits
AR 09 00 High-speed counter 1
commands
01
02
03
04
102
Function
High-
speed
Counter
Start Bit
High-
speed
Counter
Reset Bit
Measure-
ment Start
Bit (mea-
surement
mode 1 or
2)
Measure-
ment
Direction
Specifica-
tion Bit
(measure-
ment
mode 2)
Range
Compari-
son Result
Clear Bit
Details
OFF: Stops counter operation. The
high-speed counter PV is held.
ON: Starts counter operation. The
high-speed counter PV is not
reset.
OFF: If the counter reset method is
set to a software reset in the Unit
Setup Area (DM 6605 and DM
6607), the high-speed counter PV
is not cleared when internal I/O
refresh is performed in the Cus-
tomizable Counter Unit. If the
counter reset method is set to a
phase Z + software reset, phase-Z
input is disabled.
ON: If the counter reset method is
set to a software reset in the Unit
Setup Area (DM 6605 and DM
6607), the high-speed counter PV
is cleared when internal I/O refresh
is performed in the Customizable
Counter Unit. If the counter reset
method is set to a phase Z + soft-
ware reset, phase-Z input is
enabled.
OFF: Measurement for high-speed
counter rate of change or fre-
quency measurement is disabled.
ON: Starts measurement for high-
speed counter rate of change or
frequency measurement.
Note 1: Frequency measurement
is possible only with counter 1.
Note 2: This bit is valid only when
the measurement mode set in the
Unit Setup Area (DM 6606 and
DM 6608) is set to high-speed
counter rate of change (measure-
ment mode 1) or frequency mea-
surement (measurement mode 2).
Specifies the direction (up or
down) of the pulse input for which
frequency measurement is per-
formed.
OFF: Up
ON: Down
Note: Be sure to set this bit before
turning ON the Measurement Start
Bit.
OFF: The instruction execution
result (AR 10) or the output bit pat-
tern (AR 11) that is output when
the CTBL instruction is executed
for a range comparison on the
high-speed counter is not cleared.
ON: The instruction execution
result (AR 10) or the output bit pat-
tern (AR 11) that is output when
the CTBL instruction is executed
for a range comparison on the
high-speed counter is cleared.
Section 6-4
Controlled Forced
by set/reset
User Enabled