Processor - Kontron CP3002-RC User Manual

3u compactpci processor board based on the intel core i7 processor with the intel qm57 chipset
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CP3002-RC/CP3002-RA
2.
Functional Description
2.1

Processor

The CP3002-RC/CP3002-RA supports the low-power, high-performance, 64-bit, dual-core In-
tel® Core™ i7-620LE processor with 2.0 GHz clock speed.
The Intel® Core™ i7 multi-chip package processor used on the CP3002-RC/CP3002-RA in-
cludes an integrated high-performance graphics controller and a DDR3 dual-channel memory
controller with ECC support as well as one x16 PCI Express 2.0 port operating at 2.5 GT/s. It
support various technologies, such as:
• Intel® Hyper-Threading Technology
• Intel® Turbo Boost Technology
• Intel® Intelligent Power Sharing (IPS)
• Intel® SpeedStep® Technology
• Intel® Virtualization Technology
• Intel® Streaming SIMD Extensions 4.1
• Intel® Streaming SIMD Extensions 4.2
• Intel® 64 Architecture
• Execute Disable Bit
The Intel® Hyper-Threading Technology allows one execution core to function as two logical
processors. When this feature is used on the CP3002-RC/CP3002-RA, four processor cores
are present to the operating system. This results in higher processing throughput and improved
performance on the multithreaded software.
The Intel® Turbo Boost Technology and the Intel® Intelligent Power Sharing technology allow
the processor and the graphics controller to opportunistically and automatically run faster than
its rated operating clock frequency if it is operating below power, temperature, and current lim-
its.
The Intel® SpeedStep® technology enables real-time dynamic switching of the voltage and fre-
quency between several modes. This is achieved by switching the bus ratios, the core operat-
ing voltage, and the core processor speeds without resetting the system.
The Intel® Core™ i7 processor used on the CP3002-RC/CP3002-RA has the following multi-
level cache structure:
• 64 kB L1 cache for each core
• 32 kB instruction cache
• 32 kB data cache
• 256 kB L2 instruction/data cache for each core
• 4 MB L3 shared instruction/data cache shared between both cores
ID 1039-3625, Rev. 1.0
Functional Description
Page 2 - 3

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