Reset Status Register (Rstat) - Kontron CP3002-RC User Manual

CP3002-RC/CP3002-RA
4.3.6

Reset Status Register (RSTAT)

The Reset Status Register is used to determine the host's reset source.
Table 4-11: Reset Status Register (RSTAT)
REGISTER NAME
ADDRESS
BIT NAME
7 PORS Power-on reset status:
0 = System reset generated by software (warm reset)
1 = System reset generated by power-on (cold reset)
Writing a '1' to this bit clears the bit.
6 - 2 Res. Reserved
1 CPRS CompactPCI reset status (PRST signal):
0 = System reset not generated by CPCI reset input
1 = System reset generated by CPCI reset input
Writing a '1' to this bit clears the bit.
0 WTRS Watchdog timer reset status:
0 = System reset not generated by Watchdog timer
1 = System reset generated by Watchdog timer
Writing a '1' to this bit clears the bit.
Note ...
The reset status register is set to the default values by power-on reset, not by a
warm reset.
ID 1039-3625, Rev. 1.0

RESET STATUS REGISTER (RSTAT)

0x285
DESCRIPTION
Configuration
RESET
ACCESS
VALUE
N/A R/W
00000 R
0 R/W
0 R/W
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