Status Byte And Service Request (Srq) - Keithley 2001 Operator's Manual

IEEE-488 Reference
When a message is placed in the Error Queue, the Error
Available (EAV) bit in the Status Byte Register is set. An er-
ror message is cleared from the Error/Status Queue when it
is read. The Error Queue is considered cleared when it is
empty. An empty Error Queue clears the EAV bit in the Sta-
tus Byte Register. An error message from the Error Queue is
read by sending either of the following SCPI query com-
mands and then addressing the Model 2001 to talk:
:SYSTem:ERRor?
:STATus:QUEue?
Service
Request
Generation
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Status byte and service request (SRQ)

Status Byte Register  The summary messages from the
status registers and queues are used to set or clear the
appropriate bits (B0, B2, B3, B4, B5 and B7) of the Status
Byte Register. These bits do not latch and their states (0 or 1)
are solely dependent on the summary messages (0 or 1). For
example, if the Standard Event Status Register is read, its
register will clear. As a result, its summary message will
reset to 0, which in turn will clear the ESB bit in the Status
Byte Register.
Bit B6 in the Status Byte Register is either:
4-20
Refer to paragraphs
(:SYSTem:ERRor?) for complete information on reading er-
ror messages.
4.6.9
Service request is controlled by two 8-bit registers; the Status
Byte Register and the Service Request Enable Register. The
structure of these registers is shown in
Status Summary Messages
RQS
* STB ?
OSB (B6) ESB MAV
Serial Poll
(B7) (B5) (B4)
MSS
&
&
&
OR
* SRE
OSB ESB MAV
(B7) (B6) (B5) (B4)
* SRE ?
OSB = Operation Summary Bit
MSS = Master Summary Status
RQS = Request for Service
ESB = Event Summary Bit
MAV = Message Available
QSB = Questionable Summary Bit
EAV = Error Available
MSB = Measurement Summary Bit
& = Logical AND
OR = Logical OR
For description of the other bits in the Status Byte Register,
refer to
4.21
Status byte and service request (SRQ)
Read by Serial Poll
Status Byte
QSB EAV MSB
Register
(B3) (B2) (B1) (B0)
Read by *STB ?
&
&
&
Service Request
QSB EAV MSB
Enable Register
(B3) (B2) (B1) (B0)
• The Master Summary Status (MSS) bit, sent in response
to the *STB? command, indicates the status of any set
bits with corresponding enable bits set.
• The Request for Service (RQS) bit, sent in response to
a serial poll, indicates which device was requesting ser-
vice by pulling on the SRQ line.
paragraph 4.10.14.
2001-900-01 Rev. K / August 2010
(:STATus:QUEue?) and
Figure 4-13.
4.22