Queues; Status Byte And Service Request (Srq) - Keithley 2002 User Manual

IEEE-488 Reference

3.7.5 Queues

The Model 2002 uses two queues; the Output Queue and the
Error Queue. The queues are first-in first-out (FIFO) regis-
ters. The Output Queue is used to hold readings and response
messages, and the Error Queue is used to hold error mes-
sages and status messages. The Model 2002 status model
(Figure 3-4) shows how the two queues are structured with
the other registers.
Output Queue — The Output Queue is used to hold data that
pertains to the normal operation of the instrument. For exam-
ple, when a query command is sent, the response message is
placed in the Output Queue.
When data is placed in the Output Queue, the Message
Available (MAV) bit in the Status Byte Register sets. A data
message is cleared from the Output Queue when it is read.
The Output Queue is considered cleared when it is empty. An
empty Output Queue clears the MAV bit in the Status Byte
Register.
A message from the Output Queue is read by addressing the
Model 2002 to talk after the appropriate query is sent.
Error Queue — The Error Queue is used to hold error mes-
sages and status messages. When an error or status event
occurs, a message that defines the error/status is placed in the
Error Queue. This queue will hold up to 10 messages.
When a message is placed in the Error Queue, the Error
Available (EAV) bit in the Status Byte Register is set. An
error message is cleared from the Error/Status Queue when
it is read. The Error Queue is considered cleared when it is
empty. An empty Error Queue clears the EAV bit in the Sta-
tus Byte Register. An error message from the Error Queue is
read by sending either of the following SCPI query com-
mands and then addressing the Model 2002 to talk:
:SYSTem:ERRor?
:STATus:QUEue?
Refer to paragraphs 3.20.7 (:STATus:QUEue?) and 3.21.5
(:SYSTem:ERRor?) for complete information on reading
error messages.

3.7.6 Status byte and service request (SRQ)

Service request is controlled by two 8-bit registers; the Status
Byte Register and the Service Request Enable Register. The
structure of these registers is shown in Figure 3-12.
3-16
Status Byte Register — The summary messages from the
status registers and queues are used to set or clear the appro-
priate bits (B0, B2, B3, B4, B5 and B7) of the Status Byte
Register. These bits do not latch and their states (0 or 1) are
solely dependent on the summary messages (0 or 1). For
example, if the Standard Event Status Register is read, its
register will clear. As a result, its summary message will
reset to 0, which in turn will clear the ESB bit in the Status
Byte Register.
Bit B6 in the Status Byte Register is either:
• The Master Summary Status (MSS) bit, sent in
response to the *STB? command, indicates the status of
any set bits with corresponding enable bits set.
• The Request for Service (RQS) bit, sent in response to
a serial poll, indicates which device was requesting ser-
vice by pulling on the SRQ line.
For description of the other bits in the Status Byte Register,
refer to paragraph 3.10.12.
The IEEE-488.2 standard uses the following common query
command to read the Status Byte Register:
When reading the Status Byte Register using the *STB?
command, bit B6 is called the MSS bit. None of the bits in
the Status Byte Register are cleared when using the *STB?
command to read it.
The IEEE-488.1 standard has a serial poll sequence that also
reads the Status Byte Register and is better suited to detect a
service request (SRQ). When using the serial poll, bit B6 is
called the RQS bit. Serial polling causes bit B6 (RQS) to
reset. Serial polling is discussed in more detail later in this
paragraph (see "Serial Poll and SRQ").
Any of the following operations clear all bits of the Status
Byte Register:
• Cycling power.
• Sending the *CLS common command.
The MAV bit may or may not be cleared.
*STB?
NOTE