Keithley 2001 Operator's Manual page 169

cáÖìêÉ=QJU
Sequence event status
To Bit B6 (Arm) of
Operation Event
Condition Register
(See Figure 4-7).
Seq 1 = Sequence 1 (Set bit indicates that the
cáÖìêÉ=QJV
Arm event status
2001-900-01 Rev. K/ August 2010
OR
To Sequence 1 Bit
(Seq 1) of Arm
Event Condition
Register (See
Figure 4-8).
Lay1 = Layer 1 (Set bit indicates that 2001 is
in arm layer 1).
Lay2 = Layer 2 (Set bit indicates that 2001 is
in arm layer 2).
(B15)
(B15)
OR
(B15)
2001 is in the arm layer of Sequence 1)
Always Lay2 Lay1
Zero
(B15) (B2)
(B1)
(B14 - B3)
0
Lay2 Lay1
(B15) (B2)
(B1)
(B14 - B3)
0
Lay2 Lay1
(B15) (B2)
(B1)
(B14 - B3)
0
&
&
&
Lay2 Lay1
(B15) (B14 - B3) (B2) (B1)
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
Seq1
(B1)
(B14 - B2)
0
Seq1
(B1)
(B14 - B2)
0
&
&
Seq1
(B1)
(B14 - B2)
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
IEEE-488 Reference
Sequence
Condition Register
(B0)
PTR
Sequence
Transition Filter
(B0) NTR
Sequence Event
Register
(B0)
Sequence Event
Enable Register
(B0)
PTR
Arm
Transition Filter
(B0) NTR
Arm Event
Register
(B0)
Arm Event
Enable Register
(B0)
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