Sequence Event Status - Keithley 2001 Operator's Manual

IEEE-488 Reference
 This is a latched, read-only register
whose bits are set by the Arm Condition Register and Tran-
sition Filter. Once a bit in this register is set, it will remain
set (latched) until the register is cleared by a specific clearing
operation. The bits of this register are logically ANDed with
the bits of the Arm Event Enable Register and applied to an
OR gate. The output of the OR gate is the Arm Summary Bit
that is applied to the Operation Condition Register. The fol-
lowing SCPI query command can be used to read the Arm
Event Register:
:STATus:OPERation:ARM:EVENt?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations
that will clear the Operation Event Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the :STATus:OPERation:ARM?
command.
by the user and serves as a mask for the Arm Event Register.
When masked, a set bit (B1) in the Arm Event Register will
not set the Waiting for Arm bit in the Operation Condition
Register. Conversely, when unmasked, a set bit (B1) in the
Arm Event Register will set the Waiting for Arm bit.
Bit B1 in the Arm Event Register is masked when the corre-
sponding bit (B1) in the Arm Event Enable Register is
cleared (0). When the masked bit of the Arm Event Register
sets, it is ANDed with the corresponding cleared bit in the
Arm Event Enable Register. The logic "0" output of the
AND gate is applied to the input of the OR gate and thus, will
not set the Waiting for Arm bit in the Operation Condition
Register.
Bit B1 in the Arm Event Register is unmasked when the cor-
responding bit (B1) in the Arm Event Enable Register is set
(1). When the unmasked bit of the Arm Event Register sets,
it is ANDed with the corresponding set bit in the Arm Event
Enable Register. The logic "1" output of the AND gate is ap-
plied to the input of the OR gate and thus, will set the Waiting
for Arm bit in the Operation Condition Register.
Bit B1 of the Arm Event Enable Register can be set or
cleared by using the following SCPI command:
:STATus:OPERation:ARM:ENABle
<NRf>
The following SCPI query command can be used to read the
Arm Event Enable Register:
4-12
query
 This register is programmed
:STATus:OPERation:ARM:ENABle?
Reading this register using the above SCPI command will
not clear the register. The following list summarizes opera-
tions that will clear the Arm Event Enable Register:
1. Cycling power.
2. Sending the :STATus:OPERation:ARM:ENABle
command.
4.6.4

Sequence event status

The reporting of sequence events is controlled by a set of 16-
bit registers; the Sequence Condition Register, the Transition
Filter, the Sequence Event Register and the Sequence Event
Enable Register. cáÖìêÉ=QJV= shows how these registers are
structured.
Two bits of this register set are used by the Model 2001 to re-
port sequence events. Bit B1 (In arm layer 1) is set when in-
strument is in (or exited) the arm layer (arm layer 1) of
operation. Bit B2 (In arm layer 2) is set when the instrument
is in (or exited) the scan layer (arm layer 2). The operation
process over the bus is explained in
The various registers used for sequence event status are de-
scribed as follows. Note that these registers are controlled by
the :STATus:OPERation:ARM:SEQuence commands of the
:STATus subsystem (see paragraph
Sequence Condition Register  This is a real-time 16-bit
read-only register that constantly updates to reflect the cur-
rent arm layer status of the instrument. For example, if the
Model 2001 is currently in the scan layer of operation, bit B2
(In arm layer 2) of this register will be set.
The following SCPI query command can be used to read the
Sequence Condition Register:
:STATus:OPERation:ARM:SEQuence:CO
NDition?
The Sequence Condition Register and the Transition Filter
are used to set the bits of the Sequence Event Register. The
Transition Filter is discussed next.
Sequence Transition Filter  The transition filter is made
up of two 16-bit registers that are programmed by the user. It
is used to specify which transition (0 to 1, or 1 to 0) in the
Sequence Condition Register will set the corresponding bit
in the Sequence Event Register.
The filter can be programmed for positive transitions (PTR),
negative transitions (NTR) or both. When an event bit is pro-
grammed for a positive transition, the event bit in the Se-
quence Event Register will set when the corresponding bit in
2001-900-01 Rev. K / August 2010
0
paragraph 4.7.
4.21).