Serial Memory Interface - Infineon TRAVEO T2G Cluster 4M Lite Kit User Manual

TRAVEO™ T2G Cluster 4M Lite Kit user guide
KIT_T2G_C-2D-4M_LITE
Hardware blocks
Figure 24 shows the connection of the JTAG to the 20-pin Arm® converter from I-jet to the same JTAG header
X302.
Figure 24 Connecting i-Jet to JTAG header X302
3.6

Serial memory interface

The Serial Memory Interface (SMIF) is a master that provides a low pin count connection to off-chip SPI devices,
such as EEPROM, FRAM, MRAM, or NAND memories, in SDR or DDR mode, and HYPERBUS™ devices such as
HYPERFLASH™ (NOR flash) and HYPERRAM™ (PSRAM and pseudo static RAM). SMIF provides two modes for data
transfer operation to and from external devices:
• eXecute-In-Place (XIP) mode: The read and write transfers on the XIP AXI interface are translated on-the-fly to
external device SPI transfers.
• MMIO mode: This mode supports MMIO-based accesses to external devices. The MMIO operation mode is less
efficient than the XIP operation mode for read and write operations. However, it is more flexible than the XIP
operation mode and this helps to implement other device operations in addition to read and write operations,
such as programming and changing power modes.
This kit has two SMIF devices:
• SMIF0 – SEMPER™ Flash (S26HL)
• SMIF1 – HYPERRAM™ (S27KL)
Figure 25 shows the location of SEMPER™ Flash and HYPERRAM™ mounted in this kit.
User guide 27 002-39200 Rev. **
2023-12-11