User Manuals: Infineon XMC4500 series Microcontroller

Manuals and User Guides for Infineon XMC4500 series Microcontroller. We have 2 Infineon XMC4500 series Microcontroller manuals available for free PDF download: Reference Manual, Application Manual

Infineon XMC4500 series Reference Manual (2689 pages)

ARM Cortex-M4 32-bit processor core

Brand: Infineon | Category: Microcontrollers | Size: 18 MB

Table of Contents

8
- Table 6-5 Table
  8
- Table 7-2 Table
  8
- Table 7-4 Table
  9
- Table 8-1 Table
  10
- Table 8-3 Table
  11
- Table 8-5 Table
  12
- Table 8-7 Table
  13
- Table 8-9 Table
  14
- Table 8-11 Table
  15
- Table 9-2 Table
  16
- Table 9-4 Table
  17
- Table 10-2 Table
  18
- Table 10-4 Table
  19
- Table 11-2 Table
  20
- Table 11-6 Table
  21
- Table 12-1 Table
  22
- Table 12-3 Table
  23
- Table 12-5 Table
  24
- Table 12-7 Table
  25
- Table 12-9 Table
  26
- Table 13-2 Table
  27
- Table 13-6 Table
  28
- Table 16-1 Table
  32
- Table 16-3 Table
  33
- Table 16-5 Table
  34
- Table 16-7 Table
  35
- Table 17-1 Table
  36
- Table 17-3 Table
  37
- Table 17-5 Table
  38
- Table 17-7 Table
  39
- Introduction
  48
- Introduction
  49
- Overview
  49
- Block Diagram
  51
- CPU Subsystem
  52
- On-Chip Memories
  53
- Communication Peripherals
  54
- Analog Frontend Peripherals
  56
- Industrial Control Peripherals
  57
- On-Chip Debug Support
  57
- Central Processing Unit (CPU)
  60
- Overview
  60
- Features
  61
- Block Diagram
  61
- Programmers Model
  63
- Processor Mode and Privilege Levels for Software Execution
  63
- Stacks
  63
- Table 6-3 Table
  64
- Core Registers
  65
- Table 2-2 Table
  66
- Exceptions and Interrupts
  76
- Data Types
  76
- The Cortex Microcontroller Software Interface Standard
  76
- CMSIS Functions
  77
- Table 2-4 Table
  77
- Memory Model
  79
- Memory Regions, Types and Attributes
  79
- Memory System Ordering of Memory Accesses
  80
- Behavior of Memory Accesses
  81
- Software Ordering of Memory Accesses
  82
- Memory Endianness
  83
- Synchronization Primitives
  83
- Exception Model
  85
- Exception States
  85
- Instruction Set
  85
- Programming Hints for the Synchronization Primitives
  85
- Exception Types
  86
- Exception Handlers
  88
- Vector Table
  89
- Exception Priorities
  90
- Interrupt Priority Grouping
  90
- Exception Entry and Return
  91
- Fault Handling
  95
- Fault Types
  96
- Fault Escalation and Hard Faults
  97
- Fault Status Registers and Fault Address Registers
  98
- Lockup
  98
- Power Management
  99
- Entering Sleep Mode
  99
- The External Event Input
  100
- Wakeup from Sleep Mode
  100
- System Control Block
  101
  - Power Management Programming Hints
    101
- System Control Block Design Hints and Tips
  102
- System Timer, Systick
  102
- Systick Design Hints and Tips
  102
- Nested Vectored Interrupt Controller (NVIC)
  102
- Level-Sensitive and Pulse Interrupts
  103
- Using CMSIS Functions to Access NVIC
  104
- NVIC Design Hints and Tips
  104
- Memory Protection Unit (MPU)
  105
- MPU Access Permission Attributes
  107
- MPU Mismatch
  109
- Updating an MPU Region
  109
- MPU Design Hints and Tips
  112
- Floating Point Unit (FPU)
  112
- Enabling the FPU
  113
- PPB Registers
  113
- Table 2-6 Table
  114
- SCS Registers
  117
- Table 2-8 Table
  130
- Systick Registers
  143
- NVIC Registers
  146
- MPU Registers
  152
- FPU Registers
  160
- Bus System
  170
- Bus Interfaces
  170
- Bus Matrix
  170
- Service Request Processing
  173
- Overview
  173
- Features
  173
- Block Diagram
  174
- Service Request Distribution
  175
- Interrupt Service Requests
  176
- Functional Description
  179
- DMA Line Router (DLR)
  179
- DMA Service Request Source Selection
  182
- Event Request Unit (ERU)
  187
- Event Request Select Unit (ERS)
  188
- Event Trigger Logic (Etlx)
  189
- Cross Connect Matrix
  191
- Output Gating Unit (Oguy)
  192
- Initialization and System Dependencies
  195
- Debug Behavior
  195
- Power, Reset and Clock
  195
- Service Request Generation
  195
- Registers
  196
- DLR Registers
  196
- Table 2-10 Table
  196
- Table 2-12 Table
  196
- ERU Registers
  201
- Interconnects
  206
- ERU1 Connections
  207
- ERU0 Connections
  207
- Table 2-14 Table
  209
- Table 2-16 Table
  210
- Table 2-18 Table
  211
- General Purpose DMA (GPDMA)
  217
- Overview
  217
- Features
  217
- Block Diagram
  219
- Functional Description
  220
- Terminology
  220
- Variable Definitions
  223
- Flow Controller and Transfer Type
  224
- Handshaking Interface
  225
- Hardware Handshaking
  226
- Software Handshaking
  226
- Handshaking with GPDMA as Flow Controller
  227
- Handshaking with Peripheral as Flow Controller
  229
- FIFO Usage
  230
- Bus and Channel Locking
  231
- Scatter/Gather
  233
- Abnormal Transfer Termination
  236
- Basic Transfers
  237
- Block Transfer with GPDMA as the Flow Controller
  238
- Effect of Maximum AMBA Burst Length on a Block Transfer
  239
- Multi Block Transfers
  243
- Block Chaining Using Linked Lists
  243
- Table 2-20 Table
  247
- Auto-Reloading of Channel Registers
  248
- Contiguous Address between Blocks
  248
- Suspension of Transfers between Blocks
  248
- Ending Multi-Block Transfers
  249
- Single-Block Transfer
  250
- Programing Examples
  250
- Multi-Block Transfer with Source Address Auto-Reloaded and Contiguous Destination Address
  251
- Multi-Block Transfer with Source and Destination Address Auto-Reloaded
  255
- Multi-Block Transfer with Source Address Auto-Reloaded and Linked List Destination Address
  259
- Multi-Block DMA Transfer with Linked List for Source and Contiguous Destination Address
  264
- Multi-Block Transfer with Linked List for Source and Destination
  267
- Service Request Generation
  273
- Power, Reset and Clock
  274
- Initialization and System Dependencies
  274
- Registers
  275
- Table 2-22 Table
  276
- Table 4-1 Table
  277
- Table 4-3 Table
  278
- Configuration and Channel Enable Registers
  279
- Channel Registers
  281
- Table 5-2 Table
  309
- Table 4-7 Table
  309
- Table 4-9 Table
  309
- Table 4-5 Table
  309
- Table 5-6 Table
  312
- Interrupt Registers
  315
- Software Handshaking Registers
  330
- Miscellaneous GPDMA Registers
  340
- Flexible CRC Engine (FCE)
  342
- Overview
  342
- Features
  342
- Application Mapping
  343
- Block Diagram
  343
- Functional Description
  344
- Basic Operation
  346
- Automatic Signature Check
  346
- Register Protection and Monitoring Methods
  347
- Service Request Generation
  349
- Initialization and System Dependencies
  350
- Power, Reset and Clock
  350
- Debug Behavior
  350
- Registers
  352
- Table 5-10 Table
  352
- Table 6-1 Table
  352
- System Registers Description
  353
- CRC Kernel Control/Status Registers
  354
- Properties of CRC Code
  365
- Interconnects
  365
- Memory Organization
  368
- Overview
  368
- Features
  368
- Cortex-M4 Address Space
  368
- Memory Regions
  370
- Memory Map
  370
- Service Request Generation
  374
- Initialization and System Dependencies
  376
- Power, Reset and Clock
  376
- Debug Behavior
  376
- Registers
  377
- Flash and Program Memory Unit (PMU)
  381
- Overview
  381
- Block Diagram
  381
- Boot ROM (BROM)
  382
- BROM Addressing
  382
- Prefetch Unit
  382
- Overview
  382
- Operation
  383
- Instruction Buffer
  383
- Data Buffer
  383
- PMU Interface
  384
- Program Flash (PFLASH)
  385
- Overview
  385
- Features
  385
- Definition of Terms
  386
- Flash Structure
  387
- Flash Read Access
  388
- Flash Write and Erase Operations
  389
- Modes of Operation
  389
- Command Sequences
  390
- Command Sequence Definitions
  390
- Flash Page Programming Example
  394
- Flash Protection
  397
- Configuring Flash Protection in the UCB
  397
- Flash Read Protection
  398
- Flash Write and OTP Protection
  400
- System Wide Effects of Flash Protection
  402
- Data Integrity and Safety
  402
- Error-Correcting Code (ECC)
  402
- Margin Checks
  403
- Service Request Generation
  403
- Interrupt Control
  404
- Trap Control
  404
- Handling Errors During Operation
  405
- SQER "Sequence Error
  405
- PFOPER "Operation Error
  406
- PROER "Protection Error
  406
- VER "Verification Error
  407
- PFSBER/DFSBER "Single-Bit Error
  408
- Handling Flash Errors During Startup
  409
- Power, Reset and Clock
  409
- Power Supply
  409
- Power Reduction
  409
- Reset Control
  411
- Resets During Flash Operation
  411
- Clock
  413
- Registers
  413
- PMU Registers
  413
- PMU ID Register
  414
- Prefetch Registers
  415
- Prefetch Configuration Register
  415
- Flash Registers
  417
- Flash Status Definition
  418
- Flash Configuration Control
  423
- Flash Identification Register
  428
- Margin Check Control Register
  429
- Protection Configuration Indication
  429
- Window Watchdog Timer (WDT)
  435
- Overview
  435
- Features
  435
- Block Diagram
  436
- Time-Out Mode
  437
- Pre-Warning Mode
  438
- Bad Service Operation
  439
- Power, Reset and Clock
  441
- Initialization and Control Sequence
  441
- Debug Behavior
  441
- Service Request Processing
  441
- Initialization & Start of Operation
  442
- Reconfiguration & Restart of Operation
  442
- Software Stop & Resume Operation
  443
- Enter Sleep/Deep Sleep & Resume Operation
  443
- Prewarning Alarm Handling
  443
- Registers
  445
- Registers Description
  445
- Interconnects
  450
- Real Time Clock (RTC)
  452
- Overview
  452
- Features
  452
- Block Diagram
  452
- RTC Operation
  453
- Register Access Operations
  454
- Periodic Wake-Up Trigger Generation
  455
- Timer Alarm Wake-Up Trigger Generation
  455
- Periodic Service Request
  455
- Wake-Up from Hibernation Trigger
  455
- Timer Alarm Service Request
  455
- Service Request Processing
  455
- Debug Behavior
  456
- Power, Reset and Clock
  456
- Initialization and Control Sequence
  456
- Initialization & Start of Operation
  456
- Re-Configuration & Re-Start of Operation
  457
- Configure and Enable Periodic Event
  457
- Configure and Enable Timer Event
  457
- Registers
  459
- Registers Description
  459
- Interconnects
  471
- Features
  472
- Overview
  472
- System Control Unit (SCU)
  472
- Block Diagram
  473
- Miscellaneous Control Functions
  476
- Startup Software Support
  476
- Service Requests
  477
- Service Request Sources
  477
- Memory Parity Protection
  478
- Parity Error Handling
  478
- Trap Generation
  480
- Trap Sources
  480
- Die Temperature Measurement
  481
- Temperature Measurement
  481
- Offset Adjustment
  482
- Gain Adjustment
  483
- Retention Memory
  484
- Functional Description
  485
- Out of Range Comparator Control
  485
- Power Management
  485
- System States
  486
- Hibernate Domain Operating Modes
  488
- Embedded Voltage Regulator (EVR)
  490
- Power-On Reset
  490
- Supply Watchdog (SWD)
  491
- Power Validation
  491
- Supply Voltage Brown-Out Detection
  491
- Hibernate Domain Power Management
  492
- Flash Power Control
  492
- Hibernate Control
  492
- Hibernate Mode
  492
- Hibernate Domain Pin Functions
  493
- System Level Integration
  494
- Reset Control
  496
- Supported Reset Types
  496
- Block Diagram
  498
- Reset Status
  498
- Peripheral Reset Control
  498
- Clock Control
  498
- Clock Sources
  500
- Clock System Overview
  501
- Clock System Architecture
  502
- High Precision Oscillator Circuit (OSC_HP)
  506
- Backup Clock Source
  507
- Main PLL
  508
- Features
  508
- System PLL Functional Description
  508
- Configuration and Operation of the Prescaler Mode
  512
- Bypass Mode
  514
- System Oscillator Watchdog (OSC_WDG)
  514
- Factory Calibration
  515
- Automatic Calibration
  515
- PLL Power down Mode
  515
- Internally Generated System Clock Calibration
  515
- VCO Power down Mode
  515
- Alternative Internal Clock Calibration
  516
- Usb Pll
  518
- Ultra Low Power Oscillator
  520
- OSC_ULP Oscillator Watchdog (ULPWDG)
  520
- Internal Slow Clock Source
  520
- Clock Gating Control
  520
- Debug Behavior
  520
- Power, Reset and Clock
  521
- Initialization and System Dependencies
  522
- Power-Up
  523
- Power-On Reset Release
  524
- System Reset Release
  525
- Clock System Setup
  527
- Configuration of Special System Functions
  529
- Configuration of Miscellaneous Functions
  530
- Registers
  532
- GCU Registers
  532
- PCU Registers
  583
- HCU Registers
  589
- RCU Registers
  597
- CCU Registers
  615
- LED and Touch-Sense (LEDTS)
  642
- Overview
  642
- Features
  642
- Block Diagram
  643
- Functional Overview
  645
- LED Drive Mode
  648
- LED Pin Assignment and Current Capability
  650
- Touch-Sense Mode
  651
- Finger Sensing
  654
- Operating both LED Drive and Touch-Sense Modes
  655
- Service Request Processing
  655
- Debug Behavior
  656
- Power, Reset and Clock
  656
- Initialisation and System Dependencies
  656
- Function Enabling
  656
- Interpretation of Bit Field FNCOL
  657
- LEDTS Timing Calculations
  658
- Time-Multiplexed LED and Touch-Sense Functions on Pin
  659
- LEDTS Pin Control
  659
- Software Hints
  661
- Hardware Design Hints
  662
- Registers
  663
- Registers Description
  664
- Interconnects
  677
- Features
  679
- Overview
  679
- SD/MMC Interface (SDMMC)
  679
- Block Diagram
  680
- Functional Description
  682
- Card Detection
  684
- Read/ Write Operation
  685
- Special Command Types
  687
- Debug Behavior
  688
- Power, Reset and Clocks
  688
- Error Detection
  688
- Initialisation and System Dependencies
  690
- Setup SDMMC Data Transfer
  690
- Read Operation
  692
- Write Operation
  692
- Abort Transaction
  693
- Registers
  694
- Registers Description
  698
- Table 13-8
  739
- Table 13-9
  744
- Interconnects
  767
- External Bus Unit (EBU)
  770
- Overview
  770
- Features
  770
- Block Diagram
  771
- Interface Signals
  772
- Allocation of Unused Signals as GPIO
  775
- Signal States When EBU Is Inactive
  777
- Memory Controller Structure
  779
- Memory Controller AHBIF Bridge
  780
- AHB Error Generation
  781
- Clocking Modes
  782
- Clocking Strategy and Local Clock Generation
  782
- Write Data Buffering
  782
- Read Data Buffering
  782
- Clock Requirements
  784
- Standby Mode
  784
- External Bus Operation
  785
- External Memory Regions
  785
- Chip Select Control
  787
- Programmable Device Types
  787
- Support for Multiplexed Device Configurations
  787
- Support for Non-Multiplexed Device Configurations
  790
- AHB Bus Width Translation
  791
- Address Alignment During Bus Accesses
  792
- External Bus Arbitration
  793
- External Bus Modes
  793
- Arbitration Signals and Parameters
  793
- Sole Master Mode
  796
- Arbiter Mode
  796
- No Bus Mode
  796
- Arbitration Modes
  796
- Participant Mode
  800
- Arbitration Input Signal Sampling
  802
- Locking the External Bus
  803
- Reaction to an AHB Access to the External Bus
  804
- Pending Access Time-Out
  805
- Arbitrating SDRAM Control Signals
  805
- Start-Up/Boot Process
  805
- Standard Access Phases
  805
- Address Phase (AP)
  806
- Address Hold Phase (AH)
  806
- Command Delay Phase (CD)
  807
- Command Phase (CP)
  807
- Data Hold Phase (DH)
  808
- Burst Phase (BP)
  808
- Recovery Phase (RP)
  809
- Asynchronous Read/Write Accesses
  810
- Signal List
  811
- Standard Asynchronous Access Phases
  812
- Control of ADV & CS Delays During Asynchronous Accesses
  812
- Programmable Parameters
  813
- Accesses to Multiplexed Devices
  814
- Dynamic Command Delay and Wait State Insertion
  815
- External Extension of the Command Phase by WAIT
  815
- Interfacing to Nand Flash Devices
  817
- NAND Flash
  819
- Synchronous Read/Write Accesses
  821
- Signals
  822
- Support for Four Burst FLASH Device Types
  823
- Typical Burst Flash Connection
  823
- Burst Flash Clock
  823
- Standard Access Phases
  824
- Burst Length Control
  825
- Control of ADV & CS Delays During Burst FLASH Access
  825
- Burst Flash Clock Feedback
  826
- Asynchronous Address Phase
  827
- Page Mode Support
  827
- Critical Word First Read Accesses
  828
- Example Burst Flash Access Cycle
  828
- External Cycle Control Via the WAIT Input
  830
- Flash Non-Array Access Support
  831
- Termination of a Burst Access
  831
- Burst Flash Device Programming Sequences
  832
- Cellular RAM
  832
- Programmable Parameters
  834
- SDRAM Interface
  836
- Features
  836
- Signal List
  836
- External Bus Clock Generation
  837
- External Interface
  837
- SDRAM Characteristics
  838
- Supported SDRAM Commands
  839
- SDRAM Device Size
  840
- Power up Sequence
  840
- Initialization Sequence
  840
- Mobile SDRAM Support
  843
- Short Burst Accesses
  844
- Burst Accesses
  844
- Multibanking Operation
  845
- Bank Mask
  846
- Row Mask
  847
- Banks Precharge
  848
- Refresh Cycles
  849
- Self-Refresh Mode
  851
- SDRAM Addressing Scheme
  852
- Power down Mode
  859
- Programmable Parameters
  860
- SDRAM Recovery Phases
  860
- Module Reset
  862
- Debug Behavior
  862
- Clocks
  862
- Power, Reset and Clock
  862
- Power
  863
- System Dependencies
  863
- Registers
  864
- General Control Registers
  866
- Region Control Registers
  871
- SDRAM Control Registers
  884
- Ethernet MAC (ETH)
  893
- Overview
  893
- ETH Core Features
  894
- DMA Block Features
  895
- Transaction Layer (MTL) Features
  895
- Functional Description
  897
- Monitoring, Test, and Debugging Support Features
  897
- Block Diagram
  897
- ETH Core
  898
- Transmission
  898
- MAC Transmit Interface Protocol
  902
- Reception
  902
- MAC Transaction Layer (MTL)
  910
- Transmit Path
  910
- Receive Path
  916
- DMA Controller
  918
- Initialization
  919
- Transmission
  922
- Reception
  927
- Interrupts
  931
- DMA Descriptors
  933
- Descriptor Formats
  933
- MAC Management Counters
  966
- Power Management Block
  966
- PMT Block Description
  967
- Remote Wake-Up Frame Detection
  969
- Magic Packet Detection
  969
- System Considerations During Power-Down
  970
- PHY Interconnect
  971
- PHY Interconnect Selection
  971
- Station Management Interface
  971
- Station Management Functions
  972
- Station Management Write Operation
  973
- Station Management Read Operation
  973
- Media Independent Interface
  974
- Reduced Media Independent Interface
  975
- RMII Block Diagram
  976
- RMII Block Overview
  976
- RMII Transmit Timing Diagrams
  977
- Transmit Bit Ordering
  977
- IEEE 1588-2002 Overview
  980
- Reference Timing Source
  982
- Transmit Path Functions
  982
- Receive Path Functions
  982
- Time Stamp Error Margin
  983
- Frequency Range of Reference Timing Clock
  983
- Advanced Time Stamp Feature Support
  984
- Peer-To-Peer PTP (Pdelay) Transparent Clock (P2P TC) Message Support
  984
- Clock Types
  986
- PTP Processing and Control
  987
- Reference Timing Source (for Advance Timestamp Feature)
  991
- Transmit Path Functions
  992
- Receive Path Functions
  992
- System Time Register Module
  993
- Application BUS Interface
  995
- Service Request Generation
  997
- DMA Service Requests
  998
- Power Management Service Requests
  998
- System Time Module
  998
- MAC Management Counter Service Requests
  998
- Debug
  999
- Power Reset and Clock
  999
- ETH Registers
  1000
- Register Description
  1000
- Registers Overview
  1001
- Registers Description
  1017
  - Interconnects
    1224
- Universal Serial Bus (USB)
  1229
  - Block Diagram
    1230
  - Functional Description
    1231
- USB Device
  1232
- FIFO Architecture
  1233
- Device FIFO Architecture
  1234
- Programming Overview
  1235
- Core Initialization
  1239
- Host Programming Overview
  1240
- Host Connection
  1241
- Channel Initialization in Buffer DMA or Slave Mode
  1242
- Halting a Channel
  1243
- Selecting the Queue Depth
  1244
- Handling Disconnects
  1245
- Host Programming for Various USB Transactions
  1246
- Host Programming in Slave Mode
  1248
- Writing the Transmit FIFO in Slave Mode
  1249
- Reading the Receive FIFO in Slave Mode
  1250
- Control Transactions in Slave Mode
  1251
- Handling Interrupts
  1252
- Bulk and Control OUT/SETUP Transactions in Slave Mode
  1253
- Handling Interrupts
  1255
- Interrupt in Transactions in Slave Mode
  1256
- Handling Interrupts
  1257
- Interrupt out Transactions in Slave Mode
  1259
- Isochronous in Transactions in Slave Mode
  1262
- Handling Interrupts
  1263
  - Isochronous out Transactions in Slave Mode
    1264
- Handling Interrupts
  1265
- Host Programming in Buffer DMA Mode
  1266
- Normal Bulk and Control in Operations
  1267
- Bulk and Control OUT/SETUP Transactions in Buffer DMA Mode
  1268
- NAK and NYET Handling with Internal DMA
  1269
  - Handling Interrupts
    1271
- Interrupt in Transactions in Buffer DMA Mode
  1273
  - Handling Interrupts
    1274
- Interrupt out Transactions in Buffer DMA Mode
  1275
- Handling Interrupts
  1277
- Isochronous in Transactions in Buffer DMA Mode
  1278
- Handling Interrupts
  1279
  - Isochronous out Transactions in Buffer DMA Mode
    1280
  - Handling Interrupts
    1281
- Host Programming in Scatter-Gather DMA Mode
  1283
- IN Memory Structure
  1287
- OUT Memory Structure
  1290
- Channel Initialization in Scatter-Gather DMA Mode
  1292
- Asynchronous Transfers
  1293
- Asynchronous Transfer Descriptor
  1294
- Isochronous Transactions
  1295
- Interrupt Transactions
  1298
- Device Programming Overview
  1300
- Device Disconnection
  1301
- Endpoint Initialization
  1302
- Initialization on Enumeration Completion
  1303
- Initialization on Setconfiguration/Setinterface Command
  1304
- Programming out Endpoint Features
  1305
- Setting the Global out NAK
  1306
- Transfer Stop Programming for out Endpoints
  1307
- IN Endpoint Disable
  1308
- Timeout for Control in Endpoints
  1309
- Transfer Stop Programming for in Endpoints
  1310
- Worst-Case Response Time
  1311
- Handling Babble Conditions
  1312
- Device Programming Operations in Buffer DMA or Slave Mode
  1313
- Device Programming in Slave Mode
  1315
- Control Read Transfers (SETUP, Data IN, Status OUT)
  1316
- Two-Stage Control Transfers (Setup/Status IN)
  1317
- Packet Read from FIFO
  1319
- IN Data Transfers
  1321
- OUT Data Transfers
  1322
- Handling more than Three Back-To-Back SETUP Packets
  1325
- Non-Periodic (Bulk and Control) in Data Transfers
  1326
- Examples
  1327
- Non-Isochronous out Data Transfers
  1332
- Isochronous out Data Transfers
  1336
- Incomplete Isochronous out Data Transfers
  1342
- Incomplete Isochronous in Data Transfers
  1344
- Device Programming in Buffer DMA Mode
  1355
- Control Read Transfers (SETUP, Data IN, Status OUT)
  1356
  - Two-Stage Control Transfers (Setup/Status IN)
    1357
- Non-Periodic (Bulk and Control) in Data Transfers
  1360
- Non-Isochronous out Data Transfers
  1362
- Incomplete Isochronous out Data Transfers
  1364
- Periodic in (Interrupt and Isochronous) Data Transfers
  1366
- Periodic in Data Transfers Using the Periodic Transfer Interrupt
  1368
- Interrupt out Data Transfers Using Periodic Transfer Interrupt
  1374
- Device Programming in Scatter-Gather DMA Mode
  1376
- SPRAM Requirements
  1377
- OUT Data Memory Structure
  1378
- Isochronous out
  1384
- Descriptor Update Interrupt Enable Modes
  1390
- Control Transfer Handling
  1391
- Application Programming Sequence
  1392
- Internal Data Flow
  1399
- Three-Stage Control Read
  1402
- Two-Stage Control Transfer
  1404
- Back to Back SETUP During Control Write
  1405
- Back-To-Back Setups During Control Read
  1408
- Extra Tokens During Control Write Data Phase
  1410
- Extra Tokens During Control Read Data Phase
  1412
- Premature SETUP During Control Write Data Phase
  1414
- Premature SETUP During Control Read Data Phase
  1417
- Premature Status During Control Write
  1419
- Premature Status During Control Read
  1421
- Lost ACK During Last Packet of Control Read
  1423
- Bulk in Transfer in Scatter-Gather DMA Mode
  1424
- Bulk out Transfer in Scatter-Gather DMA Mode
  1429
- Interrupt Transfer Handling in Scatter/Gather DMA Mode
  1433
- Interrupt out Transfer in Scatter/Gather DMA Mode
  1434
- Isochronous out Transfer in Scatter/Gather DMA Mode
  1439
- OTG Revision 1.3 Programming Model
  1441
- B-Device Session Request Protocol
  1442
- A-Device Host Negotiation Protocol
  1444
- B-Device Host Negotiation Protocol
  1445
- Clock Gating Programming Model
  1446
- Host Mode Suspend and Remote Wakeup with Clock Gating
  1447
- Host Mode Session End and Start with Clock Gating
  1448
- Device Mode Suspend and Resume with Clock Gating
  1449
- Device Mode Session End and Start with Clock Gating
  1450
- Device Mode RAM Allocation
  1452
- Host Mode RAM Allocation
  1455
- Dynamic FIFO Allocation
  1457
- Dynamic FIFO Reallocation in Device Mode
  1458
  - Service Request Generation
    1459
- Debug Behaviour
  1460
- Power, Reset and Clock
  1461
- Registers
  1462
  - Register Description
    1469
  - Interconnects
    1572
- Universal Serial Interface Channel (USIC)
  1573
- Operating the USIC
  1578
- Output Signals
  1580
- Baud Rate Generator
  1581
- Channel Events and Interrupts
  1582
- Operating the USIC Communication Channel
  1586
- Protocol Control and Status
  1587
- Mode Control
  1588
- General Channel Events and Interrupts
  1589
- Data Transfer Events and Interrupts
  1590
- Baud Rate Generator Event and Interrupt
  1592
- Protocol-Specific Events and Interrupts
  1594
- General Input Structure
  1595
- Digital Filter
  1597
- Selected Input Monitoring
  1598
- External Frequency Input
  1599
- Capture Mode Timer
  1600
- Time Quanta Counter
  1601
- Master and Shift Clock Output Configuration
  1602
- Operating the Transmit Data Path
  1603
- Transmit Data Shift Mode
  1604
- Transmit Control Information
  1605
- Transmit Data Validation
  1606
- Operating the Receive Data Path
  1608
- Receive Data Shift Mode
  1609
- Baud Rate Constraints
  1610
- Operating the FIFO Data Buffer
  1611
- FIFO Buffer Partitioning
  1612
- Transmit Buffer Events and Interrupts
  1613
- Receive Buffer Events and Interrupts
  1617
- FIFO Buffer Bypass
  1622
- FIFO Access Constraints
  1623
- Handling of FIFO Transmit Control Information
  1624
- Asynchronous Serial Channel (ASC = UART)
  1626
  - Frame Format
    1627
- Idle Time
  1628
- Start Bit Detection
  1629
- Operating the ASC
  1630
  - Baud Rate Generation
    1631
- Noise Detection
  1632
- Automatic Shadow Mechanism
  1634
- Mode Control Behavior
  1635
- Data Transfer Interrupt Handling
  1636
- Protocol-Related Argument and Error
  1637
- ASC Protocol Registers
  1638
- ASC Protocol Status Register
  1641
- Hardware LIN Support
  1644
- Synchronous Serial Channel (SSC)
  1646
- Transmit and Receive Data Signals
  1648
- Shift Clock Signals
  1649
- Slave Select Signals
  1651
- Operating the SSC
  1653
- Disabling SSC Mode
  1654
- Transfer Mode
  1656
  - Baud Rate Generator Interrupt Handling
    1657
- Operating the SSC in Master Mode
  1659
  - Baud Rate Generation
    1660
- MSLS Generation
  1661
- Automatic Slave Select Update
  1662
- Slave Select Delay Generation
  1663
- Protocol Interrupt Events
  1664
- End-Of-Frame Control
  1665
- Operating the SSC in Slave Mode
  1667
  - End-Of-Frame Control
    1668
- SSC Protocol Registers
  1669
- SSC Protocol Status Register
  1673
- SSC Timing Considerations
  1675
- Delay Compensation in Master Mode
  1678
- Complete Closed-Loop Delay Compensation
  1679
- Inter-IC Bus Protocol (IIC)
  1680
- Symbols
  1681
- Frame Format
  1682
- Operating the IIC
  1683
- Transmission Chain
  1684
- Non-Acknowledge and Error Conditions
  1685
- IIC Protocol Interrupt Events
  1686
- Baud Rate Generator Interrupt Handling
  1687
- Receiver Handling
  1688
- Symbol Timing
  1689
- Start Symbol
  1690
- Stop Symbol
  1691
- Data Flow Handling
  1692
- Valid Master Transmit Data Formats
  1694
- Master Transmit/Receive Modes
  1697
- Slave Transmit/Receive Modes
  1699
- IIC Protocol Registers
  1700
- IIC Protocol Status Register
  1703
- Inter-IC Sound Bus Protocol (IIS)
  1706
- Protocol Overview
  1707
- Transfer Delay
  1708
- Operating the IIS
  1709
- Automatic Shadow Mechanism
  1710
- Parity Mode
  1712
- Baud Rate Generator Interrupt Handling
  1713
- Receive Buffer Handling
  1714
- Baud Rate Generation
  1715
- WA Generation
  1716
- Protocol Interrupt Events
  1717
- Protocol Events and Interrupts
  1718
- IIS Protocol Status Register
  1721
  - Service Request Generation
    1724
  - Registers
    1725
- Address Map
  1728
- Module Identification Registers
  1729
- Channel Control and Configuration Registers
  1730
- Channel Configuration Register
  1735
- Kernel State Configuration Register
  1736
- Interrupt Node Pointer Register
  1739
- Protocol Related Registers
  1740
- Protocol Status Register
  1741
- Protocol Status Clear Register
  1742
- Input Stage Register
  1743
- Baud Rate Generator Registers
  1749
- Baud Rate Generator Register
  1750
- Capture Mode Timer Register
  1753
- Transmission Control and Status Register
  1757
- Flag Modification Registers
  1763
- Data Buffer Registers
  1765
- Receive Buffer Registers RBUF0, RBUF1
  1766
- Receive Buffer Registers RBUF, RBUFD, RBUFSR
  1772
- FIFO Buffer and Bypass Registers
  1776
- General FIFO Buffer Control Registers
  1779
- Transmit FIFO Buffer Control Registers
  1785
- Receive FIFO Buffer Control Registers
  1789
- FIFO Buffer Data Registers
  1794
- FIFO Buffer Pointer Registers
  1797
  - Interconnects
    1798
- USIC Module 0 Interconnects
  1799
- USIC Module 1 Interconnects
  1807
- USIC Module 2 Interconnects
  1814
- Controller Area Network Controller (Multican)
  1823
- Overview
  1824
  - Block Diagram
    1826
- CAN Basics
  1827
- CAN Frame Formats
  1828
- Remote Frames
  1830
- Error Frames
  1832
- The Nominal Bit Time
  1833
- Error Detection and Error Handling
  1834
- Multican Kernel Functional Description
  1836
- Port Input Control
  1838
- CAN Node Control
  1839
- Bit Timing Unit
  1840
- Bitstream Processor
  1841
- Error Handling Unit
  1842
- CAN Frame Counter
  1843
- Message Object List Structure
  1845
- List of Unallocated Elements
  1846
- List Command Panel
  1847
- CAN Node Analysis Features
  1850
- Bit Timing Analysis
  1851
- Message Acceptance Filtering
  1854
- Transmit Acceptance Filtering
  1855
- Message Postprocessing
  1857
- Pending Messages
  1859
- Message Object Data Handling
  1861
- Frame Transmission
  1864
- Message Object Functionality
  1867
- Message Object FIFO Structure
  1868
- Receive FIFO
  1870
- Transmit FIFO
  1871
- Gateway Mode
  1872
- Foreign Remote Requests
  1874
- Service Request Generation
  1875
  - Debug Behavior
    1877
  - Power, Reset and Clock
    1878
- Module Clock Generation
  1880
- Register Description
  1881
- Global Module Registers
  1883
- CAN Node Registers
  1896
- Message Object Registers
  1915
- Multican Module External Registers
  1936
- Interconnects
  1942
- Port and I/O Line Control
  1943
- Multican Interrupt Output Connections
  1945
- Versatile Analog-To-Digital Converter (VADC)
  1947
- Introduction and Basic Structure
  1950
- Configuration of General Functions
  1955
- Priority Channel Assignment
  1956
- Conversion Request Generation
  1957
- Queued Request Source Handling
  1959
- Channel Scan Request Source Handling
  1962
- Request Source Arbitration
  1966
- Arbiter Operation and Configuration
  1967
- Conversion Start Mode
  1968
- Analog Input Channel Configuration
  1970
- Conversion Timing
  1972
- Alias Feature
  1973
- Conversion Modes
  1974
- Compare with Standard Conversions (Limit Checking)
  1975
- Utilizing Fast Compare Mode
  1977
- Boundary Flag Control
  1978
  - Conversion Result Handling
    1980
- Data Alignment
  1982
- Wait-For-Read Mode
  1983
- Result FIFO Buffer
  1984
- Result Event Generation
  1985
- Data Modification
  1986
- Synchronization of Conversions
  1993
- Equidistant Sampling
  1996
- Safety Features
  1997
- Signal Path Test Modes
  1998
- Configuration of Test Functions
  1999
- External Multiplexer Control
  2000
  - Service Request Generation
    2002
  - Registers
    2004
  - Module Identification
    2007
  - System Registers
    2009
  - General Registers
    2012
- Arbitration and Source Registers
  2014
- Channel Control Registers
  2042
- Result Registers
  2047
- Miscellaneous Registers
  2055
- Service Request Registers
  2067
  - Interconnects
    2079
- Analog Module Connections in the XMC4500
  2081
- Digital Module Connections in the XMC4500
  2083
- Delta-Sigma Demodulator (DSD)
  2090
  - Introduction and Basic Structure
    2093
  - Configuration of General Functions
    2094
- Modulator Clock Selection and Generation
  2096
- Input Data Selection
  2098
- External Modulator
  2099
- Main Filter Chain
  2100
- Integrator Stage
  2101
- Auxiliary Filter
  2102
- Conversion Result Handling
  2104
- Resolver Support
  2105
- Return Signal Synchronization
  2107
- Time-Stamp Support
  2109
- Module Identification
  2110
  - System Registers
    2111
- General Registers
  2113
- Input Path Control
  2114
- Filter Configuration
  2118
- Conversion Result Handling
  2122
- Service Request Registers
  2124
- Miscellaneous Registers
  2125
  - Interconnects
    2130
- Digital to Analog Converter (DAC)
  2133
  - Block Diagram
    2134
- Operating Modes
  2135
- Data FIFO Buffer (FIFO)
  2136
- Data Output Stage
  2137
- Pattern Generators (PG) - Waveform Generator
  2138
- Noise Generators (NG) - Pseudo Random Number Generator
  2139
- Entering any Operating Mode
  2140
- Data Processing Mode
  2141
- Pattern Generation Mode
  2142
- Noise Generation Mode
  2143
- Ramp Generation Mode
  2144
  - Power, Reset and Clock
    2145
  - Registers
    2147
  - Register Description
    2148
- DAC Configuration Registers
  2149
- DAC Data Registers
  2156
- DAC Pattern Registers
  2158
  - Interconnects
    2160
- Digital Connections
  2161
- Synchronization Interface of the Pattern Generator
  2162
- Capture/Compare Unit 4 (CCU4)
  2164
  - Features
    2165
  - Block Diagram
    2167
  - Functional Description
    2169
  - Input Selector
    2171
  - Connection Matrix
    2173
- Starting/Stopping the Timer
  2175
  - Counting Modes
    2176
  - Calculating the PWM Period and Duty Cycle
    2177
  - Updating the Period and Duty Cycle
    2178
  - Edge Aligned Mode
    2182
  - Center Aligned Mode
    2183
  - Single Shot Mode
    2184
  - Active/Passive Rules
    2185
- External Start/Stop
  2186
  - External Counting Direction
    2188
  - External Gating Signal
    2190
  - External Load
    2191
  - External Capture
    2192
  - External Modulation
    2198
  - TRAP Function
    2200
  - Status Bit Override
    2202
- Multi-Channel Control
  2203
  - Timer Concatenation
    2206
  - PWM Dithering
    2211
  - Prescaler
    2216
  - Normal Prescaler Mode
    2217
- CCU4 Usage
  2219
  - Prescaler Usage
    2221
- PWM Dither
  2223
  - Capture Mode Usage
    2226
  - Service Request Generation
    2231
  - Debug Behavior
    2234
- Module Reset
  2235
  - Power
    2236
  - Registers
    2238
  - Global Registers
    2244
- Slice (Cc4Y) Registers
  2261
  - Interconnects
    2294
- CCU41 Pins
  2299
- CCU42 Pins
  2304
- CCU43 Pins
  2309
- Capture/Compare Unit 8 (CCU8)
  2315
  - Features
    2316
  - Block Diagram
    2319
  - Functional Description
    2321
- Input Selector
  2323
- Connection Matrix
  2325
- Start/Stop Control
  2327
- Counting Modes
  2328
- Calculating the PWM Period and Duty Cycle
  2329
- Updating the Period and Duty Cycle
  2330
- Edge Aligned Mode
  2334
- Center Aligned Mode
  2335
- Single Shot Mode
  2336
- Active/Passive Rules
  2337
- Edge Aligned Compare Modes
  2342
- Center Aligned Compare Modes
  2346
- External Events Control
  2349
- External Counting Direction
  2352
- External Gating Signal
  2353
- External Count Signal
  2354
- External Load
  2355
- External Capture
  2356
- External Modulation
  2361
- Trap Function
  2363
- Status Bit Override
  2366
- Multi-Channel Support
  2367
- Timer Concatenation
  2372
- Output Parity Checker
  2377
  - PWM Dithering
    2381
- Prescaler
  2385
- Normal Prescaler Mode
  2386
- CCU8 Usage
  2388
- Prescaler Usage
  2390
- PWM Dither
  2393
- Capture Mode Usage
  2395
- Parity Checker Usage
  2400
  - Service Request Generation
    2403
- Debug Behavior
  2406
- Clocks
  2407
  - Power
    2408
- System Dependencies
  2409
  - Registers
    2410
- Global Registers
  2418
- Slice (Cc8Y) Registers
  2438
  - Interconnects
    2481
- CCU81 Pins
  2489
- Position Interface Unit (POSIF)
  2498
  - Features
    2499
- Block Diagram
  2500
  - Functional Description
    2501
- Function Selector
  2503
- Hall Sensor Control
  2504
- Quadrature Decoder Control
  2510
- Quadrature Clock and Direction Decoding
  2513
- Index Control
  2514
- Stand-Alone Multi-Channel Mode
  2515
- Using the POSIF
  2516
- Quadrature Decoder Mode Usage
  2518
- Stand-Alone Multi-Channel Mode
  2524
  - Service Request Generation
    2525
- Quadrature Decoder Flags
  2527
  - Debug Behavior
    2529
  - Power, Reset and Clock
    2530
- Power
  2531
  - System Dependencies
    2532
  - Registers
    2533
  - Global Registers
    2535
- Hall Sensor Mode Registers
  2543
- Multi-Channel Mode Registers
  2545
- Quadrature Decoder Registers
  2550
  - Interrupt Registers
    2551
  - Interconnects
    2558
- POSIF0 Pins
  2559
- POSIF1 Pins
  2563
- General Purpose I/O Ports (PORTS)
  2569
- Features
  2570
  - Definition of Terms
    2571
- GPIO and Alternate Function
  2572
- Output Operation
  2573
- Hardware Controlled I/Os
  2574
  - Power Saving Mode Operation
    2575
- Analog Ports
  2576
  - Power, Reset and Clock
    2577
  - Initialization and System Dependencies
    2578
  - Registers
    2579
- Port Input/Output Control Registers
  2582
- Pad Driver Mode Register
  2586
- Pin Function Decision Control Register
  2590
- Port Output Register
  2592
- Port Output Modification Register
  2593
- Port Input Register
  2594
- Port Pin Power Save Register
  2595
- Port Pin Hardware Select Register
  2596
- Package Pin Summary
  2598
- Port I/O Functions
  2605
- Table 14-1 Table
  2606
- Port I/O Function Table
  2606
- Table 14-3 Table
  2607
- Table 14-5 Table
  2608
- Table 14-7 Table
  2610
- Startup Modes
  2613
- Startup Modes
  2615
- Initial Boot Sequence
  2616
- Boot Mode Selection
  2617
- Normal Boot Mode
  2618
- Boot from PSRAM
  2623
- Alternative Boot Mode - Address0 (ABM-0)
  2624
- Alternative Boot Mode - Address1 (ABM-1)
  2627
- CAN BSL Mode
  2630
- Boot Mode Index (BMI)
  2633
  - Debug Behavior
    2637
- Failures and Handling
  2638
  - Power, Reset and Clock
    2640
  - Clocking
    2641
- Debug and Trace System (DBG)
  2645
- Debug System Operation
  2648
- Trace Port Interface Unit (TPIU)
  2649
- Serial Wire Interface Driven System Reset
  2650
- Halting Debug and Peripheral Suspend
  2653
- Timestamping
  2655
- ROM Table
  2656
- Debug System Registers
  2658
  - Internal Pull-Up and Pull-Down on JTAG Pins
    2659
  - Debug Connector
    2660

Infineon XMC4500 series Application Manual (10 pages)

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Infineon XMC4500 series Application Manual (10 pages)

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