Infineon C166S V1 SubSystem Manuals

Infineon C166S V1 SubSystem Manuals

Manuals and User Guides for Infineon C166S V1 SubSystem. We have 1 Infineon C166S V1 SubSystem manual available for free PDF download: User Manual

Infineon C166S V1 SubSystem User Manual

Infineon C166S V1 SubSystem User Manual (460 pages)

Brand: Infineon | Category: Microcontrollers | Size: 3.4 MB

Table of Contents

Table of Contents
5
1 Introduction

11
- The Members of the 16-Bit Microcontroller Family
  12
- Summary of Basic Features
  13
Watchdog Timer

14
2 System Overview

17
3 Central Processing Unit

31
- Register Description Format
  33
- CPU Special-Function Registers
  35
- Instruction Fetch and Program Flow Control
  37
- Branch Target Addressing Modes
  37
- Sequential and Non-Sequential Instruction Flow
  39
- ATOMIC and Extended Instructions
  43
- Code Addressing Via Code Segment and Instruction Pointer
  44
- The Cpu/System Configuration Register SYSCON
  47
- Interrupt and Exception Execution
  48
- Interrupt System Structure
  49
- Interrupt Arbitration
  49
- Interrupt Vector Table
  52
- Interrupt Control Functions in the Processor Status Word
  52
- Saving the Status During Interrupt Service
  54
- Context Switching
  54
- Traps
  56
- Software Traps
  56
- Hardware Traps
  56
- Peripheral Event Controller
  62
- The PEC Source and Destination Pointers
  63
- PEC Control Registers
  66
- Short Transfer Mode
  68
- Long Transfer Mode
  69
- Channel Link Mode for Data Chaining
  71
- PEC Channels Assignment and Arbitration
  73
- Programmable End of PEC Interrupt Level
  74
- Using General-Purpose Registers
  76
- Context Switch
  80
- Data Addressing
  82
- Short Addressing Modes
  82
- Long and Indirect Addressing Modes
  84
- Addressing Via Data
  85
- DPP Override Mechanism in the C166S
  87
- Long Addressing Mode
  88
- Indirect Addressing Modes
  89
- The System Stack
  91
- Stack Overflow and Underflow
  92
- Linear Stack
  94
- Circular (Virtual) Stack
  95
- Data Processing
  98
- Data Types
  98
- Constants
  100
- The 16-Bit Adder/Subtracter, Barrel Shifter and the 16-Bit Logic Unit
  100
- Bit-Manipulation Unit
  100
- Multiply and Divide Unit
  102
- The Processor Status Word Register (PSW)
  106
- Instruction Pipeline
  110
- Particular Pipeline Effects
  110
- General Considerations
  111
- Specific Cases with Core Registers
  111
- Common Portable Solution
  116
- Instruction State Times
  117
- Dedicated Csfrs
  119
- Summary of CPU Registers
  121
- General Purpose Registers
  121
- Core Special Function Registers Ordered by Name
  123
- Core Special Function Registers Ordered by Address
  124
- Register Overview C166S Interrupt and Peripheral Event Controller
  125
4 Memory Organization

127
- Data Organization in Memory
  129
- Internal Local Memory Area
  130
- DPRAM and SFR-Area
  131
- Data Memories
  131
- Special Function Register Areas
  131
- PEC Source and Destination Pointers
  133
- External Memory Space
  134
- External Data Accesses
  134
- Crossing Memory Boundaries
  135
- System Stack
  136
- Data Organization in General Purpose Registers
  136
- SFR / ESFR Table
  138
- Interrupt Vector Table
  169
5 Instruction Set

179
- Short Instruction Summary
  179
- Instruction Set Summary
  181
  - Instruction Opcodes
    194
  - Instruction Description
    199
- Detailed Instruction Set
  
  207
7 Parallel Ports

308
- Alternate Port Functions
  308
- The External Bus Interface
  
  323
  - Single-Chip Mode
    324
  - Multiplexed Bus Modes
    325
    
    Demultiplexed Bus Modes
    328
    
    Switching Among the Bus Modes
    331
  - Programmable Bus Characteristics
    338
    
    Programmable Memory Cycle Time
    339
    
    Read/Write Signal Delay
    340
  - Controlling the External Bus Controller
    343
  - EBC Idle State
    352
  - External Bus Arbitration
    353
  - The XBUS Interface
    357
    
    XBUS Access Control
    359
  - Operation of the Watchdog Timer
    364
Asynchronous/Synchronous Serial Interface (ASC)

367
- Operational Overview
  370
- General Operation
  371
  - Asynchronous Operation
    375
    
    Asynchronous Data Frames
    376
    
    Asynchronous Transmission
    377
    
    Asynchronous Reception
    378
  - Synchronous Operation
    380
    
    Synchronous Transmission
    381
  - Baudrate Generation
    383
    
    Baudrate in Synchronous Mode
    387
  - Hardware Error Detection Capabilities
    389
High-Speed Synchronous Serial Interface (SSC)

391
- General Operation
  393
  - Operating Mode Selection
    395
  - Full-Duplex Operation
    400
  - Half-Duplex Operation
    403
  - Continuous Transfers
    404
  - Baudrate Generation
    405
  - Error Detection Mechanisms
    407
- General Purpose Timer Unit
  409
12 General Purpose Timer Unit

411
- Functional Description of Timer Block 1
  411
  - Core Timer T3
    413
  - Auxiliary Timers T2 and T4
    424
  - Timer Concatenation
    429
- Functional Description of Timer Block 2
  434
  - Core Timer T6
    436
  - Auxiliary Timer T5
    442
  - Timer Concatenation
    446
Instruction Index

453
Keyword Index

455

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