Page 1 3 2 - b i t Microcontrollers ® T r i C o r e T C 1 . 6 P & T C 1 . 6 E Instruction Set 32-bit Unified Processor Core U s e r M a n u a l ( V o l u m e 2 ) V1.0 2013-07 M i c r o c o n t r o l l e r s...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 3 2 - b i t Microcontrollers ® T r i C o r e T C 1 . 6 P & T C 1 . 6 E Instruction Set 32-bit Unified Processor Core U s e r M a n u a l ( V o l u m e 2 ) V1.0 2013-07 M i c r o c o n t r o l l e r s...
Page 4 Page Description Trademarks TriCore™ is a trademark of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of our documentation.
Page 5: Table Of Contents
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Preface 1 Compare Instructions 11 Instruction Set Information 1 Simple Compare 11 Instruction Syntax 1 Accumulating Compare 11 Operand Definitions 1 Compare with Shift 12 Instruction Mnemonic 1 Packed Compare 12 Operation Modifiers 2 Bit Operations 13 Data Type Modifiers 3...
Page 6: Preface
Please note that: • Unless stated otherwise in the text, all descriptions are common to all TriCore versions listed in this preface. Additional Information For information and links to documentation for Infineon products that use TriCore, visit: http://www.infineon.com/32-bit-microcontrollers User Manual (Volume 2)
Page 7 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Preface Text Conventions This document uses the following text conventions: • The default radix is decimal. – Hexadecimal constants are suffixed with a subscript letter ‘H’, as in: FFC – Binary constants are suffixed with a subscript letter ‘B’, as in: 111 •...
Page 8: Instruction Set Information
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Instruction Set Information This chapter contains descriptions of all TriCore™ instructions. The instruction mnemonics are grouped into families of similar or related instructions, then listed in alphabetical order within those groups. Notes 1.
Page 9: Operation Modifiers
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Some instructions, typically 16-bit instructions, use a General Purpose Register (GPR) as an implicit source or destination. Table 1-2 Implicit Operand Definitions Operand Definition D[15] Implicit Data register for many 16-bit instructions A[10] Stack Pointer (SP) A[11]...
Page 10: Data Type Modifiers
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.1.4 Data Type Modifiers The data type modifiers used in the instruction mnemonics are listed here. When multiple suffixes occur in an instruction, the order of occurrence in the mnemonic is the same as the order in this table: Table 1-4 Data Type Modifiers Data Type...
Page 11: Bit Opcode Formats
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.2.2 32-bit Opcode Formats Note: Bit[0] of the op1 field is always 1 for 32-bit instructions. Table 1-6 32-bit Opcode Formats off18 off18 off18 s1/d [9:6] [13:10] off18[5:0] [17:14] ABSB off18...
Page 12: Opcode Field Definitions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.2.3 Opcode Field Definitions Table 1-7 Opcode Field Definitions Name Width Definition Source register(s) one Source register(s) number two Source register(s) number three Destination register For a register pair (E), the coding follows the register number: E[0] = 0000 , E[2] = 0010 , E[4] = 0100...
Page 13: Instruction Operation Syntax
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Instruction Operation Syntax The operation of each instruction is described using a ‘C-like’ Register Transfer Level (RTL) notation. Notes 1. The numbering of bits begins with bit zero, which is the least-significant bit of the word. 2.
Page 14 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Table 1-8 RTL Syntax Syntax Definition TRUE Boolean true. Equivalent to integer 1 FALSE Boolean false. Equivalent to integer 0 Logical AND. Returns a boolean result Logical OR. Returns a boolean result Logical XOR.
Page 15: Rtl Functions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.3.1 RTL Functions Register Transfer Level functions are defined in the table which follows. Table 1-9 RTL Functions Function Definition abs(x) abs(x) returns ((x <0) ? (0 - x) : x); cache_address_ivld(EA) Defined in ‘Cache RTL Functions’, which follows cache_address_wb(EA)
Page 16: Cache Rtl Functions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.3.2 Cache RTL Functions CACHE[ ] is a syntactic structure which hides the implementation characteristics of the cache implemented. CACHE can be associatively accessed either by: • A single argument which is an address. •...
Page 17 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Table 1-10 Cache Functions Function Definition cache_index_wi if (CACHE[index,elem].valid==1) then { if (CACHE[index,elem].modified==1) then { pa = CACHE[index,elem].physical_address; M[pa,cacheline] = CACHE[index,elem].data; CACHE[index,elem].modified = 0; CACHE[index,elem].valid = 0; cache_Index_wb(location) if ((CACHE[index,elem].valid==1) AND (CACHE[index,elem].modified==1)) then { pa = CACHE[index,elem].physical_address;...
Page 18: Floating Point Operation Syntax
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information 1.3.3 Floating Point Operation Syntax The following table defines the floating point operation syntax. Table 1-11 Floating Point Operation Syntax Syntax Definition ADD_NAN 7FC00001 MUL_NAN 7FC00002 SQRT_NAN 7FC00004 DIV_NAN 7FC00008 POS_INFINITY...
Page 19 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Table 1-11 Floating Point Operation Syntax Syntax Definition round_to_q31(x,y) Returns a Q format result of infinite width by rounding the real value ‘x’ to a Q format value using the IEEE-754-1985 mode specified by ‘y’. i_real(x) Returns a infinitely accurate real number of equal value to the 32-bit signed integer value ‘x’.
Page 20: Coprocessor Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Coprocessor Instructions ® The TriCore instruction set architecture may be extended with implementation defined, application specific coprocessor instructions. These instructions are executed on dedicated coprocessor hardware attached to the coprocessor interface.
Page 21: Psw Status Flags (User Status Bits)
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information PSW Status Flags (User Status Bits) The Status section of a given instruction description lists the five status flags that may be affected by the operation. The PSW logically groups the five user bits together as shown below. Notes 1.
Page 22 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Information Note: The execution of User-1 mode instructions in User-1 mode may be disabled by the SYSCON .U1_IED register. A PRIV trap will result if execution is attempted. User Manual (Volume 2) 1-15 V1.0 2013-07...
Page 23: Instruction Set Overview
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Instruction Set Overview This chapter provides an overview of the TrICore® Instruction Set Architecture (ISA). The basic properties and use of each instruction type are desribed, together with a description of the selection and use of the 16-bit (short) instructions.
Page 24: Multiply And Multiply-Add
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview 2.1.3 Multiply and Multiply-Add For the multiplication of 32-bit integers, the available mnemonics are: • MUL (Multiply Signed) • MULS (Multiply Signed with Saturation) • MULS.U (Multiply Unsigned with Saturation) These translate to machine instructions producing either 32-bit or 64-bit results, depending on whether the destination operand encoded in the assembly instruction is a single data register D[n] (where n = 0, 1, …15), or an extended data register E[n] (where n = 0, 2, …14).
Page 25: Logical
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview The conditional instructions provide efficient alternatives to conditional jumps around very short sequences of code. All of the conditional instructions use a condition operand that controls the execution of the instruction. The condition operand is a data register, with any non-zero value interpreted as TRUE, and a zero value interpreted as FALSE.
Page 26: Shift
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Data Register 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 Count Leading Zero Logic TC1044 Figure 2-1 Operation of the CLZ Instruction...
Page 27 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Source Registers Destination Register Sign Fill Width TC1046B Figure 2-2 EXTR Operation Source Registers Destination Register Zero fill Width TC1045B Figure 2-3 EXTR.U Operation DEXTR The DEXTR instruction concatenates two data register sources to form a 64-bit value from which 32 consecutive bits are extracted.
Page 28: Packed Arithmetic
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview INSERT The INSERT instruction takes the width least-significant bits of a source data register, shifted left by pos bits and substitutes them into the value of another source register. All other (32-w) bits of the value of the second register are passed through.
Page 29 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Byte 3 Byte 2 Byte 1 Byte 0 Operand m Byte 3 Byte 2 Byte 1 Byte 0 Operand n Operation Destination 3 Destination 2 Destination 1 Destination 0 Result TC1050B Figure 2-7 Packed Byte Data Format...
Page 30: Psw (Program Status Word) Status Flags And Arithmetic Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview PSW (Program Status Word) Status Flags and Arithmetic Instructions Arithmetic instructions operate on data and addresses in registers. Status information about the result of the arithmetic operations is recorded in the five status flags in the Program Status Word (PSW) register. 2.3.1 Usage The status flags can be read by software using the Move From Core Register (MFCR) instruction, and can be...
Page 31: Special Case: -1 * -1
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview 2.4.2 Special Case: -1 * -1 When multiplying two maximum-negative 1.15 format values (-1), the result is the positive number (+1). For example: 8000H * 8000H = 4000 0000H This is correctly interpreted in Q format as: -1(1.15 format) * -1(1.15 format) = +1 (2.30 format) However, when the result is shifted left by 1 (left-justified), the result is 8000 0000H.
Page 32: Packed Multiply And Packed Mac
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview • MUL.Q (Multiply Q format) • MULR.Q (Multiply Q format with Rounding) The operand encodings for the MUL.Q instruction distinguish between 16-bit source operands in either the upper D[n]U or lower half D[n]L of a data register, 32-bit source operands (D[n]), and 32-bit or 64-bit destination operands (D[n] or E[n]).
Page 33: Compare Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Compare Instructions The compare instructions perform a comparison of the contents of two registers. The Boolean result (1 = true and 0 = false) is stored in the least-significant bit of a data register. The remaining bits in the register are cleared to zero.
Page 34: Compare With Shift
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview D[a] D[b] A < B ? D[c] op = AND, OR or XOR D[c] TC1052B Figure 2-9 Combining LT Comparison with Boolean Operation The evaluation of the following C expression can be optimized using the combined compare-Boolean operation: d5 = (d1 <...
Page 35: Bit Operations
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview produce two extended Booleans. The EQ.H instruction results in two extended Booleans: FFFF for a match and 0000 for no match. There are also abnormal packed-word compare instructions that compare two words in the normal way, but produce a single extended Boolean.
Page 36: Accumulating Bit Operations
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview D[a] D[b] op = AND, NAND, OR, NOR, Boolean op XOR, XNOR, ANDN or ORN D[c] TC1055B Figure 2-12 Boolean Operations 2.6.2 Accumulating Bit Operations Evaluation of complex Boolean equations can use the 3-input Boolean operations, in which the output of a two- input instruction, together with the least-significant bit of a third data register, forms the input to a further operation.
Page 37: Address Arithmetic
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview D[a] D[b] op = AND, ANDN, NAND, Boolean op NOR, OR, ORN, XNOR or D[c] Discarded Left Shift 1 D[c] TC1057B Figure 2-14 Shift Plus Boolean Operation Address Arithmetic The TriCore architecture provides selected arithmetic operations on the address registers.
Page 38: Branch Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview A[a] A[b] A < B ? D[c] TC1058B Figure 2-15 LT.A Comparison Operation There are comparison instructions for equal (EQ.A), not equal (NE.A), less than (LT.A), and greater than or equal to (GE.A).
Page 39: Conditional Branch
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Both the 24-bit and 8-bit relative displacements are scaled by two before they are used, because all instructions must be aligned on an even address. The use of a 24-bit field as an absolute address is shown in Figure 2-16.
Page 40: Loop Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Conditional Jumps on Bits Conditional jumps can be performed based on the value of any bit in any data register. The JZ.T instruction jumps when the bit is clear, and the JNZ.T instruction jumps when the bit is set. For these instructions the jump displacement field is 15-bits.
Page 41: Load And Store Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview 2.10 Load and Store Instructions The load (LD.x) and store (ST.x) instructions move data between registers and memory using seven addressing modes (Table 2-3). The addressing mode determines the effective byte address for the load or store instruction and any update of the base pointer address register.
Page 42: Load Bit
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Memory Data Registers LD.D / LD.DA M1[63:32] M1[31:0] D[n+1] / A[n+1] D[n] / A[n] ST.D / ST.DA LD.W / LD.A D[n] / A[n] ST.W / ST.A LD.HU D[n] zero fill LD.H D[n]...
Page 43: Context Related Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview The Insert Mask (IMASK) instruction can be used in conjunction with the Load Modify Store (LDMST) instruction, to store a single bit or a bit field to a location in memory, using any of the addressing modes. This operation is especially useful for reading and writing memory-mapped peripherals.
Page 44: System Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview The LDUCX instruction (Load Upper Context) loads registers A[10] to A[15] and D[8] to D[15]. The PSW and link word fields in the saved context in memory are ignored. The PSW, FCX, and PCXI are unaffected. The STLCX instruction (Store Lower Context) stores the same context information that is saved with an explicit lower context save operation: Registers A[2] to A[7] and D[0] to D[7], together with the Return Address (RA) in A[11] and the PCXI.
Page 45: Enabling And Disabling The Interrupt System
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview 2.12.3 Access to the Core Special Function Registers (CSFRs) The core accesses the CSFRs through two instructions: • MFCR – The Move From Core Register instruction moves the contents of the addressed CSFR into a data register. MFCR can be executed in any mode (i.e.
Page 46: Return (Ret) And Return From Exception (Rfe Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview Programs executing in Supervisor mode can use the 16-bit BISR instruction (Begin Interrupt Service Routine) to save the lower context of the current task, set the current CPU priority number and re-enable interrupts (which are disabled by the processor when an interrupt is taken).
Page 47 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Overview The registers D[15] and A[15] are used as implicit registers in many 16-bit instructions. For example, there is a 16-bit compare instruction (EQ) that puts a Boolean result in D[15], and a 16-bit conditional move instruction (CMOV) which is controlled by the Boolean in D[15].
Page 48: Cpu Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Instruction Set The instruction mnemonics which follow are grouped into families of similar or related instructions, then listed in alphabetical order within those groups. For explanations of the syntax used, please refer to the previous chapter. CPU Instructions Each page for this group of instructions is laid out as follows: Key:...
Page 49 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Absolute Value Description Put the absolute value of data register D[b] in data register D[c]: If the contents of D[b] are greater than or equal to zero then copy it to D[c], otherwise change the sign of D[b] and copy it to D[c]. The operands are treated as signed 32-bit signed integers.
Page 50 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABS.B Absolute Value Packed Byte ABS.H Absolute Value Packed Half-word Description Put the absolute value of each byte (ABS.B) or half-word (ABS.H) in data register D[b] into the corresponding byte or half-word of data register D[c].
Page 51 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABS.B aov_byte3 = result_byte3[7] ^ result_byte3[6]; aov_byte2 = result_byte2[7] ^ result_byte2[6]; aov_byte1 = result_byte1[7] ^ result_byte1[6]; aov_byte0 = result_byte0[7] ^ result_byte0[6]; advanced_overflow = aov_byte3 OR aov_byte2 OR aov_byte1 OR aov_byte0; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;...
Page 52 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSDIF Absolute Value of Difference Description Put the absolute value of the difference between D[a] and either D[b] (instruction format RR) or const9 (instruction format RC) in D[c]; i.e. if the contents of data register D[a] are greater than either D[b] (format RR) or const9 (format RC), then subtract D[b] (format RR) or const9 (format RC) from D[a] and put the result in data register D[c];...
Page 53 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSDIF.B Absolute Value of Difference Packed Byte ABSDIF.H Absolute Value of Difference Packed Half-word Description Compute the absolute value of the difference between the corresponding bytes (ABSDIF.B) or half-words (ABSDIF.H) of D[a] and D[b], and put each result in the corresponding byte or half-word of D[c].
Page 54 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSDIF.B aov_byte3 = result_byte3[7] ^ result_byte3[6]; aov_byte2 = result_byte2[7] ^ result_byte2[6]; aov_byte1 = result_byte1[7] ^ result_byte1[6]; aov_byte0 = result_byte0[7] ^ result_byte0[6]; advanced_overflow = aov_byte3 OR aov_byte2 OR aov_byte1 OR aov_byte0; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;...
Page 55 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSDIFS Absolute Value of Difference with Saturation Description Put the absolute value of the difference between D[a] and either D[b] (instruction format RR) or const9 (instruction format RC) in D[c]; i.e. if the contents of data register D[a] are greater than either D[b] (format RR) or const9 (format RC), then subtract D[b] (format RR) or const9 (format RC) from D[a] and put the result in data register D[c];...
Page 56 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSDIFS.H Absolute Value of Difference Packed Half-word with Saturation Description Compute the absolute value of the difference of the corresponding half-words of D[a] and D[b] and put each result in the corresponding half-word of D[c].
Page 57 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSS Absolute Value with Saturation Description Put the absolute value of data register D[b] in data register D[c]; If the contents of D[b] are greater than or equal to zero, then copy it to D[c]; otherwise change the sign of D[b] and copy it to D[c]. The operands are treated as signed, 32-bit integers, with saturation on signed overflow.
Page 58 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ABSS.H Absolute Value Packed Half-word with Saturation Description Put the absolute value of each byte or half-word in data register D[b] in the corresponding byte or half-word of data register D[c].
Page 59 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Description Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The operands are treated as 32-bit integers, and the const9 value is sign-extended before the addition is performed.
Page 60 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set result = D[a] + sign_ext(const4); D[15] = result[31:0]; ADDD[a], D[b] (SRR) 12 11 42 H result = D[a] + D[b]; D[a] = result[31:0]; ADDD[a], D[15], D[b] (SRR) 12 11 12 H result = D[15] + D[b];...
Page 61 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also ADDC, ADDI, ADDIH, ADDS, ADDS.U, ADDX User Manual (Volume 2) 3-14 V1.0 2013-07...
Page 62 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADD.A Add Address Description Add the contents of address register A[a] to the contents of address register A[b] and put the result in address register A[c]. Add the contents of address register A[a] to the contents of either address register A[b] or const4 and put the result in address register A[a].
Page 63 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADD.B Add Packed Byte ADD.H Add Packed Half-word Description Add the contents of each byte (ADD.B) or half-word (ADD.H) of D[a] and D[b] and put the result in each corresponding byte or half-word of D[c].
Page 64 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADD.B aov_byte3 = result_byte3[7] ^ result_byte3[6]; aov_byte2 = result_byte2[7] ^ result_byte2[6]; aov_byte1 = result_byte1[7] ^ result_byte1[6]; aov_byte0 = result_byte0[7] ^ result_byte0[6]; advanced_overflow = aov_byte3 OR aov_byte2 OR aov_byte1 OR aov_byte0; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;...
Page 65 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDC Add with Carry Description Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) plus the carry bit, and put the result in data register D[c]. The operands are treated as 32- bit integers.
Page 66 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDI Add Immediate Description Add the contents of data register D[a] to the value const16, and put the result in data register D[c]. The operands are treated as 32-bit signed integers. The value const16 is sign-extended before the addition is performed. ADDID[c], D[a], const16 (RLC) 28 27 12 11...
Page 67 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDIH Add Immediate High Description Left-shift const16 by 16 bits, add the contents of data register D[a], and put the result in data register D[c]. The operands are treated as signed integers. ADDIHD[c], D[a], const16 (RLC) 28 27 12 11...
Page 68 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDIH.A Add Immediate High to Address Description Left-shift const16 by 16 bits, add the contents of address register A[a], and put the result in address register A[c]. ADDIH.AA[c], A[a], const16 (RLC) 28 27 12 11 const16...
Page 69 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDS Add Signed with Saturation Description Add the contents of data register D[a] to the value in either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The operands are treated as signed, 32-bit integers, with saturation on signed overflow.
Page 70 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set adds d3, d1 See Also ADD, ADDC, ADDI, ADDIH, ADDS.U, ADDX User Manual (Volume 2) 3-23 V1.0 2013-07...
Page 71 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDS.H Add Signed Packed Half-word with Saturation ADDS.HU Add Unsigned Packed Half-word with Saturation Description Add the contents of each half-word of D[a] and D[b] and put the result in each corresponding half-word of D[c], with saturation on signed overflow (ADDS.H) or saturation on unsigned overflow (ADDS.HU).
Page 72 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples adds.h d3, d1, d2 adds.hu d3, d1, d2 See Also ADD.B, ADD.H User Manual (Volume 2) 3-25 V1.0 2013-07...
Page 73 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDS.U Add Unsigned with Saturation Description Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The operands are treated as unsigned 32-bit integers, with saturation on unsigned overflow.
Page 74 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDSC.A Add Scaled Index to Address ADDSC.AT Add Bit-Scaled Index to Address Description For ADDSC.A, left-shift the contents of data register D[a] by the amount specified by n, where n can be 0, 1, 2, or 3.
Page 75 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set addsc.a a3, a4, d15, #2 See Also ADD.A, ADDIH.A, SUB.A User Manual (Volume 2) 3-28 V1.0 2013-07...
Page 76 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADDX Add Extended Description Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The operands are treated as 32-bit signed integers. The const9 value is sign-extended before the addition is performed.
Page 77 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Bitwise AND Description Compute the bitwise AND of the contents of data register D[a] and the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The const9 value is zero-extended.
Page 78 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples d3, d1, d2 d3, d1, #126 d1, d2 d15, #126 See Also ANDN, NAND, NOR, (16-bit), OR, ORN, XNOR, User Manual (Volume 2) 3-31 V1.0 2013-07...
Page 79 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.AND.T Accumulating Bit Logical AND-AND AND.ANDN.T Accumulating Bit Logical AND-AND-Not AND.NOR.T Accumulating Bit Logical AND-NOR AND.OR.T Accumulating Bit Logical AND-OR Description Compute the logical AND, ANDN, NOR or OR of the value in bit pos1 of data register D[a] and bit pos2 of D[b]. Then compute the logical AND of that result and bit 0 of D[c], and put the result in bit 0 of D[c].
Page 80 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Not set by these instructions. Examples and.and.t d3, d1, 4, d2, #9 and.andn.t d3, d1, 6, d2, #15 and.nor.t d3, d1, 5, d2, #9 and.or.t d3, d1, 4, d2, #6 See Also OR.AND.T, OR.ANDN.T, OR.NOR.T, OR.OR.T, SH.AND.T, SH.ANDN.T, SH.NAND.T, SH.NOR.T, SH.OR.T, SH.ORN.T, SH.XNOR.T,...
Page 81 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.EQ Equal Accumulating Description Compute the logical AND of D[c][0] and the boolean result of the equality comparison operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction RC). Put the result in D[c][0].
Page 82 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.GE Greater Than or Equal Accumulating AND.GE.U Greater Than or Equal Accumulating Unsigned Description Calculate the logical AND of D[c][0] and the boolean result of the GE or GE.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 83 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set and.ge d3, d1, #126 and.ge.u d3, d1, d2 and.ge.u d3, d1, #126 See Also OR.GE, OR.GE.U, XOR.GE, XOR.GE.U User Manual (Volume 2) 3-36 V1.0 2013-07...
Page 84 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.LT Less Than Accumulating AND.LT.U Less Than Accumulating Unsigned Description Calculate the logical AND of D[c][0] and the boolean result of the LT or LT.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 85 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set and.lt d3, d1, #126 and.lt.u d3, d1, d2 and.lt.u d3, d1, #126 See Also OR.LT, OR.LT.U, XOR.LT, XOR.LT.U User Manual (Volume 2) 3-38 V1.0 2013-07...
Page 86 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.NE Not Equal Accumulating Description Calculate the logical AND of D[c][0] and the boolean result of the NE operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in D[c][0]. All other bits in D[c] are unchanged.
Page 87 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set AND.T Bit Logical AND Description Compute the logical AND of bit pos1 of data register D[a] and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. AND.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 88 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ANDN Bitwise AND-Not Description Compute the bitwise AND of the contents of data register D[a] and the ones complement of the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is zero-extended to 32-bits.
Page 89 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ANDN.T Bit Logical AND-Not Description Compute the logical AND of bit pos1 of data register D[a] and the inverse of bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. ANDN.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 90 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set BISR Begin Interrupt Service Routine Description Note: BISR can only be executed in Supervisor mode. Save the lower context by storing the contents of A[2]-A[7], D[0]-D[7], and the current A[11] (return address) to the current memory location pointed to by the FCX.
Page 91 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (FCX == 0) trap(FCU); EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; new_FCX = M(EA, word); M(EA,16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; PCXI.PCPN = ICR.CCPN;...
Page 92 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set BMERGE Bit Merge Description Take the lower 16-bits of data register D[a] and move them to the odd bit positions of data register D[c]. The lower 16-bits of data register D[b] are moved to the even bit positions of data register D[c]. The upper 16-bits of D[a] and D[b] are not used.
Page 93 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set BSPLIT Bit Split Description Split data register D[a] into a data register pair E[c] such that all the even bits of D[a] are in the even register and all the odd bits of D[a] are in the odd register. BSPLITE[c], D[a] (RR) 28 27 20 19...
Page 94 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEA.I Cache Address, Invalidate Description Note: This instruction can only be executed in Supervisor mode. If the cache line containing the byte memory location specified by the addressing mode is present in the L1 data cache, invalidate the line.
Page 95 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 22 21 16 15 12 11 off10[9:6] 0E H off10[5:0] 89 H EA = A[b]; cache_address_ivld(EA); A[b] = EA + sign_ext(off10); CACHEA.IA[b], off10 (BO) (Pre-increment Addressing Mode) 28 27 22 21 16 15...
Page 96 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEA.W Cache Address, Writeback Description If the cache line containing the byte memory location specified by the addressing mode is present in the L1 data cache, write back any modified data. The line will still be present in the L1 data cache and will be marked as unmodified.
Page 97 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 22 21 16 15 12 11 off10[9:6] 0C H off10[5:0] 89 H EA = A[b]; cache_address_wb(EA); A[b] = EA + sign_ext(off10); CACHEA.WA[b], off10 (BO) (Pre-increment Addressing Mode) 28 27 22 21 16 15...
Page 98 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEA.WI Cache Address, Writeback and Invalidate Description If the cache line containing the byte memory location specified by the addressing mode is present in the L1 data cache, write back any modified data and then invalidate the line in the L1 data cache. If the cache line containing the byte memory location specified by the addressing mode is not present in the L1 data cache then no operation should be performed in the L1 data cache.
Page 99 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 22 21 16 15 12 11 off10[9:6] 0D H off10[5:0] 89 H EA = A[b]; cache_address_wi(EA); A[b] = EA + sign_ext(off10); CACHEA.WIA[b], off10 (BO)(Pre-increment Addressing Mode) 28 27 22 21 16 15 12 11...
Page 100 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEI.W Cache Index, Writeback Description If any modified cache line at the memory index/way specified by address register A[b] is present in the L1 data cache, writeback the modified data. The line will still be present within the L1 data cache but will be marked as unmodified.
Page 101 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set cachei.w [a3+]4 See Also CACHEA.I, CACHEA.W, CACHEA.WI, CACHEI.I, CACHEI.WI User Manual (Volume 2) 3-54 V1.0 2013-07...
Page 102 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEI.I Cache Index, Invalidate Description This instruction can only be executed in Supervisor mode. If the cache line at the index/way specified by the address register A[b] is present in the L1 data cache, then invalidate the line.
Page 103 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also CACHEA.I, CACHEA.W, CACHEA.WI, CACHEI.W, CACHEI.WI User Manual (Volume 2) 3-56 V1.0 2013-07...
Page 104 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CACHEI.WI Cache Index, Writeback, Invalidate Description If the cache line at the memory index/way specified by the address register A[b] is present in the L1 data cache, write back the modified data and then invalidate the line in the L1 data cache. The address specified by the address register A[b] undergoes standard protection checks.
Page 105 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also CACHEA.I, CACHEA.W, CACHEA.WI, CACHEI.I, CACHEI.W User Manual (Volume 2) 3-58 V1.0 2013-07...
Page 106 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CADD Conditional Add Description If the contents of data register D[d] are non-zero, then add the contents of data register D[a] and the contents of either register D[b] (instruction format RRR) or const9 (instruction format RCR) and put the result in data register D[c];...
Page 107 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples cadd d3, d4, d1, d2 cadd d3, d4, d1, #126 cadd d1, d15, 6 See Also CADDN, CMOV (16-bit), CMOVN (16-bit), CSUB, CSUBN, SEL, SELN User Manual (Volume 2) 3-60 V1.0 2013-07...
Page 108 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CADDN Conditional Add-Not Description If the contents of data register D[d] are zero, then add the contents of data register D[a] and the contents of either register D[b] (instruction format RRR) or const9 (instruction format RCR) and put the result in data register D[c]; otherwise put the contents of D[a] in D[c].
Page 109 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples caddn d3, d4, d1, d2 caddn d3, d4, d1, #126 caddn d1, d15, #6 See Also CADD, CMOV (16-bit), CMOVN (16-bit), CSUB, CSUBN, SEL, SELN User Manual (Volume 2) 3-62 V1.0 2013-07...
Page 110 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CALL Call Description Add the value specified by disp24, multiplied by two and sign-extended, to the address of the CALL instruction and jump to the resulting address. The target address range is ±16 MBytes relative to the current PC. In parallel with the jump, save the caller’s Upper Context to an available Context Save Area (CSA).
Page 111 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (FCX == 0) trap(FCU); if (PSW.CDE) then if(cdc_increment()) then trap(CDO); PSW.CDE = 1; ret_addr = PC + 2 ; tmp_FCX = FCX; EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; new_FCX = M(EA, word);...
Page 112 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CALLA Call Absolute Description Jump to the address specified by disp24. In parallel with the jump, save the caller’s Upper Context to an available Context Save Area (CSA). Set register A[11] (return address) to the address of the next instruction beyond the call. Note: After CALLA, upper context registers are undefined except for A[10] and A[11].
Page 113 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CALLI Call Indirect Description Jump to the address specified by the contents of address register A[a]. In parallel with the jump save the caller’s Upper Context to an available Context Save Area (CSA). Set register A[11] (return address) to the address of the next instruction beyond the call.
Page 114 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also CALL, CALLA, RET, FCALLI, FRET User Manual (Volume 2) 3-67 V1.0 2013-07...
Page 115 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Count Leading Ones Description Count the number of consecutive ones in D[a], starting with bit 31, and put the result in D[c]. CLOD[c], D[a] (RR) 28 27 20 19 18 17 16 15 12 11...
Page 116 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CLO.H Count Leading Ones in Packed Half-words Description Count the number of consecutive ones in each half-word of D[a], starting with the most significant bit, and put each result in the corresponding half-word of D[c]. CLO.HD[c], D[a] (RR) 28 27 20 19...
Page 117 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Count Leading Signs Description Count the number of consecutive bits which have the same value as bit 31 in D[a], starting with bit 30, and put the result in D[c]. The result is the number of leading sign bits minus one, giving the number of redundant sign bits in D[a].
Page 118 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CLS.H Count Leading Signs in Packed Half-words Description Count the number of consecutive bits in each half-word in data register D[a] which have the same value as the most-significant bit in that half-word, starting with the next bit right of the most-significant bit. Put each result in the corresponding half-word of D[c].
Page 119 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Count Leading Zeros Description Count the number of consecutive zeros in D[a] starting with bit 31, and put result in D[c]. CLZD[c], D[a] (RR) 28 27 20 19 18 17 16 15 12 11 1B H...
Page 120 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CLZ.H Count Leading Zeros in Packed Half-words Description Count the number of consecutive zeros in each half-word of D[a], starting with the most significant bit of each half- word, and put each result in the corresponding half-word of D[c]. CLZ.HD[c], D[a] (RR) 28 27 20 19...
Page 121 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CMOV (16-bit) Conditional Move (16-bit) Description If the contents of data register D[15] are not zero, copy the contents of either data register D[b] (instruction format SRR) or const4 (instruction format SRC) to data register D[a]; otherwise the contents of D[a] is unchanged. The const4 value is sign-extended.
Page 122 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CMOVN (16-bit) Conditional Move-Not (16-bit) Description If the contents of data register D[15] are zero, copy the contents of either data register D[b] (instruction format SRR) or const4 (instruction format SRC) to data register D[a]; otherwise the contents of D[a] is unchanged. The const4 value is sign-extended to 32-bits.
Page 123 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CMPSWAP.W Compare and Swap Description The CMPSWAP.W instruction conditionally swaps the data register D[a] and the contents of the memory word specified by the addressing mode. If the contents of the memory word specified by the addressing mode is equal to the contents of register D[a+1] then swap the contents of the memory word with the register D[a].
Page 124 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; CMPSWAP.WA[b], off10, E[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 03 H off10[5:0] 49 H EA = A[b]; tmp = M(EA, word); M(EA, word) = (tmp == D[a+1]) ? D[a] : tmp;...
Page 125 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CRC32 CRC32 Description Calculate the CRC of register D[a] and the inverse of register D[b] and put the result in register D[c]. The CRC polynomial used is the CRC-32 polynomial as defined in the IEEE 802.3 standard. The initial value of D[b] should be zero CRC32D[c], D[b], D[a] (RR) 28 27...
Page 126 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CSUB Conditional Subtract Description If the contents of data register D[d] are not zero, subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register D[c]; otherwise put the contents of D[a] in D[c]. CSUBD[c], D[d], D[a], D[b] (RRR) 28 27 24 23...
Page 127 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CSUBN Conditional Subtract-Not Description If the contents of data register D[d] are zero, subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register D[c]; otherwise put the contents of D[a] in D[c]. CSUBND[c], D[d], D[a], D[b] (RRR) 28 27 24 23...
Page 128 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DEBUG Debug Description If the Debug mode is enabled (DBGSR.DE == 1), cause a Debug Event; otherwise execute a NOP. If the Debug mode is enabled (DBGSR.DE == 1), cause a Debug event; otherwise execute a NOP. DEBUG(SR) 12 11 0A H...
Page 129 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DEXTR Extract from Double Register Description Extract 32-bits from registers {D[a], D[b]}, where D[a] contains the most-significant 32-bits of the value, starting at the bit number specified by either 32 - D[d][4:0] (instruction format RRRR) or 32 - pos (instruction format RRPW). Put the result in D[c].
Page 130 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DISABLE Disable Interrupts Description Note: DISABLE can only be executed in User-1 mode or Supervisor mode. Disable interrupts by clearing Interrupt Enable bit (ICR.IE) in the Interrupt Control Register. Optionaly update D[a] with the ICR.IE value prior to clearing.
Page 131 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DSYNC Synchronize Data Description Forces all data accesses to complete before any data accesses associated with an instruction, semantically after the DSYNC is initiated. Note: The Data Cache (DCACHE) is not invalidated by DSYNC. Note: To ensure memory coherency, a DSYNC instruction must be executed prior to any access to an active CSA memory location.
Page 132 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DVADJ Divide-Adjust Description Divide-adjust the contents of the formatted data register E[d] using the divisor in D[b] and store the result in E[c]. E[d][63:32] contains the sign-extended final remainder from a previous DVSTEP instruction and E[d][31:0] contains the sign-extended final quotient in ones complement format.
Page 133 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Examples See Also User Manual (Volume 2) 3-86 V1.0 2013-07...
Page 134 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Divide DIV.U Divide Unsigned Description Divide the contents of register D[a] by the contents of register D[b]. Put the resulting quotient in E[c][31:0] and the remainder in E[c][63:32]. The operands and results are treated as signed 32-bit integers for the DIV instruction and as unsigned 32-bit integers for the DIV.U instruction.
Page 135 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (divisor == 0) then { quotient = 0xffffffff; remainder = 0x00000000; } else { remainder = dividend % divisor quotient = (dividend - remainder)/divisor E[c][31:0] = quotient; E[c][63:32] = remainder; Status Flags Not set by these instructions.
Page 136 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DVINIT Divide-Initialization Word DVINIT.U Divide-Initialization Word Unsigned DVINIT.B Divide-Initialization Byte DVINIT.BU Divide-Initialization Byte Unsigned DVINIT.H Divide-Initialization Half-word DVINIT.HU Divide-Initialization Half-word Unsigned Description The DVINIT group of instructions prepare the operands for a subsequent DVSTEP instruction (see DVSTEP) from the dividend D[a] and divisor D[b], and also check for conditions that will cause overflow of the final quotient result.
Page 137 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set quotient_sign = !(D[a][31] == D[b][31]); E[c][63:24] = sign_ext(D[a]); E[c][23:0] = quotient_sign ? 24’b111111111111111111111111 : 24’b0; DVINIT.BUE[c], D[a], D[b] (RR) 28 27 20 19 18 17 16 15 12 11 4A H 4B H E[c][63:24] = zero_ext(D[a]);...
Page 138 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DVINIT if ((D[b] == 0) OR ((D[b] == 32’hFFFFFFFF) AND (D[a] == 32’h80000000))) then overflow = 1 else overflow = 0; DVINIT.U if (D[b] == 0) then overflow = 1 else overflow = 0; DVINIT.B if ((D[b] == 0) OR ((D[b] == 32’hFFFFFFFF AND (D[a] == 32’hFFFFFF80)) then overflow = 1 else overflow = 0;...
Page 139 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DVSTEP Divide-Step DVSTEP.U Divide-Step Unsigned Description The DVSTEP(.U) instruction divides the contents of the formatted data register E[d] by the divisor in D[b], producing 8-bits of quotient at a time. E[d] contains a partially calculated remainder and partially calculated quotient (in ones complement format) in bit fields that depend on the number of DVSTEP instructions required to produce a final result (see DVSTEP).
Page 140 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 20 19 18 17 16 15 12 11 0E H 6B H divisor = D[b]; dividend_quotient = E[d][31:0]; remainder = E[d][63:32]; for i = 0 to 7 { remainder = (remainder <<...
Page 141 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ENABLE Enable Interrupts Description Note: ENABLE can only be executed in User-1 or Supervisor mode. Enable interrupts by setting the Interrupt Enable bit (ICR.IE) in the Interrupt Control Register (ICR) to one. ENABLE(SYS) 28 27 22 21...
Page 142 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Equal Description If the contents of data register D[a] are equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c].
Page 143 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Not set by this instruction. Not set by this instruction. Examples d3, d1, d2 d3, d1, #126 d15, d1, d2 d15, d1, #6 See Also GE, GE.U, LT, LT.U, NE, EQANY.B, EQANY.H User Manual (Volume 2) 3-96...
Page 144 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set EQ.A Equal to Address Description If the contents of address registers A[a] and A[b] are equal, set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c]. EQ.AD[c], A[a], A[b] (RR) 28 27 20 19...
Page 145 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set EQ.B Equal Packed Byte EQ.H Equal Packed Half-word EQ.W Equal Packed Word Description Compare each byte (EQ.B), half-word (EQ.H) or word (EQ.W) of D[a] with the corresponding byte, half-word or word of D[b].
Page 146 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples eq.b d3, d1, d2 eq.h d3, d1, d2 eq.w d3, d1, See Also LT.B, LT.BU, LT.H, LT.HU, LT.W, LT.WU User Manual (Volume 2) 3-99 V1.0 2013-07...
Page 147 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set EQANY.B Equal Any Byte EQANY.H Equal Any Half-word Description Compare each byte (EQANY.B) or half-word (EQANY.H) of D[a] with the corresponding byte or half-word of either D[b] (instruction format RR) or const9 (instruction format RC). If the logical OR of the Boolean results from each comparison is TRUE, set the least-significant bit of D[c] to 1 and clear the remaining bits to zero;...
Page 148 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 20 19 18 17 16 15 12 11 76 H 0B H result_halfword1 = (D[a][31:16] == D[b][31:16]); result_halfword0 = (D[a][15:0] == D[b][15:0]); result = result_halfword1 OR result_halfword1; D[c] = zero_ext(result);...
Page 149 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set EQZ.A Equal Zero Address Description If the contents of address register A[a] are equal to zero, set the least significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c]. EQZ.AD[c], A[a] (RR) 28 27 20 19...
Page 150 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set EXTR Extract Bit Field EXTR.U Extract Bit Field Unsigned Description Extract the number of consecutive bits specified by either E[d][36:32] (instruction format RRRR) or width (instruction formats RRRW and RRPW) from D[a], starting at the bit number specified by either E[d][4:0] (instruction format RRRR), D[d][4:0] (instruction format RRRW) or pos (instruction format RRPW).
Page 151 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set D[c] = zero_ext((D[a] >> E[d][4:0])[width-1:0]); If E[d][4:0] + width > 32 or if width = 0, then the results are undefined. EXTR.UD[c], D[a], D[d], width (RRRW) 28 27 24 23 21 20 16 15 12 11...
Page 152 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FCALL Fast Call Description Add the value specified by disp24, multiplied by two and sign-extended to 32-bits, to the address of the FCALL instruction and jump to the resulting address. The target address range is ±16 MBytes relative to the current PC. Store A[11] to the memory address specified by A[10] pre-decremented by 4.
Page 153 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FCALLA Fast Call Absolute Description Jump to the address specified by disp24. Store A[11] to the memory address specified by A[10] pre-decremented by 4. Store the address of the next instruction in A[11]. FCALLAdisp24 (B) 16 15 disp24[15:0]...
Page 154 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FCALLI Fast Call Indirect Description Jump to the address specified by the contents of address register A[a]. Store A[11] to the memory address specified by A[10] pre-decremented by 4. Store the address of the next instruction in A[11]. FCALLIA[a] (RR) 28 27 20 19...
Page 155 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FRET Return from Fast Call Description Return from a function that was invoked with an FCALL instruction. Jump to the address specified by A[11]. Load A[11] from the address specified by A[10] then increment A[10] by 4. Return from a function that was invoked with an FCALL instruction.
Page 156 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Greater Than or Equal GE.U Greater Than or Equal Unsigned Description If the contents of data register D[a] are greater than or equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one and clear the remaining bits to zero;...
Page 157 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Not set by these instructions. Examples d3, d1, d2 d3, d1, #126 ge.u d3, d1, d2 ge.u d3, d1, #126 See Also EQ, LT, LT.U, NE, EQANY.B, EQANY.H User Manual (Volume 2) 3-110 V1.0 2013-07...
Page 158 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set GE.A Greater Than or Equal Address Description If the contents of address register A[a] are greater than or equal to the contents of address register A[b], set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c]. Operands are treated as unsigned 32-bit integers.
Page 159 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set IMASK Insert Mask Description Create a mask containing the number of bits specified by width, starting at the bit number specified by either D[d][4:0] (instruction formats RRRW and RCRW) or pos (instruction formats RRPW and RCPW), and put the mask in data register E[c][63:32].
Page 160 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Examples imask e2, d1, d2, #11 imask e2, d1, #5, #11...
Page 161 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set INS.T Insert Bit INSN.T Insert Bit-Not Description Move the value of D[a] to D[c] with either: • For INS.T, bit pos1 of this value replaced with bit pos2 of register D[b]. •...
Page 162 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set INSERT Insert Bit Field Description Starting at bit zero, extract from either D[b] (instruction formats RRRR, RRRW, RRPW) or const4 (instruction formats RCRR, RCRW, RCPW) the number of consecutive bits specified by either E[d][36:32] (formats RRRR, RCRR) or width (formats RRRW, RRPW, RCRW, RCPW).
Page 163 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set INSERTD[c], D[a], D[b], E[d] (RRRR) 28 27 24 23 21 20 16 15 12 11 00 H 17 H width = E[d][36:32]; width mask = (2 -1) << E[d][4:0]; D[c] = (D[a] &...
Page 164 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ISYNC Synchronize Instructions Description The ISYNC instruction forces completion of all previous instructions, then flushes the CPU pipelines and invalidates any cached pipeline state before proceeding to the next instruction. Note: I-cache is not invalidated by ISYNC.
Page 165 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set IXMAX Find Maximum Index IXMAX.U Find Maximum Index (unsigned) Description Enables a search of maximum value and its related index in a vector of 16-bit signed (IXMAX) or unsigned (IXMAX.U) values.
Page 166 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (D[b][15:0] >= D[b][31:16]) AND (D[b][15:0] > E[d][47:32]) then { E[c][47:32] = D[b][15:0]; E[c][31:16] = E[d][15:0]; } else if (D[b][31:16] > D[b][15:0]) AND (D[b][31:16] > E[d][47:32]) then { E[c][47:32] = D[b][31:16]; E[c][31:16] = E[d][15:0]+1;...
Page 167 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set IXMIN Find Minimum Index IXMIN.U Find Minimum Index (unsigned) Description Enables search of minimum value and its related index in a vector of 16-bit signed (IXMIN) or unsigned (IXMIN.U) values.
Page 168 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (D[b][15:0] <= D[b][31:16]) AND (D[b][15:0] < E[d][47:32]) then { E[c][47:32] = D[b][15:0]; E[c][31:16] = E[d][15:0]; } else if (D[b][31:16] < D[b][15:0]) AND (D[b][31:16] < E[d][47:32]) then { E[c][47:32] = D[b][31:16]; E[c][31:16] = E[d][15:0]+1;...
Page 169 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump Unconditional Description Add the value specified by disp24, sign-extended and multiplied by 2, to the contents of PC and jump to that address. Add the value specified by disp8, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 170 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump Unconditional Absolute Description Load the value specified by disp24 into PC and jump to that address. The value disp24 is used to form the Effective Address (EA). JAdisp24 (B) 16 15 disp24[15:0] disp24[23:16]...
Page 171 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump if Equal Description If the contents of D[a] are equal to the contents of either D[b] or const4, then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address. The const4 value is sign- extended.
Page 172 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 12 11 disp4 BE H if (D[15] == D[b]) then PC = PC + zero_ext(disp4 + 16) * 2; Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction.
Page 173 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JEQ.A Jump if Equal Address Description If the contents of A[a] are equal to the contents of A[b], then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address. JEQ.AA[a], A[b], disp15 (BRR) 31 30 16 15...
Page 174 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump if Greater Than or Equal JGE.U Jump if Greater Than or Equal Unsigned Description If the contents of D[a] are greater than or equal to the contents of either D[b] (instruction format BRR) or const4 (instruction format BRC), then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 175 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples d1, d2, foobar d1, #6, foobar jge.u d1, d2, foobar jge.u d1, #6, foobar See Also JEQ, JLT, JLT.U, User Manual (Volume 2) 3-128 V1.0 2013-07...
Page 176 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JGEZ (16-bit) Jump if Greater Than or Equal to Zero (16-bit) Description If the contents of D[b] are greater than or equal to zero, then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 177 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JGTZ (16-bit) Jump if Greater Than Zero (16-bit) Description If the contents of D[b] are greater than zero, then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address. JGTZD[b], disp4 (SBR) 12 11 disp4...
Page 178 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump Indirect Description Load the contents of address register A[a] into PC and jump to that address. The least-significant bit is always set to 0. Load the contents of address register A[a] into PC and jump to that address. The least-significant bit is always set to 0.
Page 179 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump and Link Description Store the address of the next instruction in A[11] (return address). Add the value specified by disp24, sign- extended and multiplied by 2, to the contents of PC and jump to that address. JLdisp24 (B) 16 15 disp24[15:0]...
Page 180 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump and Link Absolute Description Store the address of the next instruction in A[11] (return address). Load the value specified by disp24 into PC and jump to that address. The value disp24 is used to form the effective address (EA). JLAdisp24 (B) 16 15 disp24[15:0]...
Page 181 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JLEZ (16-bit) Jump if Less Than or Equal to Zero (16-bit) Description If the contents of D[b] are less than or equal to zero, then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 182 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump and Link Indirect Description Store the address of the next instruction in A[11] (return address). Load the contents of address register A[a] into PC and jump to that address. The least-significant bit is set to zero. JLIA[a] (RR) 28 27 20 19...
Page 183 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump if Less Than JLT.U Jump if Less Than Unsigned Description If the contents of D[a] are less than the contents of either D[b] (instruction format BRR) or const4 (instruction format BRC), then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 184 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples d1, d2, foobar d1, #6, foobar jlt.u d1, d2, foobar jlt.u d1, #6, foobar See Also JEQ, JGE, JGE.U, User Manual (Volume 2) 3-137 V1.0 2013-07...
Page 185 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JLTZ (16-bit) Jump if Less Than Zero (16-bit) Description If the contents of D[b] are less than zero then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 186 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Jump if Not Equal Description If the contents of D[a] are not equal to the contents of either D[b] (instruction format BRR) or const4 (instruction format BRC), then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 187 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 12 11 disp4 FE H if (D[15] != D[b]) then PC = PC + zero_ext(disp4 + 16) * 2; Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction.
Page 188 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNE.A Jump if Not Equal Address Description If the contents of A[a] are not equal to the contents of A[b] then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address. JNE.AA[a], A[b], disp15 (BRR) 31 30 16 15...
Page 189 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNED Jump if Not Equal and Decrement Description If the contents of D[a] are not equal to the contents of either D[b] (instruction format BRR) or const4 (instruction format BRC), then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 190 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNEI Jump if Not Equal and Increment Description If the contents of D[a] are not equal to the contents of either D[b] (instruction format BRR) or const4 (instruction format BRC), then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 191 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNZ (16-bit) Jump if Not Equal to Zero (16-bit) Description If contents of either D[b] (instruction format SBR) or D[15] (instruction format SB) are not equal to zero, then add value specified by either disp4 (format SBR) or disp8 (format SB), zero-extended (disp4) or sign-extended (disp8) and multiplied by 2, to the contents of PC and jump to that address.
Page 192 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNZ.A Jump if Not Equal to Zero Address Description If the contents of A[a] are not equal to zero, then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 193 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JNZ.T Jump if Not Equal to Zero Bit Description If bit n of register D[a] is not equal to zero, then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 194 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JZ (16-bit) Jump if Zero (16-bit) Description If the contents of either D[15] (instruction format SB) or D[b] (instruction format SBR) are equal to zero, then add the value specified by either disp8 (format SB) or disp4 (format SBR), sign-extended (disp8) or zero-extended (disp4) and multiplied by 2, to the contents of PC, and jump to that address.
Page 195 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JZ.A Jump if Zero Address Description If the contents of A[a] are equal to zero then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address. If the contents of A[b] are equal to zero then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 196 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set JZ.T Jump if Zero Bit Description If bit n of register D[a] is equal to zero then add the value specified by disp15, sign-extended and multiplied by 2, to the contents of PC and jump to that address. If bit n of register D[15] is equal to zero then add the value specified by disp4, zero-extended and multiplied by 2, to the contents of PC and jump to that address.
Page 197 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.A Load Word to Address Register Description Load the word contents of the memory location specified by the addressing mode into address register A[a]. Note: If the target register is modified by the addressing mode, the result is undefined. Load the word contents of the memory location specified by the addressing mode into either address register A[a] or A[15].
Page 198 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = new_index < 0 ? new_index+length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; LD.AA[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 06 H off10[5:0]...
Page 199 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[c] = M(A[b], word); A[b] = A[b] + 4; LD.AA[c], A[15], off4 (SLRO) 12 11 off4 C8 H A[c] = M(A[15] + zero_ext(4 * off4), word); LD.AA[15], A[b], off4 (SRO) 12 11 off4 CC H...
Page 200 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.B Load Byte LD.BU Load Byte Unsigned Description Load the byte contents of the memory location specified by the addressing mode, sign-extended or zero-extended, into data register D[a]. Load the byte contents of the memory location specified by the addressing mode, zero-extended, into either data register D[a] or D[15].
Page 201 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = index + sign_ext(off10); new_index = new_index < 0 ? new_index+length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; LD.BD[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6]...
Page 202 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set index = zero_ext(A[b+1][15:0]); incr = zero_ext(A[b+1][31:16]); EA = A[b] + index; D[a] = zero_ext(M(EA, byte)); new_index = reverse16(reverse16(index) + reverse16(incr)); A[b+1] = {incr[15:0], new_index[15:0]}; LD.BUD[a], P[b], off10 (BO)(Circular Addressing Mode) 28 27 22 21 16 15...
Page 203 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 12 11 14 H D[c] = zero_ext(M(A[b], byte)); LD.BUD[c], A[b] (SLR)(Post-increment Addressing Mode) 12 11 04 H D[c] = zero_ext(M(A[b], byte)); A[b] = A[b] + 1; LD.BUD[c], A[15], off4 (SLRO) 12 11 off4 08 H...
Page 204 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.D Load Double-word Description Load the double-word contents of the memory location specified by the addressing mode into the extended data register E[a]. The least-significant word of the double-word value is loaded into the even register (D[n]) and the most-significant word is loaded into the odd register (D[n+1]).
Page 205 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = new_index < 0 ? new_index+length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; LD.DE[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 05 H off10[5:0]...
Page 206 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.DA Load Double-word to Address Register Description Load the double-word contents of the memory location specified by the addressing mode into an address register pair A[a]. The least-significant word of the double-word value is loaded into the even register (A[a]) and the most- significant word is loaded into the odd register (A[a+1]).
Page 207 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; LD.DA P[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 07 H off10[5:0] 09 H EA = A[b]; P[a] = M(EA, doubleword); A[b] = EA + sign_ext(off10);...
Page 208 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.H Load Half-word LD.HU Load Half-word Unsigned Description Load the half-word contents of the memory location specified by the addressing mode, sign-extended, into data register D[a]. Load the half-word contents of the memory location specified by the addressing mode, sign-extended, into either data register D[a] or D[15].
Page 209 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = index + sign_ext(off10); new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; LD.HD[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11...
Page 210 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set D[c] = sign_ext(M(A[15] + zero_ext(2 * off4), half-word)); LD.HD[15], A[b], off4 (SRO) 12 11 off4 8C H D[15] = sign_ext(M(A[b] + zero_ext(2 * off4), half-word)); LD.HUD[a], off18 (ABS)(Absolute Addressing Mode) 28 27 26 25 22 21...
Page 211 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; LD.HUD[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 03 H off10[5:0] 09 H EA = A[b]; D[a] = zero_ext(M(EA, halfword)); A[b] = EA + sign_ext(off10);...
Page 212 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.Q Load Half-word Signed Fraction Description Load the half-word contents of the memory location specified by the addressing mode into the most-significant half-word of data register D[a], setting the 16 least-significant bits of D[a] to zero. LD.QD[a], off18 (ABS)(Absolute Addressing Mode) 28 27 26 25...
Page 213 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 22 21 16 15 12 11 off10[9:6] 08 H off10[5:0] 09 H EA = A[b]; D[a] = {M(EA, halfword), 16’h0000}; A[b] = EA + sign_ext(off10); LD.QD[a], A[b], off10 (BO)(Pre-increment Addressing Mode) 28 27 22 21 16 15...
Page 214 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.W Load Word Description Load word contents of the memory location specified by the addressing mode into data register D[a]. Load word contents of the memory location specified by the addressing mode into data register either D[a] or D[15].
Page 215 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; LD.WD[a], A[b], off10 (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 04 H off10[5:0] 09 H EA = A[b]; D[a] = M(EA, word); A[b] = EA + sign_ext(off10);...
Page 216 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LD.WD[c], A[15], off4 (SLRO) 12 11 off4 48 H D[c] = M(A[15] + zero_ext(4 * off4), word); LD.WD[15], A[b], off4 (SRO) 12 11 off4 4C H D[15] = M(A[b] + zero_ext(4 * off4), word); Status Flags Not set by this instruction.
Page 217 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LDLCX Load Lower Context Description Load the contents of the memory block specified by the addressing mode into registers A[2]-A[7] and D[0]-D[7]. This operation is normally used to restore GPR values that were saved previously by an STLCX instruction. Note: The effective address specified by the addressing mode must be aligned on a 16-word boundary.
Page 218 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LDMST Load-Modify-Store Description The atomic Load-Modify-Store implements a store under a mask of a value to the memory word, whose address is specified by the addressing mode. Only those bits of the value E[a][31:0] where the corresponding bits in the mask E[a][63:32] are set, are stored into memory.
Page 219 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LDMSTA[b], off10, E[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 01 H off10[5:0] 49 H EA = A[b]; M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); A[b] = EA + sign_ext(off10);...
Page 220 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LDUCX Load Upper Context Description Load the contents of the memory block specified by the addressing mode into registers A[10] to A[15] and D[8] to D[15]. This operation is used normally to restore GPR values that were saved previously by a instruction.
Page 221 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Load Effective Address Description Compute the absolute (effective) address defined by the addressing mode and put the result in address register A[a]. Note: The auto-increment addressing modes are not supported for this instruction. LEAA[a], off18 (ABS)(Absolute Addressing Mode) 28 27 26 25...
Page 222 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LOOP Loop Description If address register A[b] is not equal to zero, then add the value specified by disp15, multiplied by two and sign- extended, to the contents of PC and jump to that address. The address register is decremented unconditionally. If address register A[b] is not equal to zero then add value specified by disp4, multiplied by two and one-extended to a 32-bit negative number, to the contents of PC and jump to that address.
Page 223 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LOOPU Loop Unconditional Description Add the value specified by disp15, multiplied by two and sign-extended, to the contents of PC and jump to that address. LOOPUdisp15 (BRR) 31 30 16 15 12 11 disp15...
Page 224 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Less Than LT.U Less Than Unsigned Description If the contents of data register D[a] are less than the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), then set the least-significant bit of D[c] to one and clear the remaining bits to zero;...
Page 225 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LT.UD[c], D[a], const9 (RC) 28 27 21 20 12 11 13 H const9 8B H result = (D[a] < zero_ext(const9)); // unsigned D[c] = zero_ext(result); LT.UD[c], D[a], D[b] (RR) 28 27 20 19 18 17...
Page 226 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LT.A Less Than Address Description If the contents of address register A[a] are less than the contents of address register A[b], set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c]. The operands are treated as unsigned 32-bit integers.
Page 227 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LT.B Less Than Packed Byte LT.BU Less Than Packed Byte Unsigned Description Compare each byte of data register D[a] with the corresponding byte of D[b]. In each case, if the value of the byte in D[a] is less than the value of the byte in D[b], set all bits in the corresponding byte of D[c] to one;...
Page 228 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LT.H Less Than Packed Half-word LT.HU Less Than Packed Half-word Unsigned Description Compare each half-word of data register D[a] with the corresponding half-word of D[b]. In each case, if the value of the half-word in D[a] is less than the value of the corresponding half-word in D[b], set all bits of the corresponding half-word of D[c] to one;...
Page 229 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LT.W Less Than Packed Word LT.WU Less Than Packed Word Unsigned Description If the contents of data register D[a] are less than the contents of data register D[b], set all bits in D[c] to one; otherwise clear all bits in D[c].
Page 230 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD Multiply-Add MADDS Multiply-Add, Saturated Description Multiply two signed 32-bit integers, add the product to a signed 32-bit or 64-bit integer and put the result into a 32- bit or 64-bit register. The value const9 is sign-extended before the multiplication is performed. The MADDS result is saturated on overflow.
Page 231 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 21 20 12 11 05 H const9 13 H result = D[d] + (D[a] * sign_ext(const9)); D[c] = ssov(result, 32); MADDSE[c], E[d], D[a], const9 (RCR) 64 + (32 * K9)-->...
Page 232 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples madd d0, d1, d2, d3 madd d0, d1, d2, #7 madd e0, e2, d6, d11 madd e0, e0, d3, #80 madds d5, d1, d2, d2 madds...
Page 233 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD.H Packed Multiply-Add Q Format MADDS.H Packed Multiply-Add Q Format, Saturated Description Multiply two signed 16-bit (half-word) values, add the product (left justified if n == 1) to a signed 32-bit value and put the result into a 32-bit register.
Page 234 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1); mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][31:16]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) <<...
Page 235 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set result_word0 = E[d][31:0] + mul_res0; E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)}; // Packed fraction MADDS.HE[c], E[d], D[a], D[b] UL, n (RRR1) 32||32 +||+ (16U * 16U || 16L * 16L)--> saturated 28 27 24 23 18 17...
Page 236 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also User Manual (Volume 2) 3-189 V1.0 2013-07...
Page 237 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD.Q Multiply-Add Q Format MADDS.Q Multiply-Add Q Format, Saturated Description Multiply two signed 16-bit or 32-bit values, add the product (left justified if n == 1) to a signed 32-bit or 64-bit value and put the result into a 32-bit or 64-bit register.
Page 238 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 32 + (16U * 32)Up --> 32 28 27 24 23 18 17 16 15 12 11 00 H 43 H result = D[d]+ (((D[a] * D[b][31:16]) << n) >> 16); D[c] = result[31:0];...
Page 239 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD.QE[c], E[d], D[a] U, D[b] U, n (RRR1) 64 + (16U * 16U) --> 64 28 27 24 23 18 17 16 15 12 11 1C H 43 H sc = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1);...
Page 240 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 20 H 43 H result = D[d] + (((D[a] * D[b][31:16]) << n) >> 16); D[c] = ssov(result, 32); // Fraction MADDS.QE[c], E[d], D[a], D[b] U, n (RRR1) 64 + (16U * 32) -->...
Page 241 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 64 + (16U * 16U) --> 64 saturated 28 27 24 23 18 17 16 15 12 11 3C H 43 H sc = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1);...
Page 242 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also User Manual (Volume 2) 3-195 V1.0 2013-07...
Page 243 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD.U Multiply-Add Unsigned MADDS.U Multiply-Add Unsigned, Saturated Description Multiply two unsigned 32-bit integers, add the product to an unsigned 32-bit or 64-bit integer, and put the result into a 32-bit or 64-bit register. The value const9 is zero-extended before the multiplication is performed. The MADDS.U result is saturated on overflow.
Page 244 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 16 15 12 11 88 H 03 H result= D[d] + (D[a] * D[b]); // unsigned operators D[c] = suov(result, 32); MADDS.UE[c], E[d], D[a], D[b] (RRR2) 64 + (32 * 32) -->...
Page 245 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDM.H Packed Multiply-Add Q Format Multi-precision MADDMS.H Packed Multiply-Add Q Format Multi-precision, Saturated Description Perform two multiplications of two signed 16-bit (half-word) values. Add the two products (left justified if n == 1) left-shifted by 16, to a signed 64-bit value and put the result in a 64-bit register.
Page 246 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set result_word0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result = E[d] + ((result_word1 + result_word0) << 16); E[c] = result[63:0]; // Multi-precision accumulator MADDM.HE[c], E[d], D[a], D[b] UU, n (RRR1) 64 + (16L * 16U) + (16U * 16U) -->...
Page 247 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 3C H 83 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 248 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDR.H Packed Multiply-Add Q Format with Rounding MADDRS.H Packed Multiply-Add Q Format with Rounding, Saturated Description Multiply two signed 16-bit (half-word) values, add the product (left justified if n == 1) to a signed 16-bit or 32-bit value and put the rounded result into half of a 32-bit register (Note that since there are two results the two register halves are used).
Page 249 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 0C H 83 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 250 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000 result_halfword0 = {D[d][15:0], 16’b0} + mul_res0 + 8000 D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};...
Page 251 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][31:16]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result_halfword1 = E[d][63:32] + mul_res1 + 8000 result_halfword0 = E[d][31:0] + mul_res0 + 8000 D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};...
Page 252 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDR.Q Multiply-Add Q Format with Rounding MADDRS.Q Multiply-Add Q Format with Rounding, Saturated Description Multiply two signed 16-bit (half-word) values, add the product (left justified if n == 1) to a 32-bit signed value, and put the rounded result in a 32-bit register.
Page 253 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 26 H 43 H sc = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); mul_res = sc ? 7FFFFFFF : ((D[a][31:16] * D[b][31:16]) <<...
Page 254 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDSU.H Packed Multiply-Add/Subtract Q Format MADDSUS.H Packed Multiply-Add/Subtract Q Format Saturated Description Multiply two signed 16-bit (half-word) values. Add (or subtract) the product (left justified if n == 1) to a signed 32- bit value and put the result into a 32-bit register.
Page 255 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 18 H C3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 256 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][31:16]) << n); result_word1 = E[d][63:32] + mul_res1; result_word0 = E[d][31:0] - mul_res0; E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)};...
Page 257 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples See Also User Manual (Volume 2) 3-210 V1.0 2013-07...
Page 258 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDSUM.H Packed Multiply-Add/Subtract Q Format Multi-precision MADDSUMS.H Packed Multiply-Add/Subtract Q Format Multi-precision Saturated Description Perform two multiplications of two signed 16-bit (half-word) values. Add one product and subtract the other product (left justified if n == 1) left-shifted by 16, to/from a signed 64-bit value and put the result in a 64-bit register.
Page 259 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 1C H C3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 260 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set E[c] = ssov(result, 64); // Multi-precision accumulator MADDSUMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) 64 + (16U * 16U) - (16L * 16L) --> 64 saturated 28 27 24 23 18 17 16 15...
Page 261 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADDSUR.H Packed Multiply-Add/Subtract Q Format with Rounding MADDSURS.H Packed Multiply-Add/Subtract Q Format with Rounding Saturated Description Multiply two signed 16-bit (half-word) values. Add (subtract) the product (left justified if n == 1) to (from) a signed 16-bit value and put the rounded result into half of a 32-bit register (Note that since there are two results, the two register halves are used).
Page 262 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 0C H C3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 263 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set sc0 = (D[a][15:0] == 8000 ) AND (D[b][31:16]] == 8000 ) AND (n == 1); mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][31:16]) <<...
Page 264 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ov_halfword1 = (result_halfword1 > 7FFFFFFF ) OR (result_halfword1 < -80000000 ov_halfword0 = (result_halfword0 > 7FFFFFFF ) OR (result_halfword0 < -80000000 overflow = ov_halfword1 OR ov_halfword0; if (overflow) then PSW.V = 1 else PSW.V = 0; if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;...
Page 265 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Maximum Value MAX.U Maximum Value Unsigned Description If the contents of data register D[a] are greater than the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), then put the contents of D[a] in data register D[c]; otherwise put the contents of either D[b] (format RR) or const9 (format RC) in D[c].
Page 266 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set max.u d3, d1, d2 max.u d3, d1, #126 See Also MIN, User Manual (Volume 2) 3-219 V1.0 2013-07...
Page 267 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MAX.B Maximum Value Packed Byte MAX.BU Maximum Value Packed Byte Unsigned Description Compute the maximum value of the corresponding bytes in D[a] and D[b] and put each result in the corresponding byte of D[c].
Page 268 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MAX.H Maximum Value Packed Half-word MAX.HU Maximum Value Packed Half-word Unsigned Description Compute the maximum value of the corresponding half-words in D[a] and D[b] and put each result in the corresponding half-word of D[c].
Page 269 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MFCR Move From Core Register Description Move the contents of the Core Special Function Register (CSFR), selected by the value const16, to data register D[c]. The CSFR address is a const16 byte offset from the CSFR base address. It must be word-aligned (the least- significant two bits equal zero).
Page 270 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Minimum Value MIN.U Minimum Value Unsigned Description If the contents of data register D[a] are less than the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), then put the contents of D[a] in data register D[c]; otherwise put the contents of either D[b] (format RR) or const9 (format RC) in to D[c].
Page 271 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set min.u d3, d1, d2 min.u d3, d1, #126 See Also MAX, MAX.U User Manual (Volume 2) 3-224 V1.0 2013-07...
Page 272 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MIN.B Minimum Value Packed Byte MIN.BU Minimum Value Packed Byte Unsigned Description Compute the minimum value of the corresponding bytes in D[a] and D[b] and put each result in the corresponding byte of D[c].
Page 273 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MIN.H Minimum Value Packed Half-word MIN.HU Minimum Value Packed Half-word Unsigned Description Compute the minimum value of the corresponding half-words in D[a] and D[b] and put each result in the corresponding half-word of D[c].
Page 274 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Move Description Move the contents of either data register D[b] (instruction format RR) or const16 (instruction format RLC), to data register D[c]. The value const16 is sign-extended to 32-bits before it is moved. The syntax is also valid with a register pair as a destination.
Page 275 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set const8 DA H D[15] = zero_ext(const8); MOVD[a], const4 (SRC) 12 11 const4 82 H D[a] = sign_ext(const4); MOVE[a], const4 (SRC) 12 11 const4 D2 H E[a] = sign_ext(const4); MOVD[a], D[b] (SRR) 12 11 02 H D[a] = D[b];...
Page 276 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also MAX, MAX.U, MOV.U, MOVH User Manual (Volume 2) 3-229 V1.0 2013-07...
Page 277 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOV.A Move Value to Address Register Description Move the contents of data register D[b] to address register A[c]. Move the contents of either data register D[b] (format SRR) or const4 (format SRC) to address register A[a]. The value const4 is zero-extended before it is moved.
Page 278 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOV.AA Move Address from Address Register Description Move the contents of address register A[b] to address register A[c]. Move the contents of address register A[b] to address register A[a]. MOV.AAA[c], A[b] (RR) 28 27 20 19...
Page 279 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOV.D Move Address to Data Register Description Move the contents of address register A[b] to data register D[c]. Move the contents of address register A[b] to data register D[a]. MOV.DD[c], A[b] (RR) 28 27 20 19...
Page 280 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOV.U Move Unsigned Description Move the zero-extended value const16 to data register D[c]. MOV.UD[c], const16 (RLC) 28 27 12 11 const16 BB H D[c] = zero_ext(const16); Status Flags Not set by this instruction. Not set by this instruction.
Page 281 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOVH Move High Description Move the value const16 to the most-significant half-word of data register D[c] and set the least-significant 16-bits to zero. MOVHD[c], const16 (RLC) 28 27 12 11 const16 7B H D[c] = {const16, 16’h0000};...
Page 282 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MOVH.A Move High to Address Description Move the value const16 to the most-significant half-word of address register A[c] and set the least-significant 16- bits to zero. MOVH.AA[c], const16 (RLC) 28 27 12 11 const16...
Page 283 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB Multiply-Subtract MSUBS Multiply-Subtract, Saturated Description Multiply two signed 32-bit integers. Subtract the product from a signed 32-bit or 64-bit integer and put the result into a 32-bit or 64-bit register. The value const9 is sign-extended before the multiplication is performed. The MSUBS result is saturated on overflow.
Page 284 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 21 20 12 11 05 H const9 33 H result = D[d] - (D[a] * sign_ext(const9)); D[c] = ssov(result, 32); MSUBSE[c], E[d], D[a], const9 (RCR) 64 - (32 * K9) -->...
Page 285 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples msub d0, d1, d2, d3 msub d0, d1, d2, #7 msub e0, e2, d6, d11 msub e0, e0, d3, #80 msubs d5, d1, d2, d2 msubs...
Page 286 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB.H Packed Multiply-Subtract Q Format MSUBS.H Packed Multiply-Subtract Q Format, Saturated Description Multiply two signed 16-bit (half-word) values. Subtract the product (left justified if n == 1) from a signed 32-bit value and put the result into a 32-bit register.
Page 287 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][31:16]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result_word1 = E[d][63:32] - mul_res1; result_word0 = E[d][31:0] - mul_res0; E[c] = {result_word1[31:0], result_word0[31:0]};...
Page 288 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)}; // Packed fraction MSUBS.HE[c], E[d], D[a], D[b] UL, n (RRR1) 32||32 -||- (16U * 16U || 16L * 16L) --> 32||32 saturated 28 27 24 23 18 17 16 15...
Page 289 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set See Also User Manual (Volume 2) 3-242 V1.0 2013-07...
Page 290 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB.Q Multiply-Subtract Q Format MSUBS.Q Multiply-Subtract Q Format, Saturated Description Multiply two signed 16-bit or 32-bit values, subtract the product (left justified if n == 1) from a signed 32-bit or 64- bit value and put the result into a 32-bit or 64-bit register.
Page 291 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB.QD[c], D[d], D[a], D[b] U, n (RRR1) 32 - (32 * 16U)Up --> 32 28 27 24 23 18 17 16 15 12 11 00 H 63 H result = D[d] - (((D[a] * D[b][31:16]) << n) >> 16); D[c] = result[31:0];...
Page 292 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set D[c] = result[31:0]; // Fraction MSUB.QE[c], E[d], D[a] U, D[b] U, n (RRR1) 64 - (16U * 16U) --> 64 28 27 24 23 18 17 16 15 12 11 1C H 63 H sc = (D[a][31:16] == 8000...
Page 293 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 32 - (32 * 16U)Up --> 32 saturated 28 27 24 23 18 17 16 15 12 11 20 H 63 H result = D[d] - (((D[a] * D[b][31:16]) << n) >> 16); D[c] = ssov(result, 32);...
Page 294 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBS.QE[c], E[d], D[a] U, D[b] U, n (RRR1) 64 - (16U * 16U) --> 64 saturated 28 27 24 23 18 17 16 15 12 11 3C H 63 H sc = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1);...
Page 295 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set msubs.q e2, e0, d11L, d4L, #1 See Also User Manual (Volume 2) 3-248 V1.0 2013-07...
Page 296 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB.U Multiply-Subtract Unsigned MSUBS.U Multiply-Subtract Unsigned, Saturated Description Multiply two unsigned 32-bit integers. Subtract the product from an unsigned 32-bit or 64-bit integer and put the result into a 32-bit or 64-bit register. The value const9 is zero-extended before the multiplication is performed. The MSUBS.U results are saturated on overflow.
Page 297 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 16 15 12 11 88 H 23 H result = D[d] - (D[a] * D[b]); // unsigned operators D[c]= suov(result, 32); MSUBS.UE[c], E[d], D[a], D[b] (RRR2) 64 - (32 * 32) -->...
Page 298 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBAD.H Packed Multiply-Subtract/Add Q Format MSUBADS.H Packed Multiply-Subtract/Add Q Format, Saturated Description Multiply two signed 16-bit (half-word) values. Subtract (or add) the product (left justified if n == 1) from a signed 32-bit value and put the result into a 32-bit register.
Page 299 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 18 H E3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 300 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][31:16]) << n); result_word1 = E[d][63:32] - mul_res1; result_word0 = E[d][31:0] + mul_res0; E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)};...
Page 301 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples See Also User Manual (Volume 2) 3-254 V1.0 2013-07...
Page 302 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBADM.H Packed Multiply-Subtract/Add Q Format-Multi-precision MSUBADMS.H Packed Multiply-Subtract/Add Q Format-Multi-precision, Saturated Description Perform two multiplications of two signed 16-bit (half-word) values. Subtract one product and add the other product (left justified if n == 1) left-shifted by 16, from/to a signed 64-bit value and put the result in a 64-bit register.
Page 303 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 1C H E3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 304 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set E[c] = ssov(result, 64); // Multi-precision accumulator MSUBADMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) 64 - (16U * 16U) + (16L * 16L) --> 64 saturated 28 27 24 23 18 17 16 15...
Page 305 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBADR.H Packed Multiply-Subtract/Add Q Format with Rounding MSUBADRS.H Packed Multiply-Subtract/Add Q Format with Rounding, Saturated Description Multiply two signed 16-bit (half-word) values. Subtract (or add) the product (left justified if n == 1) from (to) a signed 16-bit value and put the rounded result into half of a 32-bit register (Note that since there are two results the two register halves are used).
Page 306 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 0C H E3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 307 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set sc0 = (D[a][15:0] == 8000 ) AND (D[b][31:16]] == 8000 ) AND (n == 1); mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][31:16]) <<...
Page 308 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set aov_halfword1 = result_halfword1[31] ^ result_halfword1[30]; aov_halfword0 = result_halfword0[31] ^ result_halfword0[30]; advanced_overflow = aov_halfword1 OR aov_halfword0; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; if (advanced_overflow) then PSW.SAV = 1; else PSW.SAV = PSW.SAV; Examples See Also User Manual (Volume 2)
Page 309 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBM.H Packed Multiply-Subtract Q Format-Multi-precision MSUBMS.H Packed Multiply-Subtract Q Format-Multi-precision, Saturated Description Perform two multiplications of two signed 16-bit (half-word) values. Subtract the two products (left justified if n == 1) left-shifted by 16, from a signed 64-bit value and put the result in a 64-bit register.
Page 310 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 1C H A3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 311 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set E[c] = ssov(result, 64); // Multi-precision accumulator MSUBMS.HE[c], E[d], D[a], D[b] UL, n (RRR1) 64 - (16U * 16U) - (16L * 16L) > 64 saturated 28 27 24 23 18 17 16 15 12 11...
Page 312 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBR.H Packed Multiply-Subtract Q Format with Rounding MSUBRS.H Packed Multiply-Subtract Q Format with Rounding, Saturated Description Multiply two signed 16-bit (half-word) values. Subtract the product (left justified if n == 1) from a signed 16-bit or 32-bit value and put the rounded result into half of a 32-bit register.
Page 313 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 0C H A3 H sc1 = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); sc0 = (D[a][15:0] == 8000 ) AND (D[b][15:0] == 8000 ) AND (n == 1);...
Page 314 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res1 = sc1 ? 7FFFFFFF : ((D[a][31:16] * D[b][15:0]) << n); mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result_halfword1 = {D[d][31:16], 16’b0} - mul_res1 + 8000 result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000 D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};...
Page 315 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set mul_res0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result_halfword1 = E[d][63:32] - mul_res1 + 8000 result_halfword0 = E[d][31:0] - mul_res0 + 8000 D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]}; // Packed short fraction result MSUBRS.HD[c], D[d], D[a], D[b] UU, n (RRR1) 16U || 16L -||- (16L * 16U || 16U * 16U) rounded -->...
Page 316 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUBR.Q Multiply-Subtract Q Format with Rounding MSUBRS.Q Multiply-Subtract Q Format with Rounding, Saturated Description Multiply two signed 16-bit (half-word) values. Subtract the product (left justified if n == 1) from a 32-bit signed value, and put the rounded result in a 32-bit register.
Page 317 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 24 23 18 17 16 15 12 11 26 H 63 H sc = (D[a][31:16] == 8000 ) AND (D[b][31:16] == 8000 ) AND (n == 1); mul_res = sc ? 7FFFFFFF : ((D[a][31:16] * D[b][31:16]) <<...
Page 318 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MTCR Move To Core Register Description Note: This instruction can only be executed in Supervisor mode. Move the value in data register D[a] to the Core Special Function Register (CSFR) selected by the value const16. The CSFR address is a const16 byte offset from the CSFR base address.
Page 319 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Multiply MULS Multiply, Saturated Description Multiply two signed 32-bit integers and put the product into a 32-bit or 64-bit register. The value const9 is sign- extended before the multiplication is performed. The MULS result is saturated on overflow. Multiply D[a] by D[b] (two signed 32-bit integers) and put the product into D[a].
Page 320 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 12 11 E2 H result = D[a] * D[b]; D[a] = result[31:0]; MULSD[c], D[a], const9 (RC) (32 * K9) --> 32 signed saturated 28 27 21 20 12 11 05 H const9 53 H...
Page 321 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set d3, d11 See Also MUL.U, MADD, MSUB User Manual (Volume 2) 3-274 V1.0 2013-07...
Page 322 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MUL.H Packed Multiply Q Format Description Multiply two signed 16-bit (half-word) values and put the product (left justified if n == 1) into a 32-bit register. Note that since there are two results both halves of an extended data register are used. There are four cases of half- word multiplication: •...
Page 323 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set E[c] = {result_word1[31:0], result_word0[31:0]}; // Packed fraction MUL.HE[c], D[a], D[b] UU, n (RR1) (16L * 16U || 16U * 16U) --> 32||32 28 27 18 17 16 15 12 11 1B H B3 H sc1 = (D[a][15:0] == 8000...
Page 324 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MUL.Q Multiply Q Format Description Multiply two signed 16-bit or 32-bit values and put the product (left justified if n == 1) into a 32-bit or 64-bit register. There are two cases of 16*16 operations, four cases of 16*32 operations and two cases of 32*32 operations. Note that n should only take the values 0 or 1, any other value returns an undefined result.
Page 325 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 18 17 16 15 12 11 00 H 93 H result = ((D[a] * D[b][31:16]) << n) >> 16; D[c] = result[31:0];// Fraction MUL.QE[c], D[a], D[b] U, n (RR1) (32 * 16U) -->...
Page 326 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 32-bit result: advanced_overflow = result[31] ^ result[30]; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; 64-bit result: advanced_overflow = result[63] ^ result[62]; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;...
Page 327 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MUL.U Multiply Unsigned MULS.U Multiply Unsigned, Saturated Description Multiply two unsigned 32-bit integers and put the product into a 32-bit or 64-bit register. The value const9 (instruction format RC) is zero-extended before the multiplication is performed. The MULS.U result is saturated on overflow.
Page 328 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 32-bit result: overflow = (result > FFFFFFFF ) OR (result < 00000000 if (overflow) then PSW.V = 1 else PSW.V = 0; 64-bit result: It is mathematically impossible to generate an overflow when multiplying two 32-bit numbers and storing the result in a 64-bit register.
Page 329 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MULM.H Packed Multiply Q Format-Multi-precision Description Perform two multiplications of two signed 16-bit (half-word) values. Add the two products (left justified if n == 1) left-shifted by 16, in a 64-bit register. There are four cases of half-word multiplication: •...
Page 330 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set result_word0 = sc0 ? 7FFFFFFF : ((D[a][15:0] * D[b][15:0]) << n); result = (result_word1 + result_word0) << 16; E[c] = result[63:0]; // Multi-precision accumulator MULM.HE[c], D[a], D[b] UU, n (RR1) 16L * 16U + 16U * 16U -->...
Page 331 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MULMS.H MULMS.H (DEPRECATED) (Note: Deprecated in TC2!) Description MULMS.H E[c], D[a], D[b] LL, n (RR1) 28 27 18 17 16 15 12 11 3E H B3 H MULMS.H E[c], D[a], D[b] LU, n (RR1) 28 27 18 17 16 15...
Page 332 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MULR.H Packed Multiply Q Format with Rounding Description Multiply two signed 16-bit (half-word) values. Add the product (left justified if n == 1) to a signed 16-bit value and put the rounded result into half of a 32-bit register.
Page 333 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set D[c] = {result_halfword1[31:16], result_halfword0[31:16]}; // Packed short fraction MULR.HD[c], D[a], D[b] UU, n (RR1) (16L * 16U || 16U * 16U) rounded --> 16||16 28 27 18 17 16 15 12 11 0F H B3 H...
Page 334 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MULR.Q Multiply Q Format with Rounding Description Multiply two signed 16-bit (half-word) values and put the rounded result (left justified if n == 1) into a 32-bit register. The lower half-word is cleared. Note that n should only take the values 0 or 1, any other value returns an undefined result.
Page 335 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NAND Bitwise NAND Description Compute the bitwise NAND of the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is zero-extended. NANDD[c], D[a], const9 (RC) 28 27 21 20...
Page 336 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NAND.T Bit Logical NAND Description Compute the logical NAND of bit pos1 of data register D[a], and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. NAND.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 337 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Not Equal Description If the contents of data register D[a] are not equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c].
Page 338 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NE.A Not Equal Address Description If the contents of address registers A[a] and A[b] are not equal, set the least-significant bit of D[c] to one and clear the remaining bits to zero; otherwise clear all bits in D[c]. NE.AD[c], A[a], A[b] (RR) 28 27 20 19...
Page 339 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NEZ.A Not Equal Zero Address Description If the contents of address register A[a] are not equal to zero, set the least significant bit of D[c] to one and clear the remaining bits to zero;...
Page 340 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set No Operation Description Used to implement efficient low-power, non-operational instructions. Used to implement efficient low-power, non-operational instructions. NOP(SR) 12 11 00 H 00 H No operation. NOP(SYS) 28 27 22 21 12 11 00 H...
Page 341 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Bitwise NOR Description Compute the bitwise NOR of the contents of data register D[a] and the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC) and put the result in data register D[c]. The const9 value is zero-extended.
Page 342 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NOR.T Bit Logical NOR Description Compute the logical NOR of bit pos1 of data register D[a] and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. NOR.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 343 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set NOT (16-bit) Bitwise Complement NOT (16-bit) Description Compute the bitwise NOT of the contents of register D[a] and put the result in data register D[a]. NOTD[a] (SR) 12 11 00 H 46 H D[a] = ~D[a];...
Page 344 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Bitwise OR Description Compute the bitwise OR of the contents of data register D[a] and the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is zero-extended.
Page 345 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples d3, d1, d2 d3, d1, #126 d1, d2 d15, #126 See Also AND, ANDN, NAND, NOR, (16-bit), ORN, XNOR, User Manual (Volume 2) 3-298 V1.0 2013-07...
Page 346 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.AND.T Accumulating Bit Logical OR-AND OR.ANDN.T Accumulating Bit Logical OR-AND-Not OR.NOR.T Accumulating Bit Logical OR-NOR OR.OR.T Accumulating Bit Logical OR-OR Description Compute the logical operation (AND, ANDN, NOR or OR as appropriate) of the value of bit pos1 of data register D[a], and bit pos2 of D[b].
Page 347 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Not set by these instructions. Examples or.and.t d3, d1, 3, d2, 5 or.andn.t d3, d1, 3, d2, 5 or.nor.t d3, d1, 3, d2, 5 or.or.t d3, d1, 3, d2, 5 See Also AND.AND.T, AND.ANDN.T, AND.NOR.T, AND.OR.T, SH.AND.T, SH.ANDN.T, SH.NAND.T, SH.NOR.T, SH.OR.T, SH.ORN.T,...
Page 348 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.EQ Equal Accumulating Description Compute the logical OR of D[c][0] and the Boolean result of the EQ operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in D[c][0]. All other bits in D[c] are unchanged.
Page 349 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.GE Greater Than or Equal Accumulating OR.GE.U Greater Than or Equal Accumulating Unsigned Description Calculate the logical OR of D[c][0] and the Boolean result of the GE or GE.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 350 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set or.ge.u d3, d1, d2 or.ge.u d3, d1, #126 See Also AND.GE, AND.GE.U, XOR.GE, XOR.GE.U User Manual (Volume 2) 3-303 V1.0 2013-07...
Page 351 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.LT Less Than Accumulating OR.LT.U Less Than Accumulating Unsigned Description Calculate the logical OR of D[c][0] and the Boolean result of the LT or LT.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 352 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set or.lt.u d3, d1, d2 or.lt.u d3, d1, #126 See Also AND.LT, AND.LT.U, XOR.LT, XOR.LT.U User Manual (Volume 2) 3-305 V1.0 2013-07...
Page 353 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.NE Not Equal Accumulating Description Calculate the logical OR of D[c][0] and the Boolean result of the NE operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in D[c][0]. All other bits in D[c] are unchanged.
Page 354 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set OR.T Bit Logical OR Description Compute the logical OR of bit pos1 of data register D[a] and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c]. Clear the remaining bits of D[c]. OR.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 355 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Bitwise OR-Not Description Compute the bitwise OR of the contents of data register D[a] and the ones’ complement of the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is zero-extended to 32-bits.
Page 356 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ORN.T Bit Logical OR-Not Description Compute the logical OR of bit pos1 of data register D[a] and the inverse of bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. ORN.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 357 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set PACK Pack Description Take the data register pair E[d] and bit 31 of data register D[a] and pack them into an IEEE-754-1985 single precision floating point format number, in data register D[c]. The odd register E[d][63:32], holds the unbiased exponent.
Page 358 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set } else { // Normal temp_exp = int_exp + 128; fp_exp_frac[30:0] = {tmp_exp[7:0], int_mant[30:8]} + flag_rnd; fp_exp = fp_exp_frac[30:23]; fp_frac = fp_exp_frac[22:0]; D[c][31] = D[a][31]; D[c][30:23] = fp_exp; D[c][22:0] = fp_frac; Status Flags PSW.C is read by the instruction but not set by this instruction.
Page 359 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set PARITY Parity Description Compute the four byte parity bits of data register D[a]. Put each byte parity bit into every 8th bit of the data register D[c] and then clear the remaining bits of D[c]. A byte parity bit is set to one if the number of ones in a byte is an odd number.
Page 360 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set RESTORE Restore Description Restore the Interrupt Enable bit (ICR.IE) to the value saved in D[a][0]. RESTORE can only be executed in User-1 or Supervisor mode. RESTORED[a] (SYS) 28 27 22 21 12 11 0E H...
Page 361 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Return from Call Description Return from a function that was invoked with a CALL instruction. The return address is in register A[11] (return address). The caller’s upper context register values are restored as part of the return operation. Return from a function that was invoked with a CALL instruction.
Page 362 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set PSW.V is overwritten with the value restored from the CSA. PSW.SV is overwritten with the value restored from the CSA. PSW.AV is overwritten with the value restored from the CSA. PSW.SAV is overwritten with the value restored from the CSA.
Page 363 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Return From Exception Description Return from an interrupt service routine or trap handler to the task whose saved upper context is specified by the contents of the Previous Context Information register (PCXI). The contents are normally the context of the task that was interrupted or that took a trap.
Page 364 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set {new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); M(EA, word) = FCX; FCX[19:0] = PCXI[19:0]; PCXI = new_PCXI; Status Flags PSW.C is overwritten with the value restored from the Context Save Area (CSA).
Page 365 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Return From Monitor Description Note: The RFM instruction can only be executed in Supervisor mode. If the Debug mode is disabled (DBGSR.DE==0) execute as a NOP; otherwise return from a breakpoint monitor to the task whose saved debug context area is located at DCX (Debug Context Pointer).
Page 366 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set RSLCX Restore Lower Context Description Load the contents of the memory block pointed to by the PCX field in PCXI into registers A[2] to A[7], D[0] to D[7], A[11] (return address), and PCXI. This operation restores the register contents of a previously saved lower context.
Page 367 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set RSTV Reset Overflow Bits Description Reset overflow status flags in the Program Status Word (PSW). RSTV(SYS) 28 27 22 21 12 11 00 H 2F H PSW.{V, SV, AV, SAV} = {0, 0, 0, 0}; Status Flags Not set by this instruction.
Page 368 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set RSUB Reverse-Subtract Description Subtract the contents of data register D[a] from the value const9 and put the result in data register D[c]. The operands are treated as 32-bit integers. The value const9 is sign-extended before the subtraction is performed. Subtract the contents of data register D[a] from zero and put the result in data register D[a].
Page 369 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set RSUBS Reverse-Subtract with Saturation RSUBS.U Reverse-Subtract Unsigned with Saturation Description Subtract the contents of data register D[a] from the value const9 and put the result in data register D[c]. The operands are treated as signed (RSUBS) or unsigned (RSUBS.U) 32-bit integers, with saturation on signed (RSUBS) or unsigned (RSUBS.U) overflow.
Page 370 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SAT.B Saturate Byte Description If the signed 32-bit value in D[a] is less than -128, then store the value -128 in D[c]. If D[a] is greater than 127, then store the value 127 in D[c].
Page 371 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SAT.BU Saturate Byte Unsigned Description If the unsigned 32-bit value in D[a] is greater than 255, then store the value 255 in D[c]. Otherwise copy D[a] to D[c]. If the unsigned 32-bit value in D[a] is greater than 255, then store the value 255 in D[a]. Otherwise leave the contents of D[a] unchanged.
Page 372 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SAT.H Saturate Half-word Description If the signed 32-bit value in D[a] is less than -32,768, then store the value -32,768 in D[c]. If D[a] is greater than 32,767, then store the value 32,767 in D[c]. Otherwise copy D[a] to D[c]. If the signed 32-bit value in D[a] is less than -32,768, then store the value -32,768 in D[a].
Page 373 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SAT.HU Saturate Half-word Unsigned Description If the unsigned 32-bit value in D[a] is greater than 65,535, then store the value 65,535 in D[c]; otherwise copy D[a] to D[c]. If the unsigned 32-bit value in D[a] is greater than 65,535, then store the value 65,535 in D[a]; otherwise leave the contents of D[a] unchanged.
Page 374 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Select Description If the contents of data register D[d] are non-zero, copy the contents of data register D[a] to data register D[c]; otherwise copy the contents of either D[b] (instruction format RRR) or const9 (instruction format RCR), to D[c]. The value const9 (instruction format RCR) is sign-extended.
Page 375 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SELN Select-Not Description If the contents of data register D[d] are zero, copy the contents of data register D[a] to data register D[c]; otherwise copy the contents of either D[b] or const9 to D[c]. The value const9 (instruction format RCR) is sign-extended.
Page 376 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Shift Description Shift the value in D[a] by the amount specified by shift count. If the shift count specified through the contents of either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift. Otherwise right-shift by the absolute value of the shift count.
Page 377 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples d3, d1, d2 d3, d1, #26 d1, #6 See Also SH.H, SHA, SHA.H, SHAS User Manual (Volume 2) 3-330 V1.0 2013-07...
Page 378 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.EQ Shift Equal Description Left shift D[c] by one. If the contents of data register D[a] are equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one; otherwise set the least-significant bit of D[c] to 0.
Page 379 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.GE Shift Greater Than or Equal SH.GE.U Shift Greater Than or Equal Unsigned Description Left shift D[c] by one. If the contents of data register D[a] are greater than or equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one;...
Page 380 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set sh.ge.u d3, d1, d2 sh.ge.u d3, d1, #126 See Also SH.EQ, SH.LT, SH.LT.U, SH.NE User Manual (Volume 2) 3-333 V1.0 2013-07...
Page 381 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.H Shift Packed Half-words Description If the shift count specified through the contents of either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift each half-word in D[a] by the amount specified by shift count. Otherwise, right-shift each half-word in D[a] by the absolute value of the shift count.
Page 382 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.LT Shift Less Than SH.LT.U Shift Less Than Unsigned Description Left shift D[c] by one. If the contents of data register D[a] are less than the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one;...
Page 383 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples sh.lt d3, d1, d2 sh.lt d3, d1, #126 sh.lt.u d3, d1, d2 sh.lt.u d3, d1, #126 See Also SH.EQ, SH.GE, SH.GE.U, SH.NE User Manual (Volume 2) 3-336 V1.0 2013-07...
Page 384 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.NE Shift Not Equal Description Left shift D[c] by one. If the contents of data register D[a] are not equal to the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one; otherwise set the least-significant bit of D[c] to zero.
Page 385 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.AND.T Accumulating Shift-AND SH.ANDN.T Accumulating Shift-AND-Not SH.NAND.T Accumulating Shift-NAND SH.NOR.T Accumulating Shift-NOR SH.OR.T Accumulating Shift-OR SH.ORN.T Accumulating Shift-OR-Not SH.XNOR.T Accumulating Shift-XNOR SH.XOR.T Accumulating Shift-XOR Description Left shift D[c] by one. The bit shifted out is discarded. Compute the logical operation (AND, ANDN, NAND, NOR, OR, ORN, XNOR or XOR) of the value of bit pos1 of data register D[a], and bit pos2 of D[b].
Page 386 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SH.OR.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22 21 20 16 15 12 11 pos2 01 H pos1 27 H D[c] = {D[c][30:0], (D[a][pos1] OR D[b][pos2])}; SH.ORN.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22 21 20...
Page 387 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Arithmetic Shift Description If shift count specified through contents of either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift the value in D[a] by the amount specified by shift count. The vacated bits are filled with zeros and bits shifted out are discarded.
Page 388 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set shift_count = 0 - D[b][5:0]; msk = D[a][31] ? (((1 << shift_count) - 1) << (32 - shift_count)) : 0; result = msk | (D[a] >> shift_count); carry_out = (D[a][shift_count - 1:0] != 0); D[c] = result[31:0];...
Page 389 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SHA.H Arithmetic Shift Packed Half-words Description If the shift count specified through the contents of either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift each half-word in D[a] by the amount specified by shift count. The vacated bits are filled with zeros and bits shifted out are discarded.
Page 390 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set D[c][15:0] = result_halfword0[15:0]; D[c][31:16] = result_halfword1[15:0]; Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Examples sha.h d3, d1, d2...
Page 391 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SHAS Arithmetic Shift with Saturation Description If the shift count specified through the contents of either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift the value in D[a] by the amount specified by shift count. The vacated bits are filled with zeros and the result is saturated if its sign bit differs from the sign bits that are shifted out.
Page 392 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set advanced_overflow = result[31] ^ result[30]; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples shas d3, d1, d2 shas d3, d1, #26 See Also...
Page 393 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.A Store Word from Address Register Description Store the value in address register A[a] to the memory location specified by the addressing mode. Note: If the source register is modified by the addressing mode, the value stored to memory is undefinded. Store the value in address register A[a] (instruction format BO, SSR, SSRO or SSR) or A[15] (instruction format SRO or SC) to the memory location specified by the addressing mode.
Page 394 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; ST.AA[b], off10, A[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 06 H...
Page 395 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.AA[b], A[a] (SSR)(Post-increment Addressing Mode) 12 11 E4 H M(A[b], word) = A[a]; A[b] = A[b] + 4; ST.AA[15], off4, A[a] (SSRO) 12 11 off4 E8 H M(A[15] + zero_ext(4 * off4), word) = A[a]; Status Flags Not set by this instruction.
Page 396 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.B Store Byte Description Store the byte value in the eight least-significant bits of data register D[a] to the byte memory location specified by the addressing mode. Store the byte value in the eight least-significant bits of either data register D[a] (instruction format SSR, SSR0 or BO) or D[15] (instruction format SRO) to the byte memory location specified by the addressing mode.
Page 397 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; ST.BA[b], off10, D[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 00 H off10[5:0] 89 H EA = A[b]; M(EA, byte) = D[a][7:0]; A[b] = EA + sign_ext(off10);...
Page 398 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.BA[15], off4, D[a] (SSRO) 12 11 off4 28 H M(A[15] + zero_ext(off4), byte) = D[a][7:0]; Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction.
Page 399 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.D Store Double-word Description Store the value in the extended data register pair E[a] to the memory location specified by the addressing mode. The value in the even register D[n] is stored in the least-significant memory word, and the value in the odd register (D[n+1]) is stored in the most-significant memory word.
Page 400 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set M(EA4, halfword) = D[a+1][15:0]; M(EA6, halfword) = D[a+1][31:16]; new_index = index + sign_ext(off10); new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; ST.DA[b], off10, E[a] (BO)(Post-increment Addressing Mode) 28 27 22 21...
Page 401 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.DA Store Double-word from Address Registers Description Store the value in the address register pair A[a]/A[a+1] to the memory location specified by the addressing mode. The value in the even register A[a] is stored in the least-significant memory word, and the value in the odd register (A[a+1]) is stored in the most-significant memory word.
Page 402 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; ST.DAA[b], off10, P[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 07 H off10[5:0] 89 H EA = A[b]; M(EA, doubleword) = P[a]; A[b] = EA + sign_ext(off10);...
Page 403 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.H Store Half-word Description Store the half-word value in the 16 least-significant bits of data register D[a] to the half-word memory location specified by the addressing mode. Store the half-word value in the 16 least-significant bits of either data register D[a] (instruction format or D[15] to the half-word memory location specified by the addressing mode.
Page 404 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set A[b+1] = {length[15:0], new_index[15:0]}; ST.HA[b], off10, D[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 02 H off10[5:0] 89 H EA = A[b]; M(EA, halfword) = D[a][15:0]; A[b] = EA + sign_ext(off10);...
Page 405 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.HA[15], off4, D[a] (SSRO) 12 11 off4 A8 H M(A[15] + zero_ext(2 * off4), half-word) = D[a][15:0]; Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction.
Page 406 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.Q Store Half-word Signed Fraction Description Store the value in the most-significant half-word of data register D[a] to the memory location specified by the addressing mode. ST.Qoff18, D[a] (ABS)(Absolute Addressing Mode) 28 27 26 25 22 21...
Page 407 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set 28 27 22 21 16 15 12 11 off10[9:6] 08 H off10[5:0] 89 H EA = A[b]; M(EA, halfword) = D[a][31:16]; A[b] = EA + sign_ext(off10); ST.QA[b], off10, D[a] (BO)(Pre-increment Addressing Mode) 28 27 22 21 16 15...
Page 408 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.T Store Bit Description Store the bit value b to the byte at the memory address specified by off18, in the bit position specified by bpos3. The other bits of the byte are unchanged. Individual bits can be used as semaphore. ST.Toff18, bpos3, b (ABSB) 28 27 26 25...
Page 409 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.W Store Word Description Store the word value in data register D[a] to the memory location specified by the addressing mode. Store the word value in either data register D[a] (instruction format SSR, SSRO) or D[15] (instruction format SRO, SC) to the memory location specified by the addressing mode.
Page 410 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; ST.WA[b], off10, D[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 04 H...
Page 411 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ST.WA[b], D[a] (SSR)(Post-increment Addressing Mode) 12 11 64 H M(A[b], word) = D[a]; A[b] = A[b] + 4; ST.WA[15], off4, D[a] (SSRO) 12 11 off4 68 H M(A[15] + zero_ext(4 * off4), word) = D[a]; Status Flags Not set by this instruction.
Page 412 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set STLCX Store Lower Context Description Store the contents of registers A[2] to A[7], D[0] to D]7], A[11] (return address) and PCXI, to the memory block specified by the addressing mode. For this instruction, the addressing mode is limited to absolute (ABS) or base plus short offset (BO).
Page 413 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set STUCX Store Upper Context Description Store the contents of registers A[10] to A[15], D[8] to D[15], and the current PSW (the registers which comprise a task’s upper context) to the memory block specified by the addressing mode. For this instruction, the addressing mode is limited to absolute (ABS) or base plus short offset (BO).
Page 414 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Subtract Description Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register D[c]. The operands are treated as 32-bit integers. Subtract the contents of data register D[b] from the contents of either data register D[a] or D[15] and put the result in either data register D[a] or D[15].
Page 415 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set advanced_overflow = result[31] ^ result[30]; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples d3, d1, d2 d1, d2 d15, d1, d2 d1, d15, d2...
Page 416 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUB.A Subtract Address Description Subtract the contents of address register A[b] from the contents of address register A[a] and put the result in address register A[c]. Decrement the Stack Pointer (A[10]) by the zero-extended value of const8 (a range of 0 through to 255). SUB.AA[c], A[a], A[b] (RR) 28 27 20 19...
Page 417 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUB.B Subtract Packed Byte SUB.H Subtract Packed Half-word Description Subtract the contents of each byte or half-word of data register D[b] from the contents of data register D[a]. Put the result in each corresponding byte or half-word of data register D[c].
Page 418 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUB.B aov_byte3 = result_byte3[7] ^ result_byte3[6]; aov_byte2 = result_byte2[7] ^ result_byte2[6]; aov_byte1 = result_byte1[7] ^ result_byte1[6]; aov_byte0 = result_byte0[7] ^ result_byte0[6]; advanced_overflow = aov_byte3 OR aov_byte2 OR aov_byte1 OR aov_byte0; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;...
Page 419 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUBC Subtract With Carry Description Subtract the contents of data register D[b] from contents of data register D[a] plus the carry bit minus one. Put the result in data register D[c]. The operands are treated as 32-bit integers. The PSW carry bit is set to the value of the ALU carry out.
Page 420 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUBS Subtract Signed with Saturation SUBS.U Subtract Unsigned with Saturation Description Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register D[c].
Page 421 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set advanced_overflow = result[31] ^ result[30]; if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0; if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV; Examples subs d3, d1, d2 subs.u d3, d1, d2 subs...
Page 422 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUBS.H Subtract Packed Half-word with Saturation SUBS.HU Subtract Packed Half-word Unsigned with Saturation Description Subtract the contents of each half-word of data register D[b] from the contents of data register D[a]. Put the result in each corresponding half-word of data register D[c], with saturation on signed (SUBS.H) or unsigned (SUBS.HU) overflow.
Page 423 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Examples subs.h d3, d1, d2 subs.hu d3, d1, d2 See Also SUB.B, SUB.H User Manual (Volume 2) 3-376 V1.0 2013-07...
Page 424 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUBX Subtract Extended Description Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register D[c]. The operands are treated as 32-bit integers. The PSW carry bit is set to the value of the ALU carry out. SUBXD[c], D[a], D[b] (RR) 28 27 20 19...
Page 425 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SVLCX Save Lower Context Description Store the contents of registers A[2] to A[7], D[0] to D[7], A[11] (return address) and PCXI, to the memory location pointed to by the FCX register. This operation saves the lower context of the currently executing task. SVLCX(SYS) 28 27 22 21...
Page 426 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SWAP.W Swap with Data Register Description Swap atomically the contents of data register D[a] and the memory word specified by the addressing mode. SWAP.Woff18, D[a] (ABS)(Absolute Addressing Mode) 28 27 26 25 22 21 16 15...
Page 427 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set tmp = M(EA, word); M(EA, word) = D[a]; D[a] = tmp[31:0]; new_index = index + sign_ext(off10); new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]};...
Page 428 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SWAPMSK.W Swap under Mask Description The SWAPMSK.W instruction enables individual bits or bytes to be used as semaphore. Up to 32 semaphores (bits) can be tested in parallel. SWAPMSK.W uses an Extended register to provide both mask and swap data. It swaps through a mask the contents of E[a][31:0] with the contents of the memory word specified by the addressing mode.
Page 429 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set new_index = new_index < 0 ? new_index + length : new_index % length; A[b+1] = {length[15:0], new_index[15:0]}; SWAPMSK.WA[b], off10, E[a] (BO)(Post-increment Addressing Mode) 28 27 22 21 16 15 12 11 off10[9:6] 02 H...
Page 430 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SYSCALL System Call Description Cause a system call trap, using Trap Identification Number (TIN) specified by const9. Note: The trap return PC will be the instruction following the SYSCALL instruction. SYSCALLconst9 (RC) 28 27 21 20...
Page 431 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set TRAPSV Trap on Sticky Overflow Description If the PSW sticky overflow status flag (PSW.SV) is set, generate a trap to the vector entry for the sticky overflow trap handler (SOV-trap). TRAPSV(SYS) 28 27 22 21...
Page 432 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set TRAPV Trap on Overflow Description If the PSW overflow status flag (PSW.V) is set, generate a trap to the vector entry for the overflow trap handler (OVF trap). TRAPV(SYS) 28 27 22 21 12 11...
Page 433 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set UNPACK Unpack Floating Point Description Take an IEEE-754-1985 single precision floating point number in data register D[a] and unpack it as exponent and mantissa into data register pair E[c], such that it can be more easily processed through regular instructions. The odd register E[c][63:32] receives the unbiased exponent.
Page 434 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Status Flags Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Not set by this instruction. Examples unpack e2, d5 See Also PACK, SYSCALL,...
Page 435 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set WAIT Wait Description The WAIT instruction causes the processor to suspend execution until then next enabled interrupt or asynchronous event is detected. WAIT(SYS) 28 27 22 21 12 11 16 H 0D H Status Flags...
Page 436 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XNOR Bitwise XNOR Description Compute the bitwise exclusive NOR of the contents of data register D[a] and the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in to data register D[c]. The value const9 is zero-extended.
Page 437 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XNOR.T Bit Logical XNOR Description Compute the logical exclusive NOR of bit pos1 of data register D[a] and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. XNOR.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 438 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Bitwise XOR Description Compute the bitwise exclusive OR of the contents of data register D[a] and the contents of either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The value const9 is zero-extended to 32-bits.
Page 439 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XOR.EQ Equal Accumulating Description Compute the logical XOR of D[c][0] and the Boolean result of the EQ operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in D[c][0]. All other bits in D[c] are unchanged.
Page 440 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XOR.GE Greater Than or Equal Accumulating XOR.GE.U Greater Than or Equal Accumulating Unsigned Description Calculate the logical XOR of D[c][0] and the Boolean result of the GE or GE.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 441 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set xor.ge.u d3, d1, d2 xor.ge.u d3, d1, #126 See Also AND.GE, AND.GE.U, OR.GE, OR.GE.U User Manual (Volume 2) 3-394 V1.0 2013-07...
Page 442 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XOR.LT Less Than Accumulating XOR.LT.U Less Than Accumulating Unsigned Description Calculate the logical XOR of D[c][0] and the Boolean result of the LT or LT.U operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC).
Page 443 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set xor.lt.u d3, d1, d2 xor.lt.u d3, d1, #126 See Also AND.LT, AND.LT.U, OR.LT, OR.LT.U User Manual (Volume 2) 3-396 V1.0 2013-07...
Page 444 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XOR.NE Not Equal Accumulating Description Calculate the logical XOR of D[c][0] and the Boolean result of the NE operation on the contents of data register D[a] and either data register D[b] (instruction format RR) or const9. (instruction format RC). Put the result in D[c][0]. All other bits in D[c] are unchanged.
Page 445 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set XOR.T Bit Logical XOR Description Compute the logical XOR of bit pos1 of data register D[a] and bit pos2 of data register D[b]. Put the result in the least-significant bit of data register D[c] and clear the remaining bits of D[c] to zero. XOR.TD[c], D[a], pos1, D[b], pos2 (BIT) 28 27 23 22...
Page 446 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FPU Instructions Each page for this group of instructions is laid out as follows: Key: 1) Instruction Mnemonic 2) Instruction Longname 3) Description 4) Syntax, followed by Instruction Format in parentheses 5) Opcodes 6) Operation (RTL format)
Page 447 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ADD.F Add Float Description Add the contents of data register D[a] to the contents of data register D[d]. Put the result in data register D[c]. The operands and result are single precision IEEE-754-1985 floating-point numbers. If either operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC00000 ADD.FD[c], D[d], D[a] (RRR) 28 27...
Page 448 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set CMP.F Compare Float Description This instruction compares the IEEE-754-1985 single-precision floating-point operands and asserts bits in the result if their associated condition is true: bit [0] D[a] < D[b] bit [1] D[a] == D[b] bit [2] D[a] >...
Page 449 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set DIV.F Divide Float Description Divides the contents of data register D[a] by the contents of data register D[b] and put the result in data register D[c]. The operands and result are single-precision IEEE-754-1985 floating-point numbers. If either operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC00000 DIV.FD[c], D[a], D[b] (RR) 28 27...
Page 450 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOI Float to Integer Description Converts the contents of data register D[a] from floating-point format to a 32-bit two’s complement signed integer format. The rounded result is put in data register D[c]. The rounding mode used for the conversion is defined by the PSW.RM field.
Page 451 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOIZ Float to Integer, Round towards Zero Description Converts the contents of data register D[a] from floating-point format to a 32-bit two’s complement signed integer format. The result is rounded towards zero and put in data register D[c]. FTOIZD[c], D[a] (RR) 28 27 20 19...
Page 452 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOQ31 Float to Fraction Description Subtracts D[b] from the exponent of the floating-point input value D[a] and converts the result to the Q31fraction format. The result is stored in D[c]. The rounding mode used for the conversion is defined by the PSW.RM field. The exponent adjustment is a 9-bit two’s complement number taken from D[b][8:0], with a value of [-256, 255].
Page 453 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOQ31Z Float to Fraction, Round towards Zero Description Subtracts D[b] from the exponent of the floating-point input value D[a] and converts the result to the Q31fraction format. The result is rounded towards zero and stored in D[c]. The exponent adjustment is a 9-bit two’s complement number taken from D[b][8:0], with a value of [-256, 255].
Page 454 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOU Float to Unsigned Description Converts the contents of data register D[a] from floating-point format to a 32-bit unsigned integer format. The rounded result is put in data register D[c]. FTOUD[c], D[a] (RR) 28 27 20 19...
Page 455 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set FTOUZ Float to Unsigned, Round towards Zero Description Converts the contents of data register D[a] from floating-point format to a 32-bit unsigned integer format. The result is rounded towards zero and put in data register D[c]. FTOUZD[c], D[a] (RR) 28 27 20 19...
Page 456 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set ITOF Integer to Float Description Converts the contents of data register D[a] from 32-bit two’s complement signed integer format to floating-point format. The rounded result is put in data register D[c]. ITOFD[c], D[a] (RR) 28 27 20 19...
Page 457 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MADD.F Multiply Add Float Description Multiplies D[a] and D[b] and adds the product to D[d]. The result is put in D[c]. The operands and result are floating- point numbers. If an operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC00000 MADD.FD[c], D[d], D[a], D[b] (RRR) 28 27 24 23...
Page 458 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if(precise_result != f_real(result)) then set_FX = 1 else set_FX = 0; if(set_FX AND !set_FI) then PSW.FX = 1; Examples madd.f d4, d3, d1, d2 See Also MSUB.F, User Manual (Volume 2) 3-411 V1.0 2013-07...
Page 459 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MSUB.F Multiply Subtract Float Description Multiplies D[a] and D[b] and subtracts the product from D[d], putting the result in D[c]. The operands and result are floating-point numbers. If any operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC0 0000 MSUB.FD[c], D[d], D[a], D[b] (RRR) 28 27...
Page 460 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set if(precise_result != f_real(result)) then set_FX = 1 else set_FX = 0; if(set_FX AND !set_FI) then PSW.FX = 1; Examples msub.f d4, d3, d1, d2 See Also MADD.F User Manual (Volume 2) 3-413 V1.0 2013-07...
Page 461 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set MUL.F Multiply Float Description Multiplies D[a] and D[b] and stores the result in D[c]. The operands and result are floating-point numbers. If an operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC00000 MUL.FD[c], D[a], D[b] (RR) 28 27 20 19...
Page 462 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set Q31TOF Fraction to Floating-point Description Converts the D[a] from Q31 fraction format to floating-point format, then adds D[b] to the exponent and stores the resulting value in D[c]. The exponent adjustment is a 9-bit two’s complement number taken from D[b][8:0], with a value in the range [-256, 255].
Page 463 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set QSEED.F Inverse Square Root Seed Description An approximation of the reciprocal of the square root of D[a] is stored in D[c]. The accuracy of the result is no less than 6.75 bits, and therefore always within ±1% of the accurate result.
Page 464 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set SUB.F Subtract Float Description Subtracts D[a] from D[d] and stores the result in D[c]. The operands and result are floating-point numbers. If any operand is a NaN (quiet or signalling), then the return result will be the quiet NaN 7FC00000 SUB.FD[c], D[d], D[a] (RRR) 28 27 24 23...
Page 465 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set UPDFL Update Flags Description The UPDFL instruction takes two 8-bit data fields from D[a], and uses them to update the PSW user flag bits (PSW [31:24]) that the FPU uses to store its exception flags and rounding mode in. D[a][15:8] are the update mask field; a ‘1’...
Page 466 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set UTOF Unsigned to Floating-point Description Converts the contents of data register D[a] from 32-bit unsigned integer format to floating-point format. The rounded result is stored in D[c]. UTOFD[c], D[a] (RR) 28 27 20 19 18 17...
Page 467: Ls And Ip Instruction Summary Lists
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set LS and IP Instruction Summary Lists This section contains two lists; one of the LS instructions and one of the IP instructions. 3.3.1 List of LS Instructions • - Add Address ADD.A •...
Page 468: List Of Ip Instructions
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Load Word LD.W • - Load Lower Context LDLCX • - Load-Modify-Store LDMST • - Load Upper Context LDUCX • - Load Effective Address • - Loop LOOP •...
Page 469 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Absolute Value of Difference Packed Half-word with Saturation ABSDIFS.H • - Absolute Value with Saturation ABSS • - Absolute Value Packed Half-word with Saturation ABSS.H • - Add •...
Page 470 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Divide-Initialization Half-word DVINIT.H • - Divide-Initialization Half-word Unsigned DVINIT.HU • - Divide-Step DVSTEP • - Divide-Step Unsigned DVSTEP.U • - Equal • - Equal Packed Byte EQ.B •...
Page 471 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Multiply-Add Q Format, Saturated MADDS.Q • - Multiply-Add Unsigned MADD.U • - Multiply-Add Unsigned, Saturated MADDS.U • - Packed Multiply-Add Q Format Multi-precision MADDM.H • - Packed Multiply-Add Q Format Multi-precision, Saturated MADDMS.H •...
Page 472 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Multiply, Saturated MULS • - Packed Multiply Q Format MUL.H • - Multiply Q Format MUL.Q • - Multiply Unsigned MUL.U • - Multiply Unsigned, Saturated MULS.U •...
Page 473 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Instruction Set • - Accumulating Shift-NAND SH.NAND.T • - Accumulating Shift-NOR SH.NOR.T • - Accumulating Shift-OR SH.OR.T • - Accumulating Shift-OR-Not SH.ORN.T • - Accumulating Shift-XNOR SH.XNOR.T • - Accumulating Shift-XOR SH.XOR.T •...
Page 474: List Of Instructions By Shortname
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Shortname List of Instructions by Shortname CALLI ABS.B CLO.H ABS.H ABSDIF CLS.H ABSDIF.B ABSDIF.H CLZ.H ABSDIFS CMOV (16-bit) ABSDIFS.H CMOVN (16-bit) ABSS CMP.F ABSS.H CMPSWAP.W ADD.A CRC32 ADD.B CSUB ADD.F...
Page 475 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Shortname GE.A LT.A GE.U LT.B IMASK LT.BU INS.T LT.H INSERT LT.HU INSN.T LT.U ISYNC LT.W ITOF LT.WU IXMAX MADD IXMAX.U MADD.F IXMIN MADD.H IXMIN.U MADD.Q MADD.U MADDM.H MADDMS.H JEQ.A MADDR.H...
Page 476 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Shortname MSUBAD.H QSEED.F MSUBADM.H RESTORE MSUBADMS.H MSUBADR.H MSUBADRS.H MSUBADS.H RSLCX MSUBM.H RSTV MSUBMS.H RSUB MSUBR.H RSUBS MSUBR.Q RSUBS.U MSUBRS.H SAT.B MSUBRS.Q SAT.BU MSUBS SAT.H MSUBS.H SAT.HU MSUBS.Q MSUBS.U SELN MTCR...
Page 477 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Shortname SUBS.U UTOF SUBX WAIT SVLCX XNOR SWAP.W XNOR.T SWAPMSK.W SYSCALL XOR.EQ TLBDEMAP XOR.GE TLBFLUSH.A XOR.GE.U TLBFLUSH.B XOR.LT TLBMAP XOR.LT.U TLBPROBE.A XOR.NE TLBPROBE.I XOR.T TRAPSV XPOSE.B TRAPV XPOSE.H UNPACK YIELD...
Page 478: List Of Instructions By Longname
® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Longname List of Instructions by Longname Absolute Value Bit Logical AND Absolute Value of Difference Bit Logical AND-Not Absolute Value of Difference Packed Byte Bit Logical NAND Absolute Value of Difference Packed Half-word 6 Bit Logical NOR Absolute Value of Difference Packed Half-word...
Page 479 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Longname Divide-Adjust Insert Bit Field Divide-Initialization Byte Insert Bit-Not Divide-Initialization Byte Unsigned Insert Mask Divide-Initialization Half-word Integer to Float Divide-Initialization Half-word Unsigned Inverse Square Root Seed Divide-Initialization Word Jump and Link Divide-Initialization Word Unsigned Jump and Link Absolute...
Page 480 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Longname Load Double-word to Address Register Multiply-Add Q Format, Saturated Load Effective Address Multiply-Add Unsigned Load Half-word Multiply-Add Unsigned, Saturated Load Half-word Signed Fraction Multiply-Add, Saturated Load Half-word Unsigned Multiply-Subtract Load Lower Context Multiply-Subtract Q Format...
Page 481 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core List of Instructions by Longname Store Byte Packed Multiply-Subtract Q Format-Multi-preci- Store Double Double (TriCore 2) sion Store Double-word Packed Multiply-Subtract Q Format-Multi-preci- Store Double-word from Address Registers 360 sion, Saturated Store Half-word Packed Multiply-Subtract/Add Q Format Store Half-word Signed Fraction...
Page 482 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Memory 22 Absolute Types Value 2 Load and Store 19 Address DEXTR Instruction Comparison 15 Operation 5 Register Double-word Address Arithmetic 15 Definition 2 Conditional Jump 17 DYSNC Arithmetic Synchronization Primitives DSP Instructions 8 Description 22 Instructions 8...
Page 483 ® TriCore TC1.6P & TC1.6E 32-bit Unified Processor Core Reading Status Flags 8 Return From Exception (RFE) Instruction Overview 24 Definition 2 Rounding Minimum (MIN) Instructions 2 Instruction Set Overview 9 Move (MOV) RSTV Instruction Instruction Set Overview 1 PSW Status Flags 8 MTCR Instruction Use of 23 Access to CSFRs 23...
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