Infineon TRAVEO T2G Cluster 4M Lite Kit User Manual page 28

TRAVEO™ T2G Cluster 4M Lite Kit user guide
KIT_T2G_C-2D-4M_LITE
Hardware blocks
Figure 25 SEMPER™ Flash and HYPERRAM™ location
3.6.1 SEMPER™ Flash
The TRAVEO™ T2G Cluster 4M Lite kit has the S26HL512T 512 Mb SEMPER™ Flash, which is a high-speed CMOS,
MIRRORBIT™ NOR Flash device compliant with the JEDEC JESD251 eXpanded SPI (xSPI) specification. SEMPER™
Flash is designed for functional safety with development according to the ISO 26262 standard to achieve ASIL-B
compliance and ASIL-D readiness.
SEMPER™ Flash with HYPERBUS™ interface devices support both the HYPERBUS™ interface as well as legacy (x1)
SPI. Both interfaces serially transfer transactions reducing the number of interface connection signals.
3.6.2 HYPERRAM™
This kit has S27KL0642 64-Mb HYPERRAM™ self-refresh DRAM (PSRAM). The Infineon 64-Mb HYPERRAM™ device is
a high-speed CMOS, self-refresh DRAM, with HYPERBUS™ interface. The DRAM array uses dynamic cells that
require periodic refresh.
The refresh control logic within the device manages the refresh operations on the DRAM array when the memory
is not actively read or written by the HYPERBUS™ interface master (host). Since the host is not required to manage
any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain
data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM (PSRAM).
Note: For datasheet and more details about SEMPER™ Flash and HYPERRAM™, refer to the
at the end of the document.
User guide 28
References section
002-39200 Rev. **
2023-12-11