Infineon C513AO Manuals

Manuals and User Guides for Infineon C513AO. We have 1 Infineon C513AO manual available for free PDF download: User Manual

Infineon C513AO User Manual

Infineon C513AO User Manual (147 pages)

8-bit CMOS Microcontroller

Brand: Infineon | Category: Microcontrollers | Size: 1.29 MB

Table of Contents

Table of Contents
4
1 Introduction

7
- Pin Configurations
  10
- Pin Definitions and Functions
  13
2 Fundamental Structure

18
- Central Processing Unit (CPU)
  19
- CPU Timing
  21
3 Memory Organization

23
4 External Bus Interface

32
- Accessing External Memory
  32
- Role of P0 and P2 as Data/Address Bus
  32
- Timing
  34
- External Program Memory Access
  34
- PSEN, Program Store Enable
  34
- Overlapping External Data and Program Memory Spaces
  34
- Address Latch Enable (ALE)
  35
- Enhanced Hooks Emulation Concept
  36
- ROM/OTP Protection
  37
- Unprotected ROM Mode
  37
- Protected ROM/OTP Mode
  38
5 Reset and System Clock Operation

40
6 On-Chip Peripheral Components

47
- Parallel I/O
  47
- Port Structures
  47
- Port 0 and Port 2 Used as Address/Data Bus
  54
- Alternate Functions
  55
- Port Timing
  58
- Port Loading and Interfacing
  59
- Read-Modify-Write Feature of Ports 2 and 3
  60
- Timers/Counters
  61
- Timer/Counter 0 and 1
  61
- Timer/Counter 0 and 1 Registers
  62
- Mode 0
  65
- Timer/Counter
  69
- Timer/Counter 2 Registers
  70
- Auto-Reload (up or down Counter)
  72
- Capture Mode
  75
- Serial Interface (USART)
  76
- Multiprocessor Communications
  77
- Serial Port Registers
  77
- Baudrates
  79
- Using Timer 1 to Generate Baudrates
  81
- Using Timer 2 to Generate Baudrates
  82
- Details about Mode 0
  83
- Details about Mode 1
  86
- Details about Modes 2 and 3
  89
- SSC Interface
  92
- General Operation of the SSC
  93
- Enable/Disable Control
  93
- Baudrate Generation (Master Mode Only)
  94
- Write Collision Detection
  94
- Master/Slave Mode Selection
  95
- Data/Clock Timing Relationships
  96
- Master Mode Operation
  96
- Slave Mode Operation
  97
- Register Description
  98
7 Interrupt System

102
- Interrupt Structure
  104
- Interrupt Registers
  105
- Interrupt Enable Registers
  105
- Interrupt Request Flags
  106
- Interrupt Priority Registers
  111
- Interrupt Handling
  113
- External Interrupts
  114
- Interrupt Response Time
  115
8 Fail Safe Mechanisms

116
9 Power Saving Modes

123
- Idle Mode
  125
- Slow-Down Mode Operation
  127
- Power-Down Mode
  128
- Invoking Power-Down Mode
  128
- Exit from Power-Down Mode
  129
10 OTP Memory Operation

131
- Programming Configuration
  131
- Pin Configuration
  132
- OTP Programming Mode - Pin Definitions
  135
- OTP Programming Mode Selection
  137
- Basic Programming Mode Selection
  137
- OTP Memory Access Mode Selection
  138
- Program/Read OTP Memory Bytes
  139
- Lock Bits Programming / Read
  141
- Access of Version Bytes
  143

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