Page 1 Intended audience This manual is for system designer and programmers who are designing or programming using TVII-B-E-4M parts. Technical reference manual Please read the Important Notice and Warnings at the end of this document 002-29852 Rev. *B www.infineon.com 2022-04-18...
Page 2 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Definitions Register Permission The following table lists the register permission based on protection context and priviledges. Permission Description READ User mode = Read access, privilege mode = Read access, Non- secure = yes PRIVILEGE - WRITE User mode = Read access, privilege mode = Read and Write access, Non-secure = yes...
Page 3 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Software Access The following table lists the behavior of registers, on various Software Read/Write Accesses. Software Reads Software Writes Software Description Access Access Register Register Register contents Ignored Software read-only Register contents Register takes data Software read and write written...
Page 4 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Hardware Access The following table lists the behavior of registers, on various Hardware Read/Write Accesses. Hardware Description Access Access Hardware read only Hardware read and write RW1S Hardware read and set RW0S Hardware read and set RW1C...
Page 5 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Core, Bus and Memory Access The Cortex-M4 CPUSS uses AHB-Lite also for the system interconnect. Most of the IPs are compliant to the AHB- Lite protocol. The AHB-Lite protocol is little endian; the least significant byte of a word is mapped onto the word's lowest byte address IPs use a bus data width of 32 bit.
Page 6 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers List of Partnumber This TRM is valid for the following part numbers. Package Code Flash(KB) Work Flash(KB) SRAM(KB) CYT2BL3BAS 64-LQFP 4160 CYT2BL3BAE 64-LQFP 4160 CYT2BL3CAS 64-LQFP 4160 CYT2BL3CAE 64-LQFP 4160 CYT2BL4BAS 80-LQFP 4160 CYT2BL4BAE...
Page 7 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Memory mapping MMIO Address Description MMIO0 PERI 0x40000000 Peripheral interconnect PERI_MS 0x40010000 Peripheral interconnect, master interface MMIO1 CRYPTO 0x40100000 Cryptography component MMIO2 CPUSS 0x40200000 CPU subsystem (CPUSS) FAULT 0x40210000 Fault structures 0x40220000 PROT 0x40230000...
Page 8: Table Of Contents
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1 BACKUP Description SRSS Backup Domain (ver3) Base Address 0x40270000 Size 0x10000 Slave Num MMIO2 - 6 Register Name Address Permission Description BACKUP_CTL 0x40270000 FULL Control Note:VDDBAK_CTL VBACKUP_MEAS EN_CHARGE_KEY are not available for this register BACKUP_RTC_RW 0x40270008 FULL RTC Read Write register...
Page 9 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1 Register Details 1.1.1 BACKUP_CTL Description: Control Address: 0x40270000 Offset: Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Default: Bit-field Table Bits Name None [7:4] WCO_EN None [2:0] [3:3] Bits Name None [15:14]...
Page 10 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 12:13 PRESCALER Prescaler for real time clock used when WCO_BYPASS=1 and CLK_SEL = WCO. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1.
Page 11: Backup_Rtc_Rw
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.2 BACKUP_RTC_RW Description: RTC Read Write register Address: 0x40270008 Offset: Retention: Not Retained IsDeepSleep: Comment: These bits are in vddbak domain but reset in DEEPSLEEP. Default: Bit-field Table Bits Name None [7:2] WRITE [1:1] READ [0:0] Bits...
Page 12 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.3 BACKUP_CAL_CTL Description: Oscillator calibration for absolute frequency Address: 0x4027000C Offset: Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Calibration only works when the PRESCALER is set to 32768. Writes are ignored unless Write bit is set Default: Bit-field Table Bits...
Page 13: Backup_Status
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.4 BACKUP_STATUS Description: Status Address: 0x40270010 Offset: 0x10 Retention: Not Retained IsDeepSleep: Comment: These bits are in vddbak domain. Default: Bit-field Table Bits Name None [7:3] WCO_OK None [1:1] RTC_BUSY [2:2] [0:0] Bits Name...
Page 14: Backup_Rtc_Time
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.5 BACKUP_RTC_TIME Description: Calendar Seconds, Minutes, Hours, Day of Week Address: 0x40270014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these will read as zero until the read bit it set and the values are copied from the RTC into these registers..
Page 15 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.6 BACKUP_RTC_DATE Description: Calendar Day of Month, Month, Year Address: 0x40270018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these will read as zero until the read bit it set and the values are copied from the RTC into these registers..
Page 16 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.7 BACKUP_ALM1_TIME Description: Alarm 1 Seconds, Minute, Hours, Day of Week Address: 0x4027001C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. This register is only used when BACKUP_ALM1_DATE.ALM_EN=1.
Page 17 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.8 BACKUP_ALM1_DATE Description: Alarm 1 Day of Month, Month Address: 0x40270020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these will read as zero until the read bit it set and the values are copied from the RTC into these registers..
Page 18 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.9 BACKUP_ALM2_TIME Description: Alarm 2 Seconds, Minute, Hours, Day of Week Address: 0x40270024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. This register is only used when BACKUP_ALM2_DATE.ALM_EN=1.
Page 19 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.10 BACKUP_ALM2_DATE Description: Alarm 2 Day of Month, Month Address: 0x40270028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these will read as zero until the read bit it set and the values are copied from the RTC into these registers..
Page 20: Backup_Intr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.11 BACKUP_INTR Description: Interrupt request register Address: 0x4027002C Offset: 0x2C Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Interrupt signal from SRSS includes this register and also BACKUP_INTR, if present. Default: Bit-field Table Bits...
Page 21: Backup_Intr_Set
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.12 BACKUP_INTR_SET Description: Interrupt set request register Address: 0x40270030 Offset: 0x30 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Allows setting interrupts for firmware testing. Default: Bit-field Table Bits Name None [7:3] CENTURY...
Page 22: Backup_Intr_Mask
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.13 BACKUP_INTR_MASK Description: Interrupt mask register Address: 0x40270034 Offset: 0x34 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. When Mask bit is set the interrupt is enabled. Default: Bit-field Table Bits Name None [7:3]...
Page 23: Backup_Intr_Masked
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.14 BACKUP_INTR_MASKED Description: Interrupt masked request register Address: 0x40270038 Offset: 0x38 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. When read, this register reflects a bitwise and between the interrupt request and mask registers.
Page 24: Backup_Reset
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.15 BACKUP_RESET Description: Backup reset register Address: 0x40270048 Offset: 0x48 Retention: Retained IsDeepSleep: Comment: This register is used to reset the backup domain from firmware. Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8]...
Page 25 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 1.1.16 BACKUP_BREG Description: Backup register region Address: 0x40271000 Offset: 0x1000 Retention: Retained IsDeepSleep: Comment: These bits are in vddbak domain. Backup memory Default: Bit-field Table Bits Name BREG [7:0] Bits Name BREG [15:8] Bits Name...
Page 26 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2 CANFD 2.1 CANFD 0 Description CAN Controller Base Address 0x40520000 Size 0x20000 Slave Num MMIO5 - 2 Register Name Address Permission Description CANFD0_CTL 0x40521000 FULL Global CAN control register CANFD0_STATUS 0x40521004 FULL Global CAN status register CANFD0_INTR0_CAUSE...
Page 27 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD0_CH0_TXFQS 0x405200C4 FULL Tx FIFO/Queue Status CANFD0_CH0_TXESC 0x405200C8 FULL Tx Buffer Element Size Configuration CANFD0_CH0_TXBRP 0x405200CC FULL Tx Buffer Request Pending CANFD0_CH0_TXBAR 0x405200D0 FULL Tx Buffer Add Request CANFD0_CH0_TXBCR 0x405200D4 FULL Tx Buffer Cancellation Request...
Page 28 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD0_CH1_NDAT1 0x40520298 FULL New Data 1 CANFD0_CH1_NDAT2 0x4052029C FULL New Data 2 CANFD0_CH1_RXF0C 0x405202A0 FULL Rx FIFO 0 Configuration CANFD0_CH1_RXF0S 0x405202A4 FULL Rx FIFO 0 Status CANFD0_CH1_RXF0A 0x405202A8 FULL Rx FIFO 0 Acknowledge...
Page 29 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD0_CH2_PSR 0x40520444 FULL Protocol Status Register CANFD0_CH2_TDCR 0x40520448 FULL Transmitter Delay Compensation Register CANFD0_CH2_IR 0x40520450 FULL Interrupt Register CANFD0_CH2_IE 0x40520454 FULL Interrupt Enable CANFD0_CH2_ILS 0x40520458 FULL Interrupt Line Select CANFD0_CH2_ILE 0x4052045C FULL...
Page 30 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD0_CH3_CREL 0x40520600 FULL Core Release Register CANFD0_CH3_ENDN 0x40520604 FULL Endian Register CANFD0_CH3_DBTP 0x4052060C FULL Data Bit Timing & Prescaler Register CANFD0_CH3_TEST 0x40520610 FULL Test Register CANFD0_CH3_RWD 0x40520614 FULL RAM Watchdog CANFD0_CH3_CCCR...
Page 31 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.2 CANFD 1 Description CAN Controller Base Address 0x40540000 Size 0x20000 Slave Num MMIO5 - 3 Register Name Address Permission Description CANFD1_CTL 0x40541000 FULL Global CAN control register CANFD1_STATUS 0x40541004 FULL Global CAN status register CANFD1_INTR0_CAUSE 0x40541010 FULL...
Page 32 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD1_CH0_TXBCR 0x405400D4 FULL Tx Buffer Cancellation Request CANFD1_CH0_TXBTO 0x405400D8 FULL Tx Buffer Transmission Occurred CANFD1_CH0_TXBCF 0x405400DC FULL Tx Buffer Cancellation Finished CANFD1_CH0_TXBTIE 0x405400E0 FULL Tx Buffer Transmission Interrupt Enable CANFD1_CH0_TXBCIE 0x405400E4 FULL Tx Buffer Cancellation Finished Interrupt Enable...
Page 33 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD1_CH1_RXF0C 0x405402A0 FULL Rx FIFO 0 Configuration CANFD1_CH1_RXF0S 0x405402A4 FULL Rx FIFO 0 Status CANFD1_CH1_RXF0A 0x405402A8 FULL Rx FIFO 0 Acknowledge CANFD1_CH1_RXBC 0x405402AC FULL Rx Buffer Configuration CANFD1_CH1_RXF1C 0x405402B0 FULL Rx FIFO 1 Configuration...
Page 34 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD1_CH2_IR 0x40540450 FULL Interrupt Register CANFD1_CH2_IE 0x40540454 FULL Interrupt Enable CANFD1_CH2_ILS 0x40540458 FULL Interrupt Line Select CANFD1_CH2_ILE 0x4054045C FULL Interrupt Line Enable CANFD1_CH2_GFC 0x40540480 FULL Global Filter Configuration CANFD1_CH2_SIDFC 0x40540484 FULL Standard ID Filter Configuration...
Page 35 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CANFD1_CH3_ENDN 0x40540604 FULL Endian Register CANFD1_CH3_DBTP 0x4054060C FULL Data Bit Timing & Prescaler Register CANFD1_CH3_TEST 0x40540610 FULL Test Register CANFD1_CH3_RWD 0x40540614 FULL RAM Watchdog CANFD1_CH3_CCCR 0x40540618 FULL CC Control Register CANFD1_CH3_NBTP 0x4054061C FULL...
Page 36 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3 Register Details 2.3.1 CANFD_CTL Description: Global CAN control register Address: 0x40521000 Offset: 0x1000 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name STOP_REQ [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 37 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.2 CANFD_STATUS Description: Global CAN status register Address: 0x40521004 Offset: 0x1004 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name STOP_ACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 38 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.3 CANFD_INTR0_CAUSE Description: Consolidated interrupt0 cause register Address: 0x40521010 Offset: 0x1010 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT0 [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 39 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.4 CANFD_INTR1_CAUSE Description: Consolidated interrupt1 cause register Address: 0x40521014 Offset: 0x1014 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT1 [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 40: Canfd0_Ts_Ctl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.5 CANFD_TS_CTL Description: Time Stamp control register Address: 0x40521020 Offset: 0x1020 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name PRESCALE [7:0] Bits Name PRESCALE [15:8] Bits Name None [23:16] Bits Name ENABLED None [30:24]...
Page 41: Canfd0_Ts_Cnt
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.6 CANFD_TS_CNT Description: Time Stamp counter value Address: 0x40521024 Offset: 0x1024 Retention: Not Retained IsDeepSleep: Comment: Not retained Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name None [23:16] Bits Name...
Page 42 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.7 CANFD_ECC_CTL Description: ECC control Address: 0x40521080 Offset: 0x1080 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:17] ECC_EN [16:16] Bits Name None [31:24] Bit-fields...
Page 43: Canfd0_Ecc_Err_Inj
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.8 CANFD_ECC_ERR_INJ Description: ECC error injection Address: 0x40521084 Offset: 0x1084 Retention: Retained IsDeepSleep: Comment: Default: 0xFFFC Bit-field Table Bits Name None [1:0] Bits Name ERR_ADDR [15:8] Bits Name None [23:21] ERR_EN None [19:16] [20:20] Bits...
Page 44: Canfd0_Ch0_Rxftop_Ctl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9 CH 2.3.9.1 CANFD_CH_RXFTOP_CTL Description: Receive FIFO Top control Address: 0x40520180 Offset: 0x180 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] F1TPE [1:1] F0TPE [0:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 45: Canfd0_Ch0_Rxftop0_Stat
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.2 CANFD_CH_RXFTOP0_STAT Description: Receive FIFO 0 Top Status Address: 0x405201A0 Offset: 0x1A0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name F0TA [7:0] Bits Name F0TA [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 46: Canfd0_Ch0_Rxftop0_Data
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.3 CANFD_CH_RXFTOP0_DATA Description: Receive FIFO 0 Top Data Address: 0x405201A8 Offset: 0x1A8 Retention: Retained IsDeepSleep: Comment: Read side effect, except if read from debug host Default: Bit-field Table Bits Name F0TD [7:0] Bits Name F0TD [15:8]...
Page 47: Canfd0_Ch0_Rxftop1_Stat
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.4 CANFD_CH_RXFTOP1_STAT Description: Receive FIFO 1 Top Status Address: 0x405201B0 Offset: 0x1B0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name F1TA [7:0] Bits Name F1TA [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 48: Canfd0_Ch0_Rxftop1_Data
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.5 CANFD_CH_RXFTOP1_DATA Description: Receive FIFO 1 Top Data Address: 0x405201B8 Offset: 0x1B8 Retention: Retained IsDeepSleep: Comment: Read side effect, except if read from debug host Default: Bit-field Table Bits Name F1TD [7:0] Bits Name F1TD [15:8]...
Page 49: M_Ttcan
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6 M_TTCAN 2.3.9.6.1 CANFD_CH_CREL Description: Core Release Register Address: 0x40520000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DAY [7:0] Bits Name MON [15:8] Bits Name SUBSTEP [23:20] YEAR [19:16] Bits Name REL [31:28]...
Page 50 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.2 CANFD_CH_ENDN Description: Endian Register Address: 0x40520004 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0x87654321 Bit-field Table Bits Name ETV [7:0] Bits Name ETV [15:8] Bits Name ETV [23:16] Bits Name ETV [31:24] Bit-fields Bits Name Default or...
Page 51 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.3 CANFD_CH_DBTP Description: Data Bit Timing & Prescaler Register Address: 0x4052000C Offset: Retention: Retained IsDeepSleep: Comment: Protected Write Default: 0xA33 Bit-field Table Bits Name DTSEG2 [7:4] DSJW [3:0] Bits Name None [15:13] DTSEG1 [12:8] Bits Name...
Page 52 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.4 CANFD_CH_TEST Description: Test Register Address: 0x40520010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Protected Write Default: Bit-field Table Bits Name RX [7:7] TX [6:5] LBCK [4:4] CAT [3:3] CAM [2:2] TAT [1:1] TAM [0:0] Bits Name...
Page 53: Canfd0_Ch0_Rwd
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.5 CANFD_CH_RWD Description: RAM Watchdog Address: 0x40520014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Protected Write Default: Bit-field Table Bits Name WDC [7:0] Bits Name WDV [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 54: Canfd0_Ch0_Cccr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.6 CANFD_CH_CCCR Description: CC Control Register Address: 0x40520018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: Protected Write Default: Bit-field Table Bits Name TEST [7:7] DAR [6:6] MON_ [5:5] CSR [4:4] CSA [3:3] ASM [2:2] CCE [1:1] INIT [0:0]...
Page 55 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled FDOE FD Operation Enable...
Page 56 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.7 CANFD_CH_NBTP Description: Nominal Bit Timing & Prescaler Register Address: 0x4052001C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: Protected Write. With a CAN clock (m_can_cclk) of 8 MHz, the reset value of 0x06000A03 configures the M_CAN for a bit rate of 500 Kbit/s.
Page 57: Canfd0_Ch0_Tscc
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.8 CANFD_CH_TSCC Description: Timestamp Counter Configuration Address: 0x40520020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [7:2] TSS [1:0] Bits Name None [15:8] Bits Name None [23:20] TCP [19:16] Bits...
Page 58: Canfd0_Ch0_Tscv
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.9 CANFD_CH_TSCV Description: Timestamp Counter Value Address: 0x40520024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TSC [7:0] Bits Name TSC [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name...
Page 59: Canfd0_Ch0_Tocc
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.10 CANFD_CH_TOCC Description: Timeout Counter Configuration Address: 0x40520028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: 0xFFFF0000 Bit-field Table Bits Name None [7:3] TOS [2:1] ETOC [0:0] Bits Name None [15:8] Bits Name TOP [23:16]...
Page 60: Canfd0_Ch0_Tocv
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.11 CANFD_CH_TOCV Description: Timeout Counter Value Address: 0x4052002C Offset: 0x2C Retention: Retained IsDeepSleep: Comment: Default: 0xFFFF Bit-field Table Bits Name TOC [7:0] Bits Name TOC [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 61 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.12 CANFD_CH_ECR Description: Error Counter Register Address: 0x40520040 Offset: 0x40 Retention: Retained IsDeepSleep: Comment: Read side effect, except if read from debug host Default: Bit-field Table Bits Name TEC [7:0] Bits Name RP [15:15] REC [14:8]...
Page 62: Canfd0_Ch0_Psr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.13 CANFD_CH_PSR Description: Protocol Status Register Address: 0x40520044 Offset: 0x44 Retention: Retained IsDeepSleep: Comment: Read side effect, except if read from debug host Default: 0x707 Bit-field Table Bits Name BO [7:7] EW [6:6] EP [5:5] ACT [4:3]...
Page 63 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RW1S Last Error Code, Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
Page 64 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 8:10 DLEC RW1S Data Phase Last Error Code , Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC.
Page 65 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.14 CANFD_CH_TDCR Description: Transmitter Delay Compensation Register Address: 0x40520048 Offset: 0x48 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [7:7] TDCF [6:0] Bits Name None TDCO [14:8] [15:15] Bits Name...
Page 66 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.15 CANFD_CH_IR Description: Interrupt Register Address: 0x40520050 Offset: 0x50 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name RF1L_ [7:7] RF1F [6:6] RF1W [5:5] RF1N [4:4] RF0L_ [3:3] RF0F [2:2] RF0W [1:1] RF0N [0:0] Bits Name...
Page 67 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RW1C Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished RW1C Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty TEFN RW1C Tx Event FIFO New Entry...
Page 68 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RW1C Bit Error Uncorrected Message RAM bit error detected, uncorrected. The flag is set in the folloiwng cases. - M_TTCAN detects uncorrectable ECC error from Message RAM when ECC is enabled and ECC error injection is disabled.
Page 69 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.16 CANFD_CH_IE Description: Interrupt Enable Address: 0x40520054 Offset: 0x54 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name RF1LE [7:7] RF1FE [6:6] RF1WE RF1NE RF0LE [3:3] RF0FE [2:2] RF0WE RF0NE [5:5] [4:4] [1:1] [0:0]...
Page 70 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TCFE Transmission Cancellation Finished Interrupt Enable 0= Interrupt Disabled 1= Interrupt Enabled TFEE Tx FIFO Empty Interrupt Enable 0= Interrupt Disabled 1= Interrupt EnabledTx FIFO Empty Interrupt Enable TEFNE Tx Event FIDO New Entry Interrupt Enable 0= Interrupt Disabled...
Page 71 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum ARAE Access to Reserved Address Enable 0= Interrupt Disabled 1= Interrupt Enabled Technical Reference Manual 002-29852 Rev. *B 2022-04-18...
Page 72 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.17 CANFD_CH_ILS Description: Interrupt Line Select Address: 0x40520058 Offset: 0x58 Retention: Retained IsDeepSleep: Comment: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.
Page 73 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Transmission Completed Interrupt Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 TCFL Transmission Cancellation Finished Interrupt Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 TFEL Tx FIFO Empty Interrupt Select...
Page 74 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum PEDL Protocol Error in Data Phase Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 ARAL Access to Reserved Address Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 Technical Reference Manual...
Page 75 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.18 CANFD_CH_ILE Description: Interrupt Line Enable Address: 0x4052005C Offset: 0x5C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] EINT1 [1:1] EINT0 [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 76 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.19 CANFD_CH_GFC Description: Global Filter Configuration Address: 0x40520080 Offset: 0x80 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [7:6] ANFS [5:4] ANFE [3:2] RRFS [1:1] RRFE [0:0] Bits Name None [15:8]...
Page 77 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.20 CANFD_CH_SIDFC Description: Standard ID Filter Configuration Address: 0x40520084 Offset: 0x84 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name FLSSA [15:8] Bits Name LSS [23:16] Bits Name None [31:24]...
Page 78 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.21 CANFD_CH_XIDFC Description: Extended ID Filter Configuration Address: 0x40520088 Offset: 0x88 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name FLESA [15:8] Bits Name None LSE [22:16] [23:23] Bits...
Page 79 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.22 CANFD_CH_XIDAM Description: Extended ID AND Mask Address: 0x40520090 Offset: 0x90 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: 0x1FFFFFFF Bit-field Table Bits Name EIDM [7:0] Bits Name EIDM [15:8] Bits Name EIDM [23:16] Bits Name...
Page 80 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.23 CANFD_CH_HPMS Description: High Priority Message Status Address: 0x40520094 Offset: 0x94 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name MSI [7:6] BIDX [5:0] Bits Name FLST FIDX [14:8] [15:15] Bits Name None [23:16] Bits...
Page 81 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.24 CANFD_CH_NDAT1 Description: New Data 1 Address: 0x40520098 Offset: 0x98 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ND [7:0] Bits Name ND [15:8] Bits Name ND [23:16] Bits Name ND [31:24] Bit-fields Bits Name...
Page 82 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.25 CANFD_CH_NDAT2 Description: New Data 2 Address: 0x4052009C Offset: 0x9C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ND [7:0] Bits Name ND [15:8] Bits Name ND [23:16] Bits Name ND [31:24] Bit-fields Bits Name...
Page 83 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.26 CANFD_CH_RXF0C Description: Rx FIFO 0 Configuration Address: 0x405200A0 Offset: 0xA0 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name F0SA [15:8] Bits Name None F0S [22:16] [23:23] Bits...
Page 84 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.27 CANFD_CH_RXF0S Description: Rx FIFO 0 Status Address: 0x405200A4 Offset: 0xA4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:7] F0FL [6:0] Bits Name None [15:14] F0GI [13:8] Bits Name None [23:22] F0PI [21:16]...
Page 85 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.28 CANFD_CH_RXF0A Description: Rx FIFO 0 Acknowledge Address: 0x405200A8 Offset: 0xA8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] F0AI [5:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 86 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.29 CANFD_CH_RXBC Description: Rx Buffer Configuration Address: 0x405200AC Offset: 0xAC Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name RBSA [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 87 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.30 CANFD_CH_RXF1C Description: Rx FIFO 1 Configuration Address: 0x405200B0 Offset: 0xB0 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name F1SA [15:8] Bits Name None F1S [22:16] [23:23] Bits...
Page 88 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.31 CANFD_CH_RXF1S Description: Rx FIFO 1 Status Address: 0x405200B4 Offset: 0xB4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:7] F1FL [6:0] Bits Name None [15:14] F1GI [13:8] Bits Name None [23:22] F1PI [21:16]...
Page 89 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.32 CANFD_CH_RXF1A Description: Rx FIFO 1 Acknowledge Address: 0x405200B8 Offset: 0xB8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] F1AI [5:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 90 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.33 CANFD_CH_RXESC Description: Rx Buffer / FIFO Element Size Configuration Address: 0x405200BC Offset: 0xBC Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [7:7] F1DS [6:4] None [3:3] F0DS [2:0] Bits Name...
Page 91 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.34 CANFD_CH_TXBC Description: Tx Buffer Configuration Address: 0x405200C0 Offset: 0xC0 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name TBSA [15:8] Bits Name None [23:22] NDTB [21:16] Bits Name...
Page 92 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.35 CANFD_CH_TXFQS Description: Tx FIFO/Queue Status Address: 0x405200C4 Offset: 0xC4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] TFFL [5:0] Bits Name None [15:13] TFGI [12:8] Bits Name None [23:22] TFQF TFQPI [20:16]...
Page 93 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.36 CANFD_CH_TXESC Description: Tx Buffer Element Size Configuration Address: 0x405200C8 Offset: 0xC8 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [7:3] TBDS [2:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 94 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.37 CANFD_CH_TXBRP Description: Tx Buffer Request Pending Address: 0x405200CC Offset: 0xCC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TRP [7:0] Bits Name TRP [15:8] Bits Name TRP [23:16] Bits Name TRP [31:24] Bit-fields...
Page 95 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.38 CANFD_CH_TXBAR Description: Tx Buffer Add Request Address: 0x405200D0 Offset: 0xD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name AR [7:0] Bits Name AR [15:8] Bits Name AR [23:16] Bits Name AR [31:24] Bit-fields...
Page 96 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.39 CANFD_CH_TXBCR Description: Tx Buffer Cancellation Request Address: 0x405200D4 Offset: 0xD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name CR [7:0] Bits Name CR [15:8] Bits Name CR [23:16] Bits Name CR [31:24] Bit-fields...
Page 97 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.40 CANFD_CH_TXBTO Description: Tx Buffer Transmission Occurred Address: 0x405200D8 Offset: 0xD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TO [7:0] Bits Name TO [15:8] Bits Name TO [23:16] Bits Name TO [31:24] Bit-fields...
Page 98 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.41 CANFD_CH_TXBCF Description: Tx Buffer Cancellation Finished Address: 0x405200DC Offset: 0xDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name CF [7:0] Bits Name CF [15:8] Bits Name CF [23:16] Bits Name CF [31:24] Bit-fields...
Page 99 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.42 CANFD_CH_TXBTIE Description: Tx Buffer Transmission Interrupt Enable Address: 0x405200E0 Offset: 0xE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TIE [7:0] Bits Name TIE [15:8] Bits Name TIE [23:16] Bits Name TIE [31:24]...
Page 100 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.43 CANFD_CH_TXBCIE Description: Tx Buffer Cancellation Finished Interrupt Enable Address: 0x405200E4 Offset: 0xE4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name CFIE [7:0] Bits Name CFIE [15:8] Bits Name CFIE [23:16] Bits Name CFIE [31:24]...
Page 101 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.44 CANFD_CH_TXEFC Description: Tx Event FIFO Configuration Address: 0x405200F0 Offset: 0xF0 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name EFSA [15:8] Bits Name None [23:22] EFS [21:16] Bits Name...
Page 102 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.45 CANFD_CH_TXEFS Description: Tx Event FIFO Status Address: 0x405200F4 Offset: 0xF4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] EFFL [5:0] Bits Name None [15:13] EFGI [12:8] Bits Name None [23:21] EFPI [20:16]...
Page 103 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.46 CANFD_CH_TXEFA Description: Tx Event FIFO Acknowledge Address: 0x405200F8 Offset: 0xF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:5] EFAI [4:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 104 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.47 CANFD_CH_TTTMC Description: TT Trigger Memory Configuration Address: 0x40520100 Offset: 0x100 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name None [1:0] Bits Name TMSA [15:8] Bits Name None TME [22:16] [23:23] Bits...
Page 105 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.48 CANFD_CH_TTRMC Description: TT Reference Message Configuration Address: 0x40520104 Offset: 0x104 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name RID [7:0] Bits Name RID [15:8] Bits Name RID [23:16] Bits Name RMPS...
Page 106 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.49 CANFD_CH_TTOCF Description: TT Operation Configuration Address: 0x40520108 Offset: 0x108 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: 0x10000 Bit-field Table Bits Name LDSDL [7:5] TM [4:4] GEN [3:3] None [2:2] OM [1:0] Bits Name EECS...
Page 107 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 16:23 AWL Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00. 0x00-FF Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs.
Page 108 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.50 CANFD_CH_TTMLM Description: TT Matrix Limits Address: 0x4052010C Offset: 0x10C Retention: Retained IsDeepSleep: Comment: Protected Write. Default: Bit-field Table Bits Name CSS [7:6] CCM [5:0] Bits Name None [15:12] TXEW [11:8] Bits Name ENTT [23:16]...
Page 109 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.51 CANFD_CH_TURCF Description: TUR Configuration Address: 0x40520110 Offset: 0x110 Retention: Retained IsDeepSleep: Comment: Protected Write. Default: 0x10000000 Bit-field Table Bits Name NCL [7:0] Bits Name NCL [15:8] Bits Name DC [23:16] Bits Name ELT [31:31]...
Page 110 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.52 CANFD_CH_TTOCN Description: TT Operation Control Address: 0x40520114 Offset: 0x114 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TMC [7:6] RTIE [5:5] SWS [4:3] SWP [2:2] ECS [1:1] SGT [0:0] Bits Name LCKC...
Page 111 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Register Time Mark Compare 00= No Register Time Mark Interrupt generated 01= Register Time Mark Interrupt if Time Mark = cycle time 10= Register Time Mark Interrupt if Time Mark = local time 11= Register Time Mark Interrupt if Time Mark = global time...
Page 112 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.53 CANFD_CH_TTGTP Description: TT Global Time Preset Address: 0x40520118 Offset: 0x118 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TP [7:0] Bits Name TP [15:8] Bits Name CTP [23:16] Bits Name CTP [31:24] Bit-fields...
Page 113 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.54 CANFD_CH_TTTMK Description: TT Time Mark Address: 0x4052011C Offset: 0x11C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TM_ [7:0] Bits Name TM_ [15:8] Bits Name None TICC [22:16] [23:23] Bits Name LCKM...
Page 114 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.55 CANFD_CH_TTIR Description: TT Interrupt Register Address: 0x40520120 Offset: 0x120 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name GTW [7:7] SWE [6:6] TTMI [5:5] RTMI [4:4] SOG [3:3] CSM_ [2:2] SMC [1:1] SBC [0:0] Bits...
Page 115 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RW1C Stop Watch Event 0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected 1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected RW1C Global Time Wrap 0= No global time wrap occurred...
Page 116 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.56 CANFD_CH_TTIE Description: TT Interrupt Enable Address: 0x40520124 Offset: 0x124 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name GTWE [7:7] SWEE [6:6] TTMIE [5:5] RTMIE [4:4] SOGE [3:3] CSME [2:2] SMCE [1:1] SBCE [0:0] Bits...
Page 117 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TXOE Tx Count Overflow Interrupt Enable 0= Interrupt Disabled 1= Interrupt Enabled SE1E Scheduling Error 1 Interrupt Enable 0= Interrupt Disabled 1= Interrupt Enabled SE2E Scheduling Error 2 Interrupt Enable 0= Interrupt Disabled 1= Interrupt Enabled...
Page 118 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.57 CANFD_CH_TTILS Description: TT Interrupt Line Select Address: 0x40520128 Offset: 0x128 Retention: Retained IsDeepSleep: Comment: The TT Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the TT Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.
Page 119 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TXUL Tx Count Underflow Interrupt Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 TXOL Tx Count Overflow Interrupt Select 0= Assign to interrupt enabled by ILE.EINT0 1= Assign to interrupt enabled by ILE.EINT1 SE1L...
Page 120 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.58 CANFD_CH_TTOST Description: TT Operation Status Address: 0x4052012C Offset: 0x12C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name QCS [7:7] QGTP [6:6] SYS [5:4] MS [3:2] EL [1:0] Bits Name RTO [15:8] Bits Name...
Page 121 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 8:15 Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of -127 is reached.
Page 122 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.59 CANFD_CH_TURNA Description: TUR Numerator Actual Address: 0x40520130 Offset: 0x130 Retention: Retained IsDeepSleep: Comment: Default: 0x10000 Bit-field Table Bits Name NAV [7:0] Bits Name NAV [15:8] Bits Name None [23:18] NAV [17:16] Bits Name None [31:24]...
Page 123 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.60 CANFD_CH_TTLGT Description: TT Local & Global Time Address: 0x40520134 Offset: 0x134 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name LT [7:0] Bits Name LT [15:8] Bits Name GT [23:16] Bits Name GT [31:24]...
Page 124 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.61 CANFD_CH_TTCTC Description: TT Cycle Time & Count Address: 0x40520138 Offset: 0x138 Retention: Retained IsDeepSleep: Comment: Default: 0x3F0000 Bit-field Table Bits Name CT [7:0] Bits Name CT [15:8] Bits Name None [23:22] CC [21:16] Bits Name...
Page 125 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.62 CANFD_CH_TTCPT Description: TT Capture Time Address: 0x4052013C Offset: 0x13C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] CCV [5:0] Bits Name None [15:8] Bits Name SWV [23:16] Bits Name SWV [31:24]...
Page 126 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 2.3.9.6.63 CANFD_CH_TTCSM Description: TT Cycle Sync Mark Address: 0x40520140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name CSM [7:0] Bits Name CSM [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 127 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3 CM0P Description Cortex-M0+ specific registers Base Address 0xE0000000 Size 0x20000000 Slave Num SYSTEM 3.1 DWT Register Name Address Permission Description CM0P_DWT_DWT_CTRL 0xE0001000 FULL Watchpoint Comparator Configuration CM0P_DWT_DWT_PCSR 0xE000101C FULL Watchpoint Comparator PC Sample CM0P_DWT_DWT_COMP0 0xE0001020 FULL Watchpoint Comparator Compare Value...
Page 128 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.3 SCS Register Name Address Permission Description CM0P_SCS_SYST_CSR 0xE000E010 FULL SysTick Control & Status CM0P_SCS_SYST_RVR 0xE000E014 FULL SysTick Reload Value CM0P_SCS_SYST_CVR 0xE000E018 FULL SysTick Current Value CM0P_SCS_SYST_CALIB 0xE000E01C FULL SysTick Calibration Value CM0P_SCS_ISER 0xE000E100 FULL Interrupt Set-Enable Register...
Page 129 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM0P_ROM_ROM_CSMT 0xE00FFFCC FULL CM0+ CoreSight ROM Table Memory Type CM0P_ROM_ROM_PID4 0xE00FFFD0 FULL CM0+ CoreSight ROM Table Peripheral ID #4 CM0P_ROM_ROM_PID0 0xE00FFFE0 FULL CM0+ CoreSight ROM Table Peripheral ID #0 CM0P_ROM_ROM_PID1 0xE00FFFE4 FULL CM0+ CoreSight ROM Table Peripheral ID #1...
Page 130 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM0P_CTI_ITTRIGOUT 0xF0002EE8 FULL ITTRIGOUT Register CM0P_CTI_ITCHOUTACK 0xF0002EEC FULL ITCHOUTACK Register CM0P_CTI_ITTRIGOUTACK 0xF0002EF0 FULL ITTRIGOUTACK Register CM0P_CTI_ITCHIN 0xF0002EF4 FULL ITCHIN Register CM0P_CTI_ITTRIGIN 0xF0002EF8 FULL ITTRIGIN Register CM0P_CTI_ITCTRL 0xF0002F00 FULL Integration Mode Control Register CM0P_CTI_CLAIMSET...
Page 131: Dwt
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8 Register Details 3.8.1 DWT 3.8.1.1 CM0P_DWT_DWT_CTRL Description: Watchpoint Comparator Configuration Address: 0xE0001000 Offset: Retention: Retained IsDeepSleep: Comment: Defines the number of comparators implemented Default: 0x20000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8]...
Page 132: Cm0P_Dwt_Dwt_Pcsr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.2 CM0P_DWT_DWT_PCSR Description: Watchpoint Comparator PC Sample Address: 0xE000101C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: Samples the current value of the program counter. Unless DWT_PCSR reads as 0xFFFFFFFF, under the conditions described in Program counter sampling support on Arm TRM page C1-344, bit [0] is RAZ.
Page 133: Cm0P_Dwt_Dwt_Comp0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.3 CM0P_DWT_DWT_COMP0 Description: Watchpoint Comparator Compare Value Address: 0xE0001020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Provides a reference value for use by comparator Default: Bit-field Table Bits Name COMP [7:0] Bits Name COMP [15:8] Bits...
Page 134: Cm0P_Dwt_Dwt_Mask0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.4 CM0P_DWT_DWT_MASK0 Description: Watchpoint Comparator Mask Address: 0xE0001024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: Provides the size of the ignore mask applied to the access address range matching Default: Bit-field Table Bits Name MASK [7:0]...
Page 135: Cm0P_Dwt_Dwt_Function0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.5 CM0P_DWT_DWT_FUNCTION0 Description: Watchpoint Comparator Function Address: 0xE0001028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: Controls the operation of the comparator Default: Bit-field Table Bits Name None [7:4] FUNCTION [3:0] Bits Name None [15:8] Bits Name...
Page 136: Cm0P_Dwt_Dwt_Comp1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.6 CM0P_DWT_DWT_COMP1 Description: Watchpoint Comparator Compare Value Address: 0xE0001030 Offset: 0x30 Retention: Retained IsDeepSleep: Comment: Provides a reference value for use by comparator Default: Bit-field Table Bits Name COMP [7:0] Bits Name COMP [15:8] Bits...
Page 137: Cm0P_Dwt_Dwt_Mask1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.7 CM0P_DWT_DWT_MASK1 Description: Watchpoint Comparator Mask Address: 0xE0001034 Offset: 0x34 Retention: Retained IsDeepSleep: Comment: Provides the size of the ignore mask applied to the access address range matching Default: Bit-field Table Bits Name MASK [7:0]...
Page 138: Cm0P_Dwt_Dwt_Function1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.8 CM0P_DWT_DWT_FUNCTION1 Description: Watchpoint Comparator Function Address: 0xE0001038 Offset: 0x38 Retention: Retained IsDeepSleep: Comment: Controls the operation of the comparator Default: Bit-field Table Bits Name None [7:4] FUNCTION [3:0] Bits Name None [15:8] Bits Name...
Page 139 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.9 CM0P_DWT_DWT_PID4 Description: Watchpoint Unit CoreSight ROM Table Peripheral ID #4 Address: 0xE0001FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 140 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.10 CM0P_DWT_DWT_PID0 Description: Watchpoint Unit CoreSight ROM Table Peripheral ID #0 Address: 0xE0001FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 141 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.11 CM0P_DWT_DWT_PID1 Description: Watchpoint Unit CoreSight ROM Table Peripheral ID #1 Address: 0xE0001FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 142 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.12 CM0P_DWT_DWT_PID2 Description: Watchpoint Unit CoreSight ROM Table Peripheral ID #2 Address: 0xE0001FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 143 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.13 CM0P_DWT_DWT_PID3 Description: Watchpoint Unit CoreSight ROM Table Peripheral ID #3 Address: 0xE0001FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 144 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.14 CM0P_DWT_DWT_CID0 Description: Watchpoint Unit CoreSight ROM Table Component ID #0 Address: 0xE0001FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 145 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.15 CM0P_DWT_DWT_CID1 Description: Watchpoint Unit CoreSight ROM Table Component ID #1 Address: 0xE0001FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 146 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.16 CM0P_DWT_DWT_CID2 Description: Watchpoint Unit CoreSight ROM Table Component ID #2 Address: 0xE0001FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 147 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.1.17 CM0P_DWT_DWT_CID3 Description: Watchpoint Unit CoreSight ROM Table Component ID #3 Address: 0xE0001FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 148: Cm0P_Bp_Bp_Ctrl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2 BP 3.8.2.1 CM0P_BP_BP_CTRL Description: Breakpoint Unit Control Address: 0xE0002000 Offset: Retention: Retained IsDeepSleep: Comment: Provides BPU implementation information, and the global enable for the BPU. Default: 0x40 Bit-field Table Bits Name NUM_CODE [7:4] None [3:2]...
Page 149: Cm0P_Bp_Bp_Comp0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.2 CM0P_BP_BP_COMP0 Description: Breakpoint Compare Register Address: 0xE0002008 Offset: Retention: Retained IsDeepSleep: Comment: Holds a breakpoint address for comparison with instruction addresses in the Code memory region, see The system address map on Arm TRM page B3-258 for more information. Default: Bit-field Table Bits...
Page 150: Cm0P_Bp_Bp_Comp1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.3 CM0P_BP_BP_COMP1 Description: Breakpoint Compare Register Address: 0xE000200C Offset: Retention: Retained IsDeepSleep: Comment: Holds a breakpoint address for comparison with instruction addresses in the Code memory region, see The system address map on Arm TRM page B3-258 for more information. Default: Bit-field Table Bits...
Page 151: Cm0P_Bp_Bp_Comp2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.4 CM0P_BP_BP_COMP2 Description: Breakpoint Compare Register Address: 0xE0002010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Holds a breakpoint address for comparison with instruction addresses in the Code memory region, see The system address map on Arm TRM page B3-258 for more information. Default: Bit-field Table Bits...
Page 152: Cm0P_Bp_Bp_Comp3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.5 CM0P_BP_BP_COMP3 Description: Breakpoint Compare Register Address: 0xE0002014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Holds a breakpoint address for comparison with instruction addresses in the Code memory region, see The system address map on Arm TRM page B3-258 for more information. Default: Bit-field Table Bits...
Page 153 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.6 CM0P_BP_BP_PID4 Description: Breakpoint Unit CoreSight ROM Table Peripheral ID #4 Address: 0xE0002FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 154 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.7 CM0P_BP_BP_PID0 Description: Breakpoint Unit CoreSight ROM Table Peripheral ID #0 Address: 0xE0002FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 155 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.8 CM0P_BP_BP_PID1 Description: Breakpoint Unit CoreSight ROM Table Peripheral ID #1 Address: 0xE0002FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 156 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.9 CM0P_BP_BP_PID2 Description: Breakpoint Unit CoreSight ROM Table Peripheral ID #2 Address: 0xE0002FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 157 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.10 CM0P_BP_BP_PID3 Description: Breakpoint Unit CoreSight ROM Table Peripheral ID #3 Address: 0xE0002FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 158 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.11 CM0P_BP_BP_CID0 Description: Breakpoint Unit CoreSight ROM Table Component ID #0 Address: 0xE0002FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 159 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.12 CM0P_BP_BP_CID1 Description: Breakpoint Unit CoreSight ROM Table Component ID #1 Address: 0xE0002FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 160 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.13 CM0P_BP_BP_CID2 Description: Breakpoint Unit CoreSight ROM Table Component ID #2 Address: 0xE0002FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 161 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.2.14 CM0P_BP_BP_CID3 Description: Breakpoint Unit CoreSight ROM Table Component ID #3 Address: 0xE0002FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 162: Scs
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3 SCS 3.8.3.1 CM0P_SCS_SYST_CSR Description: SysTick Control & Status Address: 0xE000E010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Controls the SysTick counter and provides status data. The SysTick counter is functional in the Active and Sleep power modes (and not functional in the DeepSleep, and Hibernate power modes).
Page 163: Cm0P_Scs_Syst_Rvr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.2 CM0P_SCS_SYST_RVR Description: SysTick Reload Value Address: 0xE000E014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Sets or reads the reload value of the SYST_CVR register. Default: Bit-field Table Bits Name RELOAD [7:0] Bits Name RELOAD [15:8]...
Page 164: Cm0P_Scs_Syst_Cvr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.3 CM0P_SCS_SYST_CVR Description: SysTick Current Value Address: 0xE000E018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: Reads or clears the current counter value. Any write to the register clears the register to 0. Default: Bit-field Table Bits...
Page 165 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.4 CM0P_SCS_SYST_CALIB Description: SysTick Calibration Value Address: 0xE000E01C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: Reads the calibration value and parameters for SysTick. Default: Bit-field Table Bits Name TENMS [7:0] Bits Name TENMS [15:8] Bits Name...
Page 166: Cm0P_Scs_Iser
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.5 CM0P_SCS_ISER Description: Interrupt Set-Enable Register Address: 0xE000E100 Offset: 0x100 Retention: Retained IsDeepSleep: Comment: Enables, or reads the enabled state of one or more interrupts. Default: Bit-field Table Bits Name SETENA [7:0] Bits Name SETENA [15:8]...
Page 167: Cm0P_Scs_Icer
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.6 CM0P_SCS_ICER Description: Interrupt Clear Enable Register Address: 0xE000E180 Offset: 0x180 Retention: Retained IsDeepSleep: Comment: Disables, or reads the enabled state of one or more interrupts Default: Bit-field Table Bits Name CLRENA [7:0] Bits Name...
Page 168: Cm0P_Scs_Ispr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.7 CM0P_SCS_ISPR Description: Interrupt Set-Pending Register Address: 0xE000E200 Offset: 0x200 Retention: Retained IsDeepSleep: Comment: On writes, sets the status of one or more interrupts to pending. On reads, shows the pending status of the interrupts. Default: Bit-field Table Bits...
Page 169: Cm0P_Scs_Icpr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.8 CM0P_SCS_ICPR Description: Interrupt Clear-Pending Register Address: 0xE000E280 Offset: 0x280 Retention: Retained IsDeepSleep: Comment: On writes, clears the status of one or more interrupts to pending. On reads, shows the pending status of the interrupts. Default: Bit-field Table Bits...
Page 170: Cm0P_Scs_Ipr0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.9 CM0P_SCS_IPR Description: Interrupt Priority Registers Address: 0xE000E400 Offset: 0x400 Retention: Retained IsDeepSleep: Comment: Sets or reads interrupt priorities. Register n contains priorities for interrupts N=4n .. 4n+3 Default: Bit-field Table Bits Name PRI_N0 [7:6]...
Page 171 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.10 CM0P_SCS_CPUID Description: CPUID Register Address: 0xE000ED00 Offset: 0xD00 Retention: Retained IsDeepSleep: Comment: Contains the part number, version, and implementation information that is specific to this processor. Default: 0x410CC601 Bit-field Table Bits Name REVISION [3:0]...
Page 172: Cm0P_Scs_Icsr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.11 CM0P_SCS_ICSR Description: Interrupt Control State Register Address: 0xE000ED04 Offset: 0xD04 Retention: Retained IsDeepSleep: Comment: Controls and provides status information for the ARMv6-M. Default: Bit-field Table Bits Name VECTACTIVE [7:0] Bits Name None [11:9] VECTACTIV...
Page 173: Cm0P_Scs_Vtor
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.12 CM0P_SCS_VTOR Description: Vector Table Offset Register Address: 0xE000ED08 Offset: 0xD08 Retention: Retained IsDeepSleep: Comment: Holds the vector table offset address Default: Bit-field Table Bits Name None [7:0] Bits Name TBLOFF [15:8] Bits Name TBLOFF [23:16]...
Page 174: Cm0P_Scs_Aircr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.13 CM0P_SCS_AIRCR Description: Application Interrupt and Reset Control Register Address: 0xE000ED0C Offset: 0xD0C Retention: Retained IsDeepSleep: Comment: Sets or returns interrupt control data. Default: Bit-field Table Bits Name None [7:3] SYSRESETR VECTCLRAC None [0:0] EQ [2:2]...
Page 175: Cm0P_Scs_Scr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.14 CM0P_SCS_SCR Description: System Control Register Address: 0xE000ED10 Offset: 0xD10 Retention: Retained IsDeepSleep: Comment: Sets or returns system control data. Default: Bit-field Table Bits Name None [7:5] SEVONPEND None [3:3] SLEEPDEEP SLEEPONEX None [0:0] [4:4]...
Page 176: Cm0P_Scs_Ccr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.15 CM0P_SCS_CCR Description: Configuration and Control Register Address: 0xE000ED14 Offset: 0xD14 Retention: Retained IsDeepSleep: Comment: Returns configuration and control data. Default: 0x208 Bit-field Table Bits Name None [7:4] UNALIGN None [2:0] _TRP [3:3] Bits Name...
Page 177 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.16 CM0P_SCS_SHPR2 Description: System Handler Priority Register 2 Address: 0xE000ED1C Offset: 0xD1C Retention: Retained IsDeepSleep: Comment: Sets or returns priority for system handler 11 Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8]...
Page 178: Cm0P_Scs_Shpr3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.17 CM0P_SCS_SHPR3 Description: System Handler Priority Register 3 Address: 0xE000ED20 Offset: 0xD20 Retention: Retained IsDeepSleep: Comment: Sets or returns priority for system handlers 14-15. Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8]...
Page 179: Cm0P_Scs_Shcsr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.18 CM0P_SCS_SHCSR Description: System Handler Control and State Register Address: 0xE000ED24 Offset: 0xD24 Retention: Retained IsDeepSleep: Comment: Controls and provides the status of system handlers. Default: Bit-field Table Bits Name None [7:0] Bits Name SVCALLPEN...
Page 180: Cm0P_Scs_Dfsr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.19 CM0P_SCS_DFSR Description: Debug Fault Status Register Address: 0xE000ED30 Offset: 0xD30 Retention: Retained IsDeepSleep: Comment: Provides the top level reason why a debug event has occurred. Writing 1 to a register bit clears that bit to 0.
Page 181: Cm0P_Scs_Mpu_Type
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.20 CM0P_SCS_MPU_TYPE Description: MPU Type Register Address: 0xE000ED90 Offset: 0xD90 Retention: Retained IsDeepSleep: Comment: The MPU Type Register indicates how many regions the MPU supports. Software can use it to determine if the processor implements an MPU Default: 0x800 Bit-field Table...
Page 182: Cm0P_Scs_Mpu_Ctrl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.21 CM0P_SCS_MPU_CTRL Description: MPU Control Register Address: 0xE000ED94 Offset: 0xD94 Retention: Retained IsDeepSleep: Comment: Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
Page 183 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.22 CM0P_SCS_MPU_RNR Description: MPU Region Number Register Address: 0xE000ED98 Offset: 0xD98 Retention: Retained IsDeepSleep: Comment: Selects the region currently accessed by MPU_RBAR and MPU_RASR. Used with MPU_RBAR and MPU_RASR, see MPU Region Base Address Register, MPU_RBAR, and MPU Region Attribute and Size Register, MPU_RASR.
Page 184 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.23 CM0P_SCS_MPU_RBAR Description: MPU Region Base Address Register Address: 0xE000ED9C Offset: 0xD9C Retention: Retained IsDeepSleep: Comment: Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.
Page 185 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.24 CM0P_SCS_MPU_RASR Description: MPU Region Attribute and Size Register Address: 0xE000EDA0 Offset: 0xDA0 Retention: Retained IsDeepSleep: Comment: Defines the size, access behavior, and memory type of the region identified by MPU_RNR, and enables that region.
Page 186: Cm0P_Scs_Dhcsr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.25 CM0P_SCS_DHCSR Description: Debug Halting Control and Status Register Address: 0xE000EDF0 Offset: 0xDF0 Retention: Retained IsDeepSleep: Comment: Controls halting debug. When C_DEBUGEN is set to 1, C_STEP and C_MASKINTS must not modified when the processor is running.
Page 187 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum C_MASKINTS When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both: - before the write to DHCSR, the value of the C_HALT bit is 1...
Page 188 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.26 CM0P_SCS_DCRSR Description: Debug Core Register Selector Register Address: 0xE000EDF4 Offset: 0xDF4 Retention: Retained IsDeepSleep: Comment: With the DCRDR, see Debug Core Register Data Register, DCRDR on Arm TRM page C1- 337, the DCRSR provides debug access to the ARM core registers and special-purpose registers.
Page 189 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum WRITE Write transfer Technical Reference Manual 002-29852 Rev. *B 2022-04-18...
Page 190: Cm0P_Scs_Dcrdr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.27 CM0P_SCS_DCRDR Description: Debug Core Register Data Register Address: 0xE000EDF8 Offset: 0xDF8 Retention: Retained IsDeepSleep: Comment: With the DCRSR, see Debug Core Register Selector Register, DCRSR on Arm TRM page C1- 335, the DCRDR provides debug access to the ARM core registers and special-purpose registers.
Page 191: Cm0P_Scs_Demcr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.28 CM0P_SCS_DEMCR Description: Debug Exception and Monitor Control Register Address: 0xE000EDFC Offset: 0xDFC Retention: Retained IsDeepSleep: Comment: Manages vector catch behavior and enables the DWT. Default: Bit-field Table Bits Name None [7:1] _CORERE SET [0:0] Bits...
Page 192: Cm0P_Scs_Scs_Pid4
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.29 CM0P_SCS_SCS_PID4 Description: System Control Space ROM Table Peripheral ID #4 Address: 0xE000EFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 193: Cm0P_Scs_Scs_Pid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.30 CM0P_SCS_SCS_PID0 Description: System Control Space ROM Table Peripheral ID #0 Address: 0xE000EFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 194: Cm0P_Scs_Scs_Pid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.31 CM0P_SCS_SCS_PID1 Description: System Control Space ROM Table Peripheral ID #1 Address: 0xE000EFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 195: Cm0P_Scs_Scs_Pid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.32 CM0P_SCS_SCS_PID2 Description: System Control Space ROM Table Peripheral ID #2 Address: 0xE000EFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 196: Cm0P_Scs_Scs_Pid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.33 CM0P_SCS_SCS_PID3 Description: System Control Space ROM Table Peripheral ID #3 Address: 0xE000EFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 197: Cm0P_Scs_Scs_Cid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.34 CM0P_SCS_SCS_CID0 Description: System Control Space ROM Table Component ID #0 Address: 0xE000EFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 198: Cm0P_Scs_Scs_Cid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.35 CM0P_SCS_SCS_CID1 Description: System Control Space ROM Table Component ID #1 Address: 0xE000EFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 199: Cm0P_Scs_Scs_Cid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.36 CM0P_SCS_SCS_CID2 Description: System Control Space ROM Table Component ID #2 Address: 0xE000EFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 200: Cm0P_Scs_Scs_Cid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.3.37 CM0P_SCS_SCS_CID3 Description: System Control Space ROM Table Component ID #3 Address: 0xE000EFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16]...
Page 201: Rom
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4 ROM 3.8.4.1 CM0P_ROM_ROM_SCS Description: CM0+ CoreSight ROM Table Peripheral #0 Address: 0xE00FF000 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF0F003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 202: Cm0P_Rom_Rom_Dwt
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.2 CM0P_ROM_ROM_DWT Description: CM0+ CoreSight ROM Table Peripheral #1 Address: 0xE00FF004 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF02003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 203: Cm0P_Rom_Rom_Bpu
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.3 CM0P_ROM_ROM_BPU Description: CM0+ CoreSight ROM Table Peripheral #2 Address: 0xE00FF008 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF03003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 204: Cm0P_Rom_Rom_End
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.4 CM0P_ROM_ROM_END Description: CM0+ CoreSight ROM Table End Marker Address: 0xE00FF00C Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 205: Cm0P_Rom_Rom_Csmt
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.5 CM0P_ROM_ROM_CSMT Description: CM0+ CoreSight ROM Table Memory Type Address: 0xE00FFFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 206 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.6 CM0P_ROM_ROM_PID4 Description: CM0+ CoreSight ROM Table Peripheral ID #4 Address: 0xE00FFFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 207 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.7 CM0P_ROM_ROM_PID0 Description: CM0+ CoreSight ROM Table Peripheral ID #0 Address: 0xE00FFFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0xC0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 208 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.8 CM0P_ROM_ROM_PID1 Description: CM0+ CoreSight ROM Table Peripheral ID #1 Address: 0xE00FFFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB4 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 209 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.9 CM0P_ROM_ROM_PID2 Description: CM0+ CoreSight ROM Table Peripheral ID #2 Address: 0xE00FFFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 210 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.10 CM0P_ROM_ROM_PID3 Description: CM0+ CoreSight ROM Table Peripheral ID #3 Address: 0xE00FFFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 211 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.11 CM0P_ROM_ROM_CID0 Description: CM0+ CoreSight ROM Table Component ID #0 Address: 0xE00FFFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 212 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.12 CM0P_ROM_ROM_CID1 Description: CM0+ CoreSight ROM Table Component ID #1 Address: 0xE00FFFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x10 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 213: Cm0P_Rom_Rom_Cid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.13 CM0P_ROM_ROM_CID2 Description: CM0+ CoreSight ROM Table Component ID #2 Address: 0xE00FFFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 214: Cm0P_Rom_Rom_Cid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.4.14 CM0P_ROM_ROM_CID3 Description: CM0+ CoreSight ROM Table Component ID #3 Address: 0xE00FFFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 215: Romtable
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5 ROMTABLE 3.8.5.1 CM0P_ROMTABLE_ADDR0 Description: Link to Cortex M0+ ROM Table. Address: 0xF0000000 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xF00FF003 Bit-field Table Bits Name None [7:2] FORMAT PRESENT _32BIT [1:1] [0:0] Bits Name None [11:8]...
Page 216: Cm0P_Romtable_Addr1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.2 CM0P_ROMTABLE_ADDR1 Description: Link to CoreSight CTI Table. Address: 0xF0000004 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0x2003 Bit-field Table Bits Name None [7:2] FORMAT PRESENT _32BIT [1:1] [0:0] Bits Name None [11:8] Bits Name ADDR_OFFSET [23:16]...
Page 217: Cm0P_Romtable_Addr2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.3 CM0P_ROMTABLE_ADDR2 Description: Link to Cortex M0+ MTB Table. Address: 0xF0000008 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0x3003 Bit-field Table Bits Name None [7:2] FORMAT PRESENT _32BIT [1:1] [0:0] Bits Name None [11:8] Bits Name...
Page 218: Cm0P_Romtable_Did
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.4 CM0P_ROMTABLE_DID Description: Device Type Identifier register. Address: 0xF0000FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 219: Cm0P_Romtable_Pid4
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.5 CM0P_ROMTABLE_PID4 Description: Peripheral Identification Register 4. Address: 0xF0000FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COUNT [7:4] JEP_CONTINUATION [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 220: Cm0P_Romtable_Pid5
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.6 CM0P_ROMTABLE_PID5 Description: Peripheral Identification Register 5. Address: 0xF0000FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 221: Cm0P_Romtable_Pid6
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.7 CM0P_ROMTABLE_PID6 Description: Peripheral Identification Register 6. Address: 0xF0000FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 222: Cm0P_Romtable_Pid7
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.8 CM0P_ROMTABLE_PID7 Description: Peripheral Identification Register 7. Address: 0xF0000FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 223: Cm0P_Romtable_Pid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.9 CM0P_ROMTABLE_PID0 Description: Peripheral Identification Register 0. Address: 0xF0000FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name PN_MIN [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 224: Cm0P_Romtable_Pid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.10 CM0P_ROMTABLE_PID1 Description: Peripheral Identification Register 1. Address: 0xF0000FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name JEPID_MIN [7:4] PN_MAJ [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 225: Cm0P_Romtable_Pid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.11 CM0P_ROMTABLE_PID2 Description: Peripheral Identification Register 2. Address: 0xF0000FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name REV [7:4] None [3:3] JEPID_MAJ [2:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 226: Cm0P_Romtable_Pid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.12 CM0P_ROMTABLE_PID3 Description: Peripheral Identification Register 3. Address: 0xF0000FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name REV_AND [7:4] CM [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 227: Cm0P_Romtable_Cid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.13 CM0P_ROMTABLE_CID0 Description: Component Identification Register 0. Address: 0xF0000FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 228: Cm0P_Romtable_Cid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.14 CM0P_ROMTABLE_CID1 Description: Component Identification Register 1. Address: 0xF0000FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x10 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 229: Cm0P_Romtable_Cid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.15 CM0P_ROMTABLE_CID2 Description: Component Identification Register 2. Address: 0xF0000FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 230: Cm0P_Romtable_Cid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.5.16 CM0P_ROMTABLE_CID3 Description: Component Identification Register 3. Address: 0xF0000FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 231: Cti
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6 CTI 3.8.6.1 CM0P_CTI_CTICONTROL Description: CTI Control Register Address: 0xF0002000 Offset: Retention: Retained IsDeepSleep: Comment: The CTI Control Register enables the CTI. Default: Bit-field Table Bits Name None [7:1] GLBEN [0:0] Bits Name None [15:8]...
Page 232: Cm0P_Cti_Ctiintack
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.2 CM0P_CTI_CTIINTACK Description: CTI Interrupt Acknowledge Register Address: 0xF0002010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the CTITRIGOUT output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated.
Page 233: Cm0P_Cti_Ctiappset
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.3 CM0P_CTI_CTIAPPSET Description: CTI Application Trigger Set Register Address: 0xF0002014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised, corresponding to the bit written to.
Page 234: Cm0P_Cti_Ctiappclear
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.4 CM0P_CTI_CTIAPPCLEAR Description: CTI Application Trigger Clear Register Address: 0xF0002018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Clear Register is write-only. A write to this register causes a channel event to be cleared, corresponding to the bit written to.
Page 235: Cm0P_Cti_Ctiapppulse
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.5 CM0P_CTI_CTIAPPPULSE Description: CTI Application Pulse Register Address: 0xF000201C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse, one CTICLK period, to be generated, corresponding to the bit written to. The pulse external to the ECT can be extended to multi-cycle by the handshaking interface circuits.
Page 236: Cm0P_Cti_Ctiinen0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.6 CM0P_CTI_CTIINEN Description: CTI Trigger to Channel Enable Registers Address: 0xF0002020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: The CTI Trigger to Channel Enable Registers enable the signaling of an event on CTM channels when the core issues a trigger, CTITRIGIN, to the CTI.
Page 237: Cm0P_Cti_Ctiouten0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.7 CM0P_CTI_CTIOUTEN Description: CTI Channel to Trigger Enable Registers Address: 0xF00020A0 Offset: 0xA0 Retention: Retained IsDeepSleep: Comment: The CTI Channel to Trigger Enable Registers define which channels can generate a CTITRIGOUT output. There is one register for each of the eight CTITRIGOUT outputs. Within each register there is one bit for each of the four channels implemented.
Page 238: Cm0P_Cti_Ctitriginstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.8 CM0P_CTI_CTITRIGINSTATUS Description: CTI Trigger In Status Register Address: 0xF0002130 Offset: 0x130 Retention: Retained IsDeepSleep: Comment: The CTI Trigger In Status Register provides the status of the CTITRIGIN inputs. Default: Bit-field Table Bits Name TRIGINSTATUS [7:0]...
Page 239: Cm0P_Cti_Ctitrigoutstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.9 CM0P_CTI_CTITRIGOUTSTATUS Description: CTI Trigger Out Status Register Address: 0xF0002134 Offset: 0x134 Retention: Retained IsDeepSleep: Comment: The CTI Trigger Out Status Register provides the status of the CTITRIGOUT outputs. Default: Bit-field Table Bits Name TRIGOUTSTATUS [7:0]...
Page 240: Cm0P_Cti_Ctichinstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.10 CM0P_CTI_CTICHINSTATUS Description: CTI Channel In Status Register Address: 0xF0002138 Offset: 0x138 Retention: Retained IsDeepSleep: Comment: The CTI Channel In Status Register provides the status of the CTI CTICHIN inputs. Default: Bit-field Table Bits Name...
Page 241: Cm0P_Cti_Ctichoutstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.11 CM0P_CTI_CTICHOUTSTATUS Description: CTI Channel Out Status Register Address: 0xF000213C Offset: 0x13C Retention: Retained IsDeepSleep: Comment: The CTI Channel Out Status Register provides the status of the CTI CTICHOUT outputs. Default: Bit-field Table Bits Name...
Page 242: Cm0P_Cti_Ctigate
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.12 CM0P_CTI_CTIGATE Description: Enable CTI Channel Gate Register Address: 0xF0002140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs.
Page 243: Cm0P_Cti_Asicctl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.13 CM0P_CTI_ASICCTL Description: External Multiplexor Control Register Address: 0xF0002144 Offset: 0x144 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ASICCTL [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 244: Cm0P_Cti_Itchinack
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.14 CM0P_CTI_ITCHINACK Description: ITCHINACK Register Address: 0xF0002EDC Offset: 0xEDC Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHINACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 245: Cm0P_Cti_Ittriginack
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.15 CM0P_CTI_ITTRIGINACK Description: ITTRIGINACK Register Address: 0xF0002EE0 Offset: 0xEE0 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGINACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 246: Cm0P_Cti_Itchout
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.16 CM0P_CTI_ITCHOUT Description: ITCHOUT Register Address: 0xF0002EE4 Offset: 0xEE4 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUT [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 247: Cm0P_Cti_Ittrigout
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.17 CM0P_CTI_ITTRIGOUT Description: ITTRIGOUT Register Address: 0xF0002EE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGOUT [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 248: Cm0P_Cti_Itchoutack
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.18 CM0P_CTI_ITCHOUTACK Description: ITCHOUTACK Register Address: 0xF0002EEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUTACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 249: Cm0P_Cti_Ittrigoutack
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.19 CM0P_CTI_ITTRIGOUTACK Description: ITTRIGOUTACK Register Address: 0xF0002EF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGOUTACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 250: Cm0P_Cti_Itchin
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.20 CM0P_CTI_ITCHIN Description: ITCHIN Register Address: 0xF0002EF4 Offset: 0xEF4 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHIN [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 251: Cm0P_Cti_Ittrigin
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.21 CM0P_CTI_ITTRIGIN Description: ITTRIGIN Register Address: 0xF0002EF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGIN [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 252: Cm0P_Cti_Itctrl
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.22 CM0P_CTI_ITCTRL Description: Integration Mode Control Register Address: 0xF0002F00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving.
Page 253: Cm0P_Cti_Claimset
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.23 CM0P_CTI_CLAIMSET Description: Claim Tag Set Register Address: 0xF0002FA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
Page 254: Cm0P_Cti_Claimclr
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.24 CM0P_CTI_CLAIMCLR Description: Claim Tag Clear Register Address: 0xF0002FA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
Page 255: Cm0P_Cti_Lockaccess
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.25 CM0P_CTI_LOCKACCESS Description: Lock Access Register Address: 0xF0002FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: This is used to enable write access to device registers. If LOCKSTATUS[0] == 0x0 then this register is not present. Default: Bit-field Table Bits...
Page 256: Cm0P_Cti_Lockstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.26 CM0P_CTI_LOCKSTATUS Description: Lock Status Register Address: 0xF0002FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism.
Page 257: Cm0P_Cti_Authstatus
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.27 CM0P_CTI_AUTHSTATUS Description: Authentication Status Register Address: 0xF0002FB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register Default: Bit-field Table Bits...
Page 258: Cm0P_Cti_Devid
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.28 CM0P_CTI_DEVID Description: Device Configuration Register Address: 0xF0002FC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: This register is implementation-defined for each Part Number and Designer. This indicates the capabilities of the component. The entire 32-bit field can be used because the data width is determined by the particular component.
Page 259: Cm0P_Cti_Devtype
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.29 CM0P_CTI_DEVTYPE Description: Device Type Identifier Register Address: 0xF0002FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: 0x14 indicates this device has a major type of debug control logic component (0x4) and sub- type corresponding to cross trigger (0x1).
Page 260: Cm0P_Cti_Pid4
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.30 CM0P_CTI_PID4 Description: Peripheral Identification Register 4 Address: 0xF0002FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 261: Cm0P_Cti_Pid5
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.31 CM0P_CTI_PID5 Description: Peripheral Identification Register 5 Address: 0xF0002FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 262: Cm0P_Cti_Pid6
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.32 CM0P_CTI_PID6 Description: Peripheral Identification Register 6 Address: 0xF0002FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 263: Cm0P_Cti_Pid7
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.33 CM0P_CTI_PID7 Description: Peripheral Identification Register 7 Address: 0xF0002FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 264: Cm0P_Cti_Pid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.34 CM0P_CTI_PID0 Description: Peripheral Identification Register 0 Address: 0xF0002FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0xA6 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 265: Cm0P_Cti_Pid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.35 CM0P_CTI_PID1 Description: Peripheral Identification Register 1 Address: 0xF0002FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 266: Cm0P_Cti_Pid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.36 CM0P_CTI_PID2 Description: Peripheral Identification Register 2 Address: 0xF0002FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 267: Cm0P_Cti_Pid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.37 CM0P_CTI_PID3 Description: Peripheral Identification Register 3 Address: 0xF0002FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 268: Cm0P_Cti_Cid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.38 CM0P_CTI_CID0 Description: Component Identification Register 0 Address: 0xF0002FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 269: Cm0P_Cti_Cid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.39 CM0P_CTI_CID1 Description: Component Identification Register 1 Address: 0xF0002FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 270: Cm0P_Cti_Cid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.40 CM0P_CTI_CID2 Description: Component Identification Register 2 Address: 0xF0002FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 271: Cm0P_Cti_Cid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.6.41 CM0P_CTI_CID3 Description: Component Identification Register 3 Address: 0xF0002FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 272: Mtb
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7 MTB 3.8.7.1 CM0P_MTB_POSITION Description: POSITION register Address: 0xF0003000 Offset: Retention: Retained IsDeepSleep: Comment: Contains the trace write pointer and the wrap bit. Available in all MTB configurations. You can modify all fields by software. Automatic hardware mechanisms update all fields. A debug agent might use the WRAP bit to determine whether the trace information above and below the pointer address is valid.
Page 273: Cm0P_Mtb_Master
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.2 CM0P_MTB_MASTER Description: MASTER register Address: 0xF0003004 Offset: Retention: Retained IsDeepSleep: Comment: Contains: - The main trace enable bit. - Other trace control fields. Usage constraints - Before the MASTER.EN or MASTER.TSTARTEN bits are set to 1, software must initialize the POSITION and FLOW registers.
Page 274 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MASK This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment.
Page 275 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written.
Page 276: Cm0P_Mtb_Flow
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.3 CM0P_MTB_FLOW Description: FLOW register Address: 0xF0003008 Offset: Retention: Retained IsDeepSleep: Comment: Contains: - The WATERMARK address. - The AUTOSTOP and AUTOHALT control bits. Usage constraints: There are no additional usage constraints. Configurations: Available in all MTB configurations.
Page 277: Cm0P_Mtb_Base
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.4 CM0P_MTB_BASE Description: BASE register Address: 0xF000300C Offset: Retention: Retained IsDeepSleep: Comment: Purpose: Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. Usage constraints: There are no additional usage constraints.
Page 278: Cm0P_Mtb_La
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.5 CM0P_MTB_LA Description: Lock Access register Address: 0xF0003FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 279: Cm0P_Mtb_Ls
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.6 CM0P_MTB_LS Description: Lock Status register Address: 0xF0003FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 280: Cm0P_Mtb_As
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.7 CM0P_MTB_AS Description: Authentication Status register Address: 0xF0003FB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name AS_3 [3:3] NIDEN [2:2] AS_1 [1:1] DBGEN [0:0] Bits Name AS_31TO4 [15:8] Bits Name AS_31TO4 [23:16]...
Page 281: Cm0P_Mtb_Darch
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.8 CM0P_MTB_DARCH Description: Device Architecture register Address: 0xF0003FBC Offset: 0xFBC Retention: Retained IsDeepSleep: Comment: Default: 0x47700A31 Bit-field Table Bits Name ARCH_ID [7:0] Bits Name ARCH_ID [15:8] Bits Name RES_20 REVISION [19:16] [20:20] Bits Name...
Page 282: Cm0P_Mtb_Dcfg
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.9 CM0P_MTB_DCFG Description: Device Configuration register Address: 0xF0003FC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 283: Cm0P_Mtb_Did
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.10 CM0P_MTB_DID Description: Device Type Identifier register. Address: 0xF0003FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: 0x31 Bit-field Table Bits Name SUB_TYPE [7:4] CLASS [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 284: Cm0P_Mtb_Pid4
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.11 CM0P_MTB_PID4 Description: Peripheral Identification Register 4. Address: 0xF0003FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 285: Cm0P_Mtb_Pid5
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.12 CM0P_MTB_PID5 Description: Peripheral Identification Register 5. Address: 0xF0003FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 286: Cm0P_Mtb_Pid6
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.13 CM0P_MTB_PID6 Description: Peripheral Identification Register 6. Address: 0xF0003FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 287: Cm0P_Mtb_Pid7
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.14 CM0P_MTB_PID7 Description: Peripheral Identification Register 7. Address: 0xF0003FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 288: Cm0P_Mtb_Pid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.15 CM0P_MTB_PID0 Description: Peripheral Identification Register 0. Address: 0xF0003FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0x32 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 289: Cm0P_Mtb_Pid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.16 CM0P_MTB_PID1 Description: Peripheral Identification Register 1. Address: 0xF0003FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 290: Cm0P_Mtb_Pid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.17 CM0P_MTB_PID2 Description: Peripheral Identification Register 2. Address: 0xF0003FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x1B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 291: Cm0P_Mtb_Pid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.18 CM0P_MTB_PID3 Description: Peripheral Identification Register 3. Address: 0xF0003FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 292: Cm0P_Mtb_Cid0
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.19 CM0P_MTB_CID0 Description: Component Identification Register 0. Address: 0xF0003FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 293: Cm0P_Mtb_Cid1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.20 CM0P_MTB_CID1 Description: Component Identification Register 1. Address: 0xF0003FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 294: Cm0P_Mtb_Cid2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.21 CM0P_MTB_CID2 Description: Component Identification Register 2. Address: 0xF0003FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 295: Cm0P_Mtb_Cid3
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 3.8.7.22 CM0P_MTB_CID3 Description: Component Identification Register 3. Address: 0xF0003FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 296 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4 CM4 Description Cortex-M4 specific registers Base Address 0xE0000000 Size 0x20000000 Slave Num SYSTEM 4.1 ITM Register Name Address Permission Description CM4_ITM_STIM0 0xE0000000 FULL Stimulus Port registers CM4_ITM_STIM1 0xE0000004 FULL Stimulus Port registers CM4_ITM_STIM2 0xE0000008 FULL Stimulus Port registers...
Page 297 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_DWT_CTRL 0xE0001000 FULL Control register CM4_DWT_CYCCNT 0xE0001004 FULL Cycle Count register CM4_DWT_CPICNT 0xE0001008 FULL CPI Count register CM4_DWT_EXCCNT 0xE000100C FULL Exception Overhead Count register CM4_DWT_SLEEPCNT 0xE0001010 FULL Sleep Count register CM4_DWT_LSUCNT 0xE0001014 FULL...
Page 298 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_SCS_SYST_RVR 0xE000E014 FULL SysTick Reload Value Register CM4_SCS_SYST_CVR 0xE000E018 FULL SysTick Current Value Register CM4_SCS_SYST_CALIB 0xE000E01C FULL SysTick Calibration value Register CM4_SCS_NVIC_ISER0 0xE000E100 FULL Interrupt Set-Enable Registers CM4_SCS_NVIC_ISER1 0xE000E104 FULL Interrupt Set-Enable Registers...
Page 299 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_SCS_NVIC_IPR20 0xE000E450 FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR21 0xE000E454 FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR22 0xE000E458 FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR23 0xE000E45C FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR24 0xE000E460 FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR25 0xE000E464 FULL...
Page 300 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_SCS_MPU_RASR_A1 0xE000EDA8 FULL MPU alias registers CM4_SCS_MPU_RBAR_A2 0xE000EDAC FULL MPU alias registers CM4_SCS_MPU_RASR_A2 0xE000EDB0 FULL MPU alias registers CM4_SCS_MPU_RBAR_A3 0xE000EDB4 FULL MPU alias registers CM4_SCS_MPU_RASR_A3 0xE000EDB8 FULL MPU alias registers CM4_SCS_DHCSR 0xE000EDF0 FULL...
Page 301 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_ETM_PID2 0xE0041FE8 FULL Peripheral Identification Register 2. CM4_ETM_PID3 0xE0041FEC FULL Peripheral Identification Register 3. CM4_ETM_CID0 0xE0041FF0 FULL Component Identification Register 0. CM4_ETM_CID1 0xE0041FF4 FULL Component Identification Register 1. CM4_ETM_CID2 0xE0041FF8 FULL Component Identification Register 2.
Page 302 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_CM4CTI_CID3 0xE0042FFC FULL Component Identification Register 3 4.7 ROM Register Name Address Permission Description CM4_ROM_SCS 0xE007F000 FULL CM4 CoreSight ROM Table Peripheral #0 CM4_ROM_DWT 0xE007F004 FULL CM4 CoreSight ROM Table Peripheral #1 CM4_ROM_FPB 0xE007F008 FULL...
Page 303 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_TRCCTI_LOCKSTATUS 0xE0080FB4 FULL Lock Status Register CM4_TRCCTI_AUTHSTATUS 0xE0080FB8 FULL Authentication Status Register CM4_TRCCTI_DEVID 0xE0080FC8 FULL Device Configuration Register CM4_TRCCTI_DEVTYPE 0xE0080FCC FULL Device Type Identifier Register CM4_TRCCTI_PID4 0xE0080FD0 FULL Peripheral Identification Register 4 CM4_TRCCTI_PID5...
Page 304 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_ETB_ITATBCTR2 0xE008DEF0 FULL Integration Register CM4_ETB_ITATBCTR1 0xE008DEF4 FULL Integration Register CM4_ETB_ITATBCTR0 0xE008DEF8 FULL Integration Register CM4_ETB_ITCTRL 0xE008DF00 FULL Integration Mode Control Register CM4_ETB_CLAIMSET 0xE008DFA0 FULL Claim Tag Set Register CM4_ETB_CLAIMCLR 0xE008DFA4 FULL Claim Tag Clear Register...
Page 305 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CM4_ROMTABLE_CM4 0xE00FF010 FULL CM4 CoreSight ROM Table Peripheral #4 CM4_ROMTABLE_CSMT 0xE00FFFCC FULL CM4 CoreSight ROM Table Memory Type CM4_ROMTABLE_PID4 0xE00FFFD0 FULL CM4 CoreSight ROM Table Peripheral ID #4 CM4_ROMTABLE_PID0 0xE00FFFE0 FULL CM4 CoreSight ROM Table Peripheral ID #0...
Page 306 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13 Register Details 4.13.1 ITM 4.13.1.1 CM4_ITM_STIM Description: Stimulus Port registers Address: 0xE0000000 Offset: Retention: Retained IsDeepSleep: Comment: The ITM_STIMx register characteristics are: Purpose: Provide the interface for generating instrumentation messages. Usage constraints: - Accessible by word-aligned byte, halfword, and word accesses.
Page 307 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.2 CM4_ITM_TER Description: Trace Enable Register Address: 0xE0000E00 Offset: 0xE00 Retention: Retained IsDeepSleep: Comment: The ITM_TERx characteristics are: Purpose: Provide an individual enable bit for each ITM_STIM register. Usage constraints - Each ITM_TER provides enable bits for 32 ITM_STIM registers. - Bits corresponding to unimplemented ITM_STIM registers are RAZ/WI.
Page 308 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.3 CM4_ITM_TPR Description: ITM Trace Privilege Register Address: 0xE0000E40 Offset: 0xE40 Retention: Retained IsDeepSleep: Comment: Characteristics and bit assignments of the ITM_TPR register. Purpose: Enables an operating system to control the stimulus ports that are accessible by user code.
Page 309 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.4 CM4_ITM_TCR Description: Trace Control Register Address: 0xE0000E80 Offset: 0xE80 Retention: Retained IsDeepSleep: Comment: The ITM_TCR characteristics are: Purpose: Configures and controls transfers through the ITM interface. Usage constraints: For information about constraints that apply in a system that supports multiple trace streams see CoreSight requirements for the TraceBusID field on page C1-778.
Page 310 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TXENA Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU: 0 Disabled. 1 Enabled. It is IMPLEMENTATION DEFINED whether the DWT discards packets that it cannot forward to the ITM.
Page 311 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum BUSY Indicates whether the ITM is currently processing events: 0 ITM is not processing any events. 1 ITM events present and being drained. These bits are read-only. Technical Reference Manual 002-29852 Rev.
Page 312 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.5 CM4_ITM_LAR Description: Lock Access Register Address: 0xE0000FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: This is used to enable write access to device registers. If LSR[0] == 0x0 then this register is not present.
Page 313 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.6 CM4_ITM_LSR Description: Lock Status Register Address: 0xE0000FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism.
Page 314 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.7 CM4_ITM_PID4 Description: Peripheral Identification Register 4. Address: 0xE0000FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 315 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.8 CM4_ITM_PID5 Description: Peripheral Identification Register 5. Address: 0xE0000FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 316 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.9 CM4_ITM_PID6 Description: Peripheral Identification Register 6. Address: 0xE0000FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 317 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.10 CM4_ITM_PID7 Description: Peripheral Identification Register 7. Address: 0xE0000FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 318 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.11 CM4_ITM_PID0 Description: Peripheral Identification Register 0. Address: 0xE0000FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 319 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.12 CM4_ITM_PID1 Description: Peripheral Identification Register 1. Address: 0xE0000FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 320 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.13 CM4_ITM_PID2 Description: Peripheral Identification Register 2. Address: 0xE0000FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x3B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 321 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.14 CM4_ITM_PID3 Description: Peripheral Identification Register 3. Address: 0xE0000FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 322 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.15 CM4_ITM_CID0 Description: Component Identification Register 0. Address: 0xE0000FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 323 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.16 CM4_ITM_CID1 Description: Component Identification Register 1. Address: 0xE0000FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 324 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.17 CM4_ITM_CID2 Description: Component Identification Register 2. Address: 0xE0000FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 325 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.1.18 CM4_ITM_CID3 Description: Component Identification Register 3. Address: 0xE0000FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 326 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2 DWT 4.13.2.1 CM4_DWT_CTRL Description: Control register Address: 0xE0001000 Offset: Retention: Retained IsDeepSleep: Comment: The CTRL register characteristics are: Purpose: Provides configuration and status information for the DWT unit, and used to control features of the unit.
Page 327 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 10:11 SYNCTAP Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate: 00 Disabled. No Synchronization packets. 01 Synchronization counter tap at CYCCNT[24].
Page 328 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum NOCYCCNT Shows whether the implementation supports a cycle counter: 0 Cycle counter supported. 1 Cycle counter not supported. For more information see CYCCNT cycle counter and related timers on Arm TRM page C1-792.
Page 329 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.2 CM4_DWT_CYCCNT Description: Cycle Count register Address: 0xE0001004 Offset: Retention: Retained IsDeepSleep: Comment: The CYCCNT register characteristics are: Purpose: Shows or sets the value of the processor cycle counter, CYCCNT. Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state.
Page 330 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.3 CM4_DWT_CPICNT Description: CPI Count register Address: 0xE0001008 Offset: Retention: Retained IsDeepSleep: Comment: The CPICNT register characteristics are: Purpose: Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. Usage constraints: The counter initializes to 0 when software enables its counter overflow event by setting the CTRL.CPIEVTENA bit to 1.
Page 331 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.4 CM4_DWT_EXCCNT Description: Exception Overhead Count register Address: 0xE000100C Offset: Retention: Retained IsDeepSleep: Comment: The EXCCNT register characteristics are: Purpose: Counts the total cycles spent in exception processing. Usage constraints: The counter initializes to 0 when software enables its counter overflow event by setting the CTRL.EXCEVTENA bit to 1.
Page 332 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.5 CM4_DWT_SLEEPCNT Description: Sleep Count register Address: 0xE0001010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The SLEEPCNT register characteristics are: Purpose: Counts the total number of cycles that the processor is sleeping. Usage constraints: The counter initializes to 0 when software enables its counter overflow event by setting the CTRL.SLEEPEVTENA bit to 1.
Page 333 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.6 CM4_DWT_LSUCNT Description: LSU Count register Address: 0xE0001014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: The LSUCNT register characteristics are: Purpose: Increments on the additional cycles required to execute all load or store instructions Usage constraints: The counter initializes to 0 when software enables its counter overflow event by setting the CTRL.LSUEVTENA bit to 1.
Page 334 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.7 CM4_DWT_FOLDCNT Description: Folded-instruction Count register Address: 0xE0001018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: The FOLDCNT register characteristics are: Purpose: Increments on each instruction that takes 0 cycles. Usage constraints: - The counter initializes to 0 when software enables its counter overflow event by setting the CTRL.FOLDEVTENA bit to 1.
Page 335 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.8 CM4_DWT_PCSR Description: Program Counter Sample Register Address: 0xE000101C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: The PCSR characteristics are: Purpose: Samples the current value of the program counter. Usage constraints: There are no usage constraints. Note: Bit[0] of any sampled value is RAZ and does not reflect instruction set state as it does in a PC sample on the ARMv7-A and ARMv7-R architecture profiles.
Page 336 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.9 CM4_DWT_COMP0 Description: Comparator registers Address: 0xE0001020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: The COMPn register characteristics are: Purpose: Provides a reference value for use by comparator n. Usage constraints: The operation of comparator n depends also on the registers MASKn and FUNCTIONn, see Comparator Mask registers, MASKn and Comparator Function registers, FUNCTIONn on page C1-806.
Page 337 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.10 CM4_DWT_MASK0 Description: Comparator Mask registers Address: 0xE0001024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: The MASKn register characteristics are: Purpose: Provides the size of the ignore mask applied to the access address for address range matching by comparator n.
Page 338 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.11 CM4_DWT_FUNCTION0 Description: Comparator Function registers Address: 0xE0001028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: The FUNCTIONn register characteristics are: Purpose: Controls the operation of comparator n. Usage constraints: The operation of comparator n depends also on the registers COMPn and MASKn, see Comparator registers, COMPn on page C1-805 and Comparator Mask registers, MASKn on Arm TRM page C1-805.
Page 339 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum EMITRANGE If the implementation supports trace sampling, enables generation of Data trace address packets, that hold Daddr[15:0]: 0 Data trace address packets disabled. 1 Enable Data trace address packet generation. For more information see Address comparison functions on Arm TRM page C1-781.
Page 340 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MATCHED Comparator match: 0 No match. 1 Match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0.
Page 341 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.12 CM4_DWT_COMP1 Description: Comparator registers Address: 0xE0001030 Offset: 0x30 Retention: Retained IsDeepSleep: Comment: The COMPn register characteristics are: Purpose: Provides a reference value for use by comparator n. Usage constraints: The operation of comparator n depends also on the registers MASKn and FUNCTIONn, see Comparator Mask registers, MASKn and Comparator Function registers, FUNCTIONn on Arm TRM page C1-806.
Page 342 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.13 CM4_DWT_MASK1 Description: Comparator Mask registers Address: 0xE0001034 Offset: 0x34 Retention: Retained IsDeepSleep: Comment: The MASKn register characteristics are: Purpose: Provides the size of the ignore mask applied to the access address for address range matching by comparator n.
Page 343 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.14 CM4_DWT_FUNCTION1 Description: Comparator Function registers Address: 0xE0001038 Offset: 0x38 Retention: Retained IsDeepSleep: Comment: The FUNCTIONn register characteristics are: Purpose: Controls the operation of comparator n. Usage constraints: The operation of comparator n depends also on the registers COMPn and MASKn, see Comparator registers, COMPn on page C1-805 and Comparator Mask registers, MASKn on Arm TRM page C1-805.
Page 344 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum EMITRANGE If the implementation supports trace sampling, enables generation of Data trace address packets, that hold Daddr[15:0]: 0 Data trace address packets disabled. 1 Enable Data trace address packet generation. For more information see Address comparison functions on Arm TRM page C1-781.
Page 345 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MATCHED Comparator match: 0 No match. 1 Match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0.
Page 346 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.15 CM4_DWT_COMP2 Description: Comparator registers Address: 0xE0001040 Offset: 0x40 Retention: Retained IsDeepSleep: Comment: The COMPn register characteristics are: Purpose: Provides a reference value for use by comparator n. Usage constraints: The operation of comparator n depends also on the registers MASKn and FUNCTIONn, see Comparator Mask registers, MASKn and Comparator Function registers, FUNCTIONn on Arm TRM page C1-806.
Page 347 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.16 CM4_DWT_MASK2 Description: Comparator Mask registers Address: 0xE0001044 Offset: 0x44 Retention: Retained IsDeepSleep: Comment: The MASKn register characteristics are: Purpose: Provides the size of the ignore mask applied to the access address for address range matching by comparator n.
Page 348 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.17 CM4_DWT_FUNCTION2 Description: Comparator Function registers Address: 0xE0001048 Offset: 0x48 Retention: Retained IsDeepSleep: Comment: The FUNCTIONn register characteristics are: Purpose: Controls the operation of comparator n. Usage constraints: The operation of comparator n depends also on the registers COMPn and MASKn, see Comparator registers, COMPn on page C1-805 and Comparator Mask registers, MASKn on Arm TRM page C1-805.
Page 349 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum EMITRANGE If the implementation supports trace sampling, enables generation of Data trace address packets, that hold Daddr[15:0]: 0 Data trace address packets disabled. 1 Enable Data trace address packet generation. For more information see Address comparison functions on Arm TRM page C1-781.
Page 350 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MATCHED Comparator match: 0 No match. 1 Match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0.
Page 351 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.18 CM4_DWT_COMP3 Description: Comparator registers Address: 0xE0001050 Offset: 0x50 Retention: Retained IsDeepSleep: Comment: The COMPn register characteristics are: Purpose: Provides a reference value for use by comparator n. Usage constraints: The operation of comparator n depends also on the registers MASKn and FUNCTIONn, see Comparator Mask registers, MASKn and Comparator Function registers, FUNCTIONn on Arm TRM page C1-806.
Page 352 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.19 CM4_DWT_MASK3 Description: Comparator Mask registers Address: 0xE0001054 Offset: 0x54 Retention: Retained IsDeepSleep: Comment: The MASKn register characteristics are: Purpose: Provides the size of the ignore mask applied to the access address for address range matching by comparator n.
Page 353 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.20 CM4_DWT_FUNCTION3 Description: Comparator Function registers Address: 0xE0001058 Offset: 0x58 Retention: Retained IsDeepSleep: Comment: The FUNCTIONn register characteristics are: Purpose: Controls the operation of comparator n. Usage constraints: The operation of comparator n depends also on the registers COMPn and MASKn, see Comparator registers, COMPn on Arm TRM page C1-805 and Comparator Mask registers, MASKn on Arm TRM page C1-805.
Page 354 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum EMITRANGE If the implementation supports trace sampling, enables generation of Data trace address packets, that hold Daddr[15:0]: 0 Data trace address packets disabled. 1 Enable Data trace address packet generation. For more information see Address comparison functions on Arm TRM page C1-781.
Page 355 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MATCHED Comparator match: 0 No match. 1 Match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0.
Page 356 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.21 CM4_DWT_PID4 Description: Peripheral Identification Register 4. Address: 0xE0001FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 357 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.22 CM4_DWT_PID5 Description: Peripheral Identification Register 5. Address: 0xE0001FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 358 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.23 CM4_DWT_PID6 Description: Peripheral Identification Register 6. Address: 0xE0001FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 359 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.24 CM4_DWT_PID7 Description: Peripheral Identification Register 7. Address: 0xE0001FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 360 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.25 CM4_DWT_PID0 Description: Peripheral Identification Register 0. Address: 0xE0001FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 361 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.26 CM4_DWT_PID1 Description: Peripheral Identification Register 1. Address: 0xE0001FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 362 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.27 CM4_DWT_PID2 Description: Peripheral Identification Register 2. Address: 0xE0001FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x3B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 363 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.28 CM4_DWT_PID3 Description: Peripheral Identification Register 3. Address: 0xE0001FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 364 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.29 CM4_DWT_CID0 Description: Component Identification Register 0. Address: 0xE0001FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 365 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.30 CM4_DWT_CID1 Description: Component Identification Register 1. Address: 0xE0001FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 366 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.31 CM4_DWT_CID2 Description: Component Identification Register 2. Address: 0xE0001FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 367 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.2.32 CM4_DWT_CID3 Description: Component Identification Register 3. Address: 0xE0001FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 368 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3 FPB 4.13.3.1 CM4_FPB_CTRL Description: FlashPatch Control Register Address: 0xE0002000 Offset: Retention: Retained IsDeepSleep: Comment: The FP_CTRL Register characteristics are: Purpose: Provides FPB implementation information, and the global enable for the FPB unit. Usage constraints: There are no usage constraints.
Page 369 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 28:31 REV Flash Patch Breakpoint architecture revision: 0000 Flash Patch Breakpoint version 1. 0001 Flash Patch Breakpoint version 2. Supports breakpoints on any location in the 4GB address range. Technical Reference Manual 002-29852 Rev.
Page 370 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.2 CM4_FPB_REMAP Description: FlashPatch Remap register Address: 0xE0002004 Offset: Retention: Retained IsDeepSleep: Comment: The FP_REMAP register characteristics are: Purpose: Indicates whether the implementation supports flash patch remap, and if it does, holds the SRAM address for remap.
Page 371 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.3 CM4_FPB_COMP Description: FlashPatch Comparator register Address: 0xE0002008 Offset: Retention: Retained IsDeepSleep: Comment: The FP_COMPn register characteristics are: Purpose: Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-648.
Page 372 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.4 CM4_FPB_PID4 Description: Peripheral Identification Register 4. Address: 0xE0002FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 373 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.5 CM4_FPB_PID5 Description: Peripheral Identification Register 5. Address: 0xE0002FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 374 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.6 CM4_FPB_PID6 Description: Peripheral Identification Register 6. Address: 0xE0002FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 375 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.7 CM4_FPB_PID7 Description: Peripheral Identification Register 7. Address: 0xE0002FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 376 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.8 CM4_FPB_PID0 Description: Peripheral Identification Register 0. Address: 0xE0002FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 377 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.9 CM4_FPB_PID1 Description: Peripheral Identification Register 1. Address: 0xE0002FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 378 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.10 CM4_FPB_PID2 Description: Peripheral Identification Register 2. Address: 0xE0002FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x2B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 379 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.11 CM4_FPB_PID3 Description: Peripheral Identification Register 3. Address: 0xE0002FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 380 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.12 CM4_FPB_CID0 Description: Component Identification Register 0. Address: 0xE0002FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 381 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.13 CM4_FPB_CID1 Description: Component Identification Register 1. Address: 0xE0002FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 382 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.14 CM4_FPB_CID2 Description: Component Identification Register 2. Address: 0xE0002FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 383 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.3.15 CM4_FPB_CID3 Description: Component Identification Register 3. Address: 0xE0002FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 384 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4 SCS 4.13.4.1 CM4_SCS_ACTLR Description: Auxiliary Control Register Address: 0xE000E008 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 385 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.2 CM4_SCS_SYST_CSR Description: SysTick Control and Status Register Address: 0xE000E010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 386 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.3 CM4_SCS_SYST_RVR Description: SysTick Reload Value Register Address: 0xE000E014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 387 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.4 CM4_SCS_SYST_CVR Description: SysTick Current Value Register Address: 0xE000E018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 388 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.5 CM4_SCS_SYST_CALIB Description: SysTick Calibration value Register Address: 0xE000E01C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 389 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.6 CM4_SCS_NVIC_ISER Description: Interrupt Set-Enable Registers Address: 0xE000E100 Offset: 0x100 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 390 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.7 CM4_SCS_NVIC_ICER Description: Interrupt Clear-Enable Registers Address: 0xE000E180 Offset: 0x180 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 391 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.8 CM4_SCS_NVIC_ISPR Description: Interrupt Set-Pending Registers Address: 0xE000E200 Offset: 0x200 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 392 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.9 CM4_SCS_NVIC_ICPR Description: Interrupt Clear-Pending Registers Address: 0xE000E280 Offset: 0x280 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 393 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.10 CM4_SCS_NVIC_IABR Description: Interrupt Active Bit Registers Address: 0xE000E300 Offset: 0x300 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 394 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.11 CM4_SCS_NVIC_IPR Description: Interrupt Priority Registers Address: 0xE000E400 Offset: 0x400 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 395 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.12 CM4_SCS_CPUID Description: CPUID Base Register Address: 0xE000ED00 Offset: 0xD00 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 396 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.13 CM4_SCS_ICSR Description: Interrupt Control and State Register Address: 0xE000ED04 Offset: 0xD04 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 397 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.14 CM4_SCS_VTOR Description: Vector Table Offset Register Address: 0xE000ED08 Offset: 0xD08 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 398 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.15 CM4_SCS_AIRCR Description: Application Interrupt and Reset Control Register Address: 0xE000ED0C Offset: 0xD0C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 399 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.16 CM4_SCS_SCR Description: System Control Register Address: 0xE000ED10 Offset: 0xD10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 400 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.17 CM4_SCS_CCR Description: Configuration and Control Register Address: 0xE000ED14 Offset: 0xD14 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 401 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.18 CM4_SCS_SHPR1 Description: System Handler Priority Register 1 Address: 0xE000ED18 Offset: 0xD18 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 402 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.19 CM4_SCS_SHPR2 Description: System Handler Priority Register 2 Address: 0xE000ED1C Offset: 0xD1C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 403 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.20 CM4_SCS_SHPR3 Description: System Handler Priority Register 3 Address: 0xE000ED20 Offset: 0xD20 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 404 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.21 CM4_SCS_SHCSR Description: System Handler Control and State Register Address: 0xE000ED24 Offset: 0xD24 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 405 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.22 CM4_SCS_CFSR Description: Configurable Fault Status Register Address: 0xE000ED28 Offset: 0xD28 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 406 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.23 CM4_SCS_HFSR Description: HardFault Status Register Address: 0xE000ED2C Offset: 0xD2C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 407 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.24 CM4_SCS_DFSR Description: Debug Fault Status Register Address: 0xE000ED30 Offset: 0xD30 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 408 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.25 CM4_SCS_MMFAR Description: MemManage Fault Address Register Address: 0xE000ED34 Offset: 0xD34 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 409 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.26 CM4_SCS_BFAR Description: BusFault Address Register Address: 0xE000ED38 Offset: 0xD38 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 410 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.27 CM4_SCS_AFSR Description: Auxiliary Fault Status Register Address: 0xE000ED3C Offset: 0xD3C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 411 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.28 CM4_SCS_CPACR Description: Coprocessor Access Control Register Address: 0xE000ED88 Offset: 0xD88 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 412 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.29 CM4_SCS_MPU_TYPE Description: MPU Type Register Address: 0xE000ED90 Offset: 0xD90 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 413 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.30 CM4_SCS_MPU_CTRL Description: MPU Control Register Address: 0xE000ED94 Offset: 0xD94 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 414 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.31 CM4_SCS_MPU_RNR Description: MPU Region Number Register Address: 0xE000ED98 Offset: 0xD98 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 415 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.32 CM4_SCS_MPU_RBAR Description: MPU Region Base Address Register Address: 0xE000ED9C Offset: 0xD9C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 416 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.33 CM4_SCS_MPU_RASR Description: MPU Region Attribute and Size Register Address: 0xE000EDA0 Offset: 0xDA0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 417 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.34 CM4_SCS_MPU_RBAR_A1 Description: MPU alias registers Address: 0xE000EDA4 Offset: 0xDA4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 418 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.35 CM4_SCS_MPU_RASR_A1 Description: MPU alias registers Address: 0xE000EDA8 Offset: 0xDA8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 419 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.36 CM4_SCS_MPU_RBAR_A2 Description: MPU alias registers Address: 0xE000EDAC Offset: 0xDAC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 420 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.37 CM4_SCS_MPU_RASR_A2 Description: MPU alias registers Address: 0xE000EDB0 Offset: 0xDB0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 421 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.38 CM4_SCS_MPU_RBAR_A3 Description: MPU alias registers Address: 0xE000EDB4 Offset: 0xDB4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 422 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.39 CM4_SCS_MPU_RASR_A3 Description: MPU alias registers Address: 0xE000EDB8 Offset: 0xDB8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 423 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.40 CM4_SCS_DHCSR Description: Debug Halting Control and Status Register Address: 0xE000EDF0 Offset: 0xDF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 424 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.41 CM4_SCS_DCRSR Description: Debug Core Register Selector Register Address: 0xE000EDF4 Offset: 0xDF4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 425 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.42 CM4_SCS_DCRDR Description: Debug Core Register Data Register Address: 0xE000EDF8 Offset: 0xDF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 426 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.43 CM4_SCS_DEMCR Description: Debug Exception and Monitor Control Register Address: 0xE000EDFC Offset: 0xDFC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 427 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.44 CM4_SCS_STIR Description: Software Triggered Interrupt Register Address: 0xE000EF00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 428 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.45 CM4_SCS_FPCCR Description: FP Context Control Register Address: 0xE000EF34 Offset: 0xF34 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 429 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.46 CM4_SCS_FPCAR Description: FP Context Control Register Address: 0xE000EF38 Offset: 0xF38 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 430 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.47 CM4_SCS_FPDSCR Description: FP Context Control Register Address: 0xE000EF3C Offset: 0xF3C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 431 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.48 CM4_SCS_PID4 Description: Peripheral Identification Register 4 Address: 0xE000EFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 432 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.49 CM4_SCS_PID5 Description: Peripheral Identification Register 5 Address: 0xE000EFD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 433 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.50 CM4_SCS_PID6 Description: Peripheral Identification Register 6 Address: 0xE000EFD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 434 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.51 CM4_SCS_PID7 Description: Peripheral Identification Register 7 Address: 0xE000EFDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 435 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.52 CM4_SCS_PID0 Description: Peripheral Identification Register 0 Address: 0xE000EFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 436 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.53 CM4_SCS_PID1 Description: Peripheral Identification Register 1 Address: 0xE000EFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 437 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.54 CM4_SCS_PID2 Description: Peripheral Identification Register 2 Address: 0xE000EFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 438 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.55 CM4_SCS_PID3 Description: Peripheral Identification Register 3 Address: 0xE000EFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 439 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.56 CM4_SCS_CID0 Description: Component Identification Register 0 Address: 0xE000EFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 440 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.57 CM4_SCS_CID1 Description: Component Identification Register 1 Address: 0xE000EFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0xE0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 441 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.58 CM4_SCS_CID2 Description: Component Identification Register 2 Address: 0xE000EFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 442 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.4.59 CM4_SCS_CID3 Description: Component Identification Register 3 Address: 0xE000EFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 443 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5 ETM 4.13.5.1 CM4_ETM_CR Description: Main Control Register Address: 0xE0041000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 444 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.2 CM4_ETM_CCR Description: Main Control Register Address: 0xE0041004 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 445 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.3 CM4_ETM_TRIGGER Description: Trigger Event Register Address: 0xE0041008 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 446 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.4 CM4_ETM_SR Description: ETM Status Register Address: 0xE0041010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 447 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.5 CM4_ETM_SCR Description: System Configuration Register Address: 0xE0041014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 448 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.6 CM4_ETM_TEEVR Description: TraceEnable Event Register Address: 0xE0041020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 449 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.7 CM4_ETM_TECR1 Description: TraceEnable Control 1 Register Address: 0xE0041024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 450 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.8 CM4_ETM_FFLR Description: FIFOFULL Level Register Address: 0xE0041028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 451 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.9 CM4_ETM_CNTRLDVR1 Description: Free-running counter reload value Address: 0xE0041140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 452 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.10 CM4_ETM_SYNCFR Description: Synchronization Frequency Register Address: 0xE00411E0 Offset: 0x1E0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 453 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.11 CM4_ETM_IDR Description: ID Register Address: 0xE00411E4 Offset: 0x1E4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 454 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.12 CM4_ETM_CCER Description: Configuration Code Extension Register Address: 0xE00411E8 Offset: 0x1E8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 455 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.13 CM4_ETM_TESSEICR Description: TraceEnable Start/Stop EmbeddedICE Control Register Address: 0xE00411F0 Offset: 0x1F0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 456 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.14 CM4_ETM_TSEVR Description: Timestamp Event Register Address: 0xE00411F8 Offset: 0x1F8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 457 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.15 CM4_ETM_TRACEIDR Description: CoreSight Trace ID Register Address: 0xE0041200 Offset: 0x200 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 458 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.16 CM4_ETM_IDR2 Description: ETM ID Register 2 Address: 0xE0041208 Offset: 0x208 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 459 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.17 CM4_ETM_PDSR Description: Device Power-Down Status Register Address: 0xE0041314 Offset: 0x314 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 460 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.18 CM4_ETM_ITMISCIN Description: Integration Test Miscellaneous Inputs Address: 0xE0041EE0 Offset: 0xEE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 461 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.19 CM4_ETM_ITTRIGOUT Description: Integration Test Trigger Out Address: 0xE0041EE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 462 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.20 CM4_ETM_ITATBCTR2 Description: ETM Integration Test ATB Control 2 Address: 0xE0041EF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 463 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.21 CM4_ETM_ITATBCTR0 Description: ETM Integration Test ATB Control 0 Address: 0xE0041EF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 464 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.22 CM4_ETM_ITCTRL Description: Integration Mode Control Register Address: 0xE0041F00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 465 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.23 CM4_ETM_CLAIMSET Description: Claim Tag Set Register Address: 0xE0041FA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 466 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.24 CM4_ETM_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE0041FA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 467 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.25 CM4_ETM_LAR Description: Lock Access Register Address: 0xE0041FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 468 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.26 CM4_ETM_LSR Description: Lock Status Register Address: 0xE0041FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 469 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.27 CM4_ETM_AUTHSTATUS Description: Authentication Status Register Address: 0xE0041FB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 470 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.28 CM4_ETM_DEVTYPE Description: CoreSight Device Type Register Address: 0xE0041FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: 0x13 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 471 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.29 CM4_ETM_PID4 Description: Peripheral Identification Register 4. Address: 0xE0041FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 472 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.30 CM4_ETM_PID5 Description: Peripheral Identification Register 5. Address: 0xE0041FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 473 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.31 CM4_ETM_PID6 Description: Peripheral Identification Register 6. Address: 0xE0041FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 474 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.32 CM4_ETM_PID7 Description: Peripheral Identification Register 7. Address: 0xE0041FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 475 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.33 CM4_ETM_PID0 Description: Peripheral Identification Register 0. Address: 0xE0041FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0x25 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 476 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.34 CM4_ETM_PID1 Description: Peripheral Identification Register 1. Address: 0xE0041FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 477 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.35 CM4_ETM_PID2 Description: Peripheral Identification Register 2. Address: 0xE0041FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 478 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.36 CM4_ETM_PID3 Description: Peripheral Identification Register 3. Address: 0xE0041FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 479 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.37 CM4_ETM_CID0 Description: Component Identification Register 0. Address: 0xE0041FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 480 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.38 CM4_ETM_CID1 Description: Component Identification Register 1. Address: 0xE0041FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 481 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.39 CM4_ETM_CID2 Description: Component Identification Register 2. Address: 0xE0041FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 482 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.5.40 CM4_ETM_CID3 Description: Component Identification Register 3. Address: 0xE0041FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 483 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6 CM4CTI 4.13.6.1 CM4_CM4CTI_CTICONTROL Description: CTI Control Register Address: 0xE0042000 Offset: Retention: Retained IsDeepSleep: Comment: The CTI Control Register enables the CTI. Default: Bit-field Table Bits Name None [7:1] GLBEN [0:0] Bits Name None [15:8]...
Page 484 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.2 CM4_CM4CTI_CTIINTACK Description: CTI Interrupt Acknowledge Register Address: 0xE0042010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the CTITRIGOUT output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated.
Page 485 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.3 CM4_CM4CTI_CTIAPPSET Description: CTI Application Trigger Set Register Address: 0xE0042014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised, corresponding to the bit written to.
Page 486 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.4 CM4_CM4CTI_CTIAPPCLEAR Description: CTI Application Trigger Clear Register Address: 0xE0042018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Clear Register is write-only. A write to this register causes a channel event to be cleared, corresponding to the bit written to.
Page 487 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.5 CM4_CM4CTI_CTIAPPPULSE Description: CTI Application Pulse Register Address: 0xE004201C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse, one CTICLK period, to be generated, corresponding to the bit written to. The pulse external to the ECT can be extended to multi-cycle by the handshaking interface circuits.
Page 488 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.6 CM4_CM4CTI_CTIINEN Description: CTI Trigger to Channel Enable Registers Address: 0xE0042020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: The CTI Trigger to Channel Enable Registers enable the signaling of an event on CTM channels when the core issues a trigger, CTITRIGIN, to the CTI.
Page 489 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.7 CM4_CM4CTI_CTIOUTEN Description: CTI Channel to Trigger Enable Registers Address: 0xE00420A0 Offset: 0xA0 Retention: Retained IsDeepSleep: Comment: The CTI Channel to Trigger Enable Registers define which channels can generate a CTITRIGOUT output. There is one register for each of the eight CTITRIGOUT outputs. Within each register there is one bit for each of the four channels implemented.
Page 490 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.8 CM4_CM4CTI_CTITRIGINSTATUS Description: CTI Trigger In Status Register Address: 0xE0042130 Offset: 0x130 Retention: Retained IsDeepSleep: Comment: The CTI Trigger In Status Register provides the status of the CTITRIGIN inputs. Default: Bit-field Table Bits Name TRIGINSTATUS [7:0]...
Page 491 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.9 CM4_CM4CTI_CTITRIGOUTSTATUS Description: CTI Trigger Out Status Register Address: 0xE0042134 Offset: 0x134 Retention: Retained IsDeepSleep: Comment: The CTI Trigger Out Status Register provides the status of the CTITRIGOUT outputs. Default: Bit-field Table Bits Name TRIGOUTSTATUS [7:0]...
Page 492 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.10 CM4_CM4CTI_CTICHINSTATUS Description: CTI Channel In Status Register Address: 0xE0042138 Offset: 0x138 Retention: Retained IsDeepSleep: Comment: The CTI Channel In Status Register provides the status of the CTI CTICHIN inputs. Default: Bit-field Table Bits Name...
Page 493 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.11 CM4_CM4CTI_CTICHOUTSTATUS Description: CTI Channel Out Status Register Address: 0xE004213C Offset: 0x13C Retention: Retained IsDeepSleep: Comment: The CTI Channel Out Status Register provides the status of the CTI CTICHOUT outputs. Default: Bit-field Table Bits Name...
Page 494 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.12 CM4_CM4CTI_CTIGATE Description: Enable CTI Channel Gate Register Address: 0xE0042140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs.
Page 495 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.13 CM4_CM4CTI_ASICCTL Description: External Multiplexor Control Register Address: 0xE0042144 Offset: 0x144 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ASICCTL [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 496 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.14 CM4_CM4CTI_ITCHINACK Description: ITCHINACK Register Address: 0xE0042EDC Offset: 0xEDC Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHINACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 497 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.15 CM4_CM4CTI_ITTRIGINACK Description: ITTRIGINACK Register Address: 0xE0042EE0 Offset: 0xEE0 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGINACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 498 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.16 CM4_CM4CTI_ITCHOUT Description: ITCHOUT Register Address: 0xE0042EE4 Offset: 0xEE4 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUT [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 499 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.17 CM4_CM4CTI_ITTRIGOUT Description: ITTRIGOUT Register Address: 0xE0042EE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGOUT [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 500 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.18 CM4_CM4CTI_ITCHOUTACK Description: ITCHOUTACK Register Address: 0xE0042EEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUTACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 501 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.19 CM4_CM4CTI_ITTRIGOUTACK Description: ITTRIGOUTACK Register Address: 0xE0042EF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGOUTACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 502 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.20 CM4_CM4CTI_ITCHIN Description: ITCHIN Register Address: 0xE0042EF4 Offset: 0xEF4 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHIN [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 503 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.21 CM4_CM4CTI_ITTRIGIN Description: ITTRIGIN Register Address: 0xE0042EF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGIN [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 504 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.22 CM4_CM4CTI_ITCTRL Description: Integration Mode Control Register Address: 0xE0042F00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving.
Page 505 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.23 CM4_CM4CTI_CLAIMSET Description: Claim Tag Set Register Address: 0xE0042FA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
Page 506 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.24 CM4_CM4CTI_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE0042FA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
Page 507 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.25 CM4_CM4CTI_LOCKACCESS Description: Lock Access Register Address: 0xE0042FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: This is used to enable write access to device registers. If LOCKSTATUS[0] == 0x0 then this register is not present. Default: Bit-field Table Bits...
Page 508 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.26 CM4_CM4CTI_LOCKSTATUS Description: Lock Status Register Address: 0xE0042FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism.
Page 509 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.27 CM4_CM4CTI_AUTHSTATUS Description: Authentication Status Register Address: 0xE0042FB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register Default: Bit-field Table Bits...
Page 510 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.28 CM4_CM4CTI_DEVID Description: Device Configuration Register Address: 0xE0042FC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: This register is implementation-defined for each Part Number and Designer. This indicates the capabilities of the component. The entire 32-bit field can be used because the data width is determined by the particular component.
Page 511 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.29 CM4_CM4CTI_DEVTYPE Description: Device Type Identifier Register Address: 0xE0042FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: 0x14 indicates this device has a major type of debug control logic component (0x4) and sub- type corresponding to cross trigger (0x1).
Page 512 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.30 CM4_CM4CTI_PID4 Description: Peripheral Identification Register 4 Address: 0xE0042FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 513 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.31 CM4_CM4CTI_PID5 Description: Peripheral Identification Register 5 Address: 0xE0042FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 514 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.32 CM4_CM4CTI_PID6 Description: Peripheral Identification Register 6 Address: 0xE0042FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 515 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.33 CM4_CM4CTI_PID7 Description: Peripheral Identification Register 7 Address: 0xE0042FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 516 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.34 CM4_CM4CTI_PID0 Description: Peripheral Identification Register 0 Address: 0xE0042FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 517 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.35 CM4_CM4CTI_PID1 Description: Peripheral Identification Register 1 Address: 0xE0042FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 518 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.36 CM4_CM4CTI_PID2 Description: Peripheral Identification Register 2 Address: 0xE0042FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x4B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 519 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.37 CM4_CM4CTI_PID3 Description: Peripheral Identification Register 3 Address: 0xE0042FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 520 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.38 CM4_CM4CTI_CID0 Description: Component Identification Register 0 Address: 0xE0042FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 521 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.39 CM4_CM4CTI_CID1 Description: Component Identification Register 1 Address: 0xE0042FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 522 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.40 CM4_CM4CTI_CID2 Description: Component Identification Register 2 Address: 0xE0042FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 523 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.6.41 CM4_CM4CTI_CID3 Description: Component Identification Register 3 Address: 0xE0042FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 524 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7 ROM 4.13.7.1 CM4_ROM_SCS Description: CM4 CoreSight ROM Table Peripheral #0 Address: 0xE007F000 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF8F003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 525 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.2 CM4_ROM_DWT Description: CM4 CoreSight ROM Table Peripheral #1 Address: 0xE007F004 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF82003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 526 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.3 CM4_ROM_FPB Description: CM4 CoreSight ROM Table Peripheral #2 Address: 0xE007F008 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF83003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 527 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.4 CM4_ROM_ITM Description: CM4 CoreSight ROM Table Peripheral #3 Address: 0xE007F00C Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF81003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 528 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.5 CM4_ROM_CTI Description: CM4 CoreSight ROM Table Peripheral #4 Address: 0xE007F010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: 0xFFFC3003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 529 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.6 CM4_ROM_ETM Description: CM4 CoreSight ROM Table Peripheral #5 Address: 0xE007F014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Default: 0xFFFC2003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 530 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.7 CM4_ROM_CSMT Description: CM4 CoreSight ROM Table Memory Type Address: 0xE007FFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 531 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.8 CM4_ROM_PID4 Description: CM4 CoreSight ROM Table Peripheral ID #4 Address: 0xE007FFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 532 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.9 CM4_ROM_PID0 Description: CM4 CoreSight ROM Table Peripheral ID #0 Address: 0xE007FFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0xC0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 533 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.10 CM4_ROM_PID1 Description: CM4 CoreSight ROM Table Peripheral ID #1 Address: 0xE007FFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB4 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 534 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.11 CM4_ROM_PID2 Description: CM4 CoreSight ROM Table Peripheral ID #2 Address: 0xE007FFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 535 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.12 CM4_ROM_PID3 Description: CM4 CoreSight ROM Table Peripheral ID #3 Address: 0xE007FFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 536 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.13 CM4_ROM_CID0 Description: CM4 CoreSight ROM Table Component ID #0 Address: 0xE007FFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 537 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.14 CM4_ROM_CID1 Description: CM4 CoreSight ROM Table Component ID #1 Address: 0xE007FFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x10 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 538 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.15 CM4_ROM_CID2 Description: CM4 CoreSight ROM Table Component ID #2 Address: 0xE007FFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 539 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.7.16 CM4_ROM_CID3 Description: CM4 CoreSight ROM Table Component ID #3 Address: 0xE007FFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 540 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8 TRCCTI 4.13.8.1 CM4_TRCCTI_CTICONTROL Description: CTI Control Register Address: 0xE0080000 Offset: Retention: Retained IsDeepSleep: Comment: The CTI Control Register enables the CTI. Default: Bit-field Table Bits Name None [7:1] GLBEN [0:0] Bits Name None [15:8]...
Page 541 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.2 CM4_TRCCTI_CTIINTACK Description: CTI Interrupt Acknowledge Register Address: 0xE0080010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the CTITRIGOUT output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated.
Page 542 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.3 CM4_TRCCTI_CTIAPPSET Description: CTI Application Trigger Set Register Address: 0xE0080014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised, corresponding to the bit written to.
Page 543 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.4 CM4_TRCCTI_CTIAPPCLEAR Description: CTI Application Trigger Clear Register Address: 0xE0080018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: The CTI Application Trigger Clear Register is write-only. A write to this register causes a channel event to be cleared, corresponding to the bit written to.
Page 544 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.5 CM4_TRCCTI_CTIAPPPULSE Description: CTI Application Pulse Register Address: 0xE008001C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse, one CTICLK period, to be generated, corresponding to the bit written to. The pulse external to the ECT can be extended to multi-cycle by the handshaking interface circuits.
Page 545 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.6 CM4_TRCCTI_CTIINEN Description: CTI Trigger to Channel Enable Registers Address: 0xE0080020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: The CTI Trigger to Channel Enable Registers enable the signaling of an event on CTM channels when the core issues a trigger, CTITRIGIN, to the CTI.
Page 546 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.7 CM4_TRCCTI_CTIOUTEN Description: CTI Channel to Trigger Enable Registers Address: 0xE00800A0 Offset: 0xA0 Retention: Retained IsDeepSleep: Comment: The CTI Channel to Trigger Enable Registers define which channels can generate a CTITRIGOUT output. There is one register for each of the eight CTITRIGOUT outputs. Within each register there is one bit for each of the four channels implemented.
Page 547 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.8 CM4_TRCCTI_CTITRIGINSTATUS Description: CTI Trigger In Status Register Address: 0xE0080130 Offset: 0x130 Retention: Retained IsDeepSleep: Comment: The CTI Trigger In Status Register provides the status of the CTITRIGIN inputs. Default: Bit-field Table Bits Name TRIGINSTATUS [7:0]...
Page 548 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.9 CM4_TRCCTI_CTITRIGOUTSTATUS Description: CTI Trigger Out Status Register Address: 0xE0080134 Offset: 0x134 Retention: Retained IsDeepSleep: Comment: The CTI Trigger Out Status Register provides the status of the CTITRIGOUT outputs. Default: Bit-field Table Bits Name TRIGOUTSTATUS [7:0]...
Page 549 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.10 CM4_TRCCTI_CTICHINSTATUS Description: CTI Channel In Status Register Address: 0xE0080138 Offset: 0x138 Retention: Retained IsDeepSleep: Comment: The CTI Channel In Status Register provides the status of the CTI CTICHIN inputs. Default: Bit-field Table Bits Name...
Page 550 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.11 CM4_TRCCTI_CTICHOUTSTATUS Description: CTI Channel Out Status Register Address: 0xE008013C Offset: 0x13C Retention: Retained IsDeepSleep: Comment: The CTI Channel Out Status Register provides the status of the CTI CTICHOUT outputs. Default: Bit-field Table Bits Name...
Page 551 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.12 CM4_TRCCTI_CTIGATE Description: Enable CTI Channel Gate Register Address: 0xE0080140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs.
Page 552 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.13 CM4_TRCCTI_ASICCTL Description: External Multiplexor Control Register Address: 0xE0080144 Offset: 0x144 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ASICCTL [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 553 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.14 CM4_TRCCTI_ITCHINACK Description: ITCHINACK Register Address: 0xE0080EDC Offset: 0xEDC Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHINACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 554 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.15 CM4_TRCCTI_ITTRIGINACK Description: ITTRIGINACK Register Address: 0xE0080EE0 Offset: 0xEE0 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGINACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 555 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.16 CM4_TRCCTI_ITCHOUT Description: ITCHOUT Register Address: 0xE0080EE4 Offset: 0xEE4 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUT [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 556 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.17 CM4_TRCCTI_ITTRIGOUT Description: ITTRIGOUT Register Address: 0xE0080EE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: This register is a write-only register. Default: Bit-field Table Bits Name CTTRIGOUT [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 557 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.18 CM4_TRCCTI_ITCHOUTACK Description: ITCHOUTACK Register Address: 0xE0080EEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHOUTACK [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 558 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.19 CM4_TRCCTI_ITTRIGOUTACK Description: ITTRIGOUTACK Register Address: 0xE0080EF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGOUTACK [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 559 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.20 CM4_TRCCTI_ITCHIN Description: ITCHIN Register Address: 0xE0080EF4 Offset: 0xEF4 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name None [7:4] CTCHIN [3:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 560 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.21 CM4_TRCCTI_ITTRIGIN Description: ITTRIGIN Register Address: 0xE0080EF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: This register is a read-only register. Default: Bit-field Table Bits Name CTTRIGIN [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 561 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.22 CM4_TRCCTI_ITCTRL Description: Integration Mode Control Register Address: 0xE0080F00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving.
Page 562 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.23 CM4_TRCCTI_CLAIMSET Description: Claim Tag Set Register Address: 0xE0080FA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
Page 563 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.24 CM4_TRCCTI_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE0080FA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
Page 564 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.25 CM4_TRCCTI_LOCKACCESS Description: Lock Access Register Address: 0xE0080FB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: This is used to enable write access to device registers. If LOCKSTATUS[0] == 0x0 then this register is not present. Default: Bit-field Table Bits...
Page 565 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.26 CM4_TRCCTI_LOCKSTATUS Description: Lock Status Register Address: 0xE0080FB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism.
Page 566 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.27 CM4_TRCCTI_AUTHSTATUS Description: Authentication Status Register Address: 0xE0080FB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register Default: Bit-field Table Bits...
Page 567 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.28 CM4_TRCCTI_DEVID Description: Device Configuration Register Address: 0xE0080FC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: This register is implementation-defined for each Part Number and Designer. This indicates the capabilities of the component. The entire 32-bit field can be used because the data width is determined by the particular component.
Page 568 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.29 CM4_TRCCTI_DEVTYPE Description: Device Type Identifier Register Address: 0xE0080FCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: 0x14 indicates this device has a major type of debug control logic component (0x4) and sub- type corresponding to cross trigger (0x1).
Page 569 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.30 CM4_TRCCTI_PID4 Description: Peripheral Identification Register 4 Address: 0xE0080FD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 570 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.31 CM4_TRCCTI_PID5 Description: Peripheral Identification Register 5 Address: 0xE0080FD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 571 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.32 CM4_TRCCTI_PID6 Description: Peripheral Identification Register 6 Address: 0xE0080FD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 572 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.33 CM4_TRCCTI_PID7 Description: Peripheral Identification Register 7 Address: 0xE0080FDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 573 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.34 CM4_TRCCTI_PID0 Description: Peripheral Identification Register 0 Address: 0xE0080FE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 574 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.35 CM4_TRCCTI_PID1 Description: Peripheral Identification Register 1 Address: 0xE0080FE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 575 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.36 CM4_TRCCTI_PID2 Description: Peripheral Identification Register 2 Address: 0xE0080FE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x4B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 576 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.37 CM4_TRCCTI_PID3 Description: Peripheral Identification Register 3 Address: 0xE0080FEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 577 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.38 CM4_TRCCTI_CID0 Description: Component Identification Register 0 Address: 0xE0080FF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 578 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.39 CM4_TRCCTI_CID1 Description: Component Identification Register 1 Address: 0xE0080FF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 579 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.40 CM4_TRCCTI_CID2 Description: Component Identification Register 2 Address: 0xE0080FF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 580 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.8.41 CM4_TRCCTI_CID3 Description: Component Identification Register 3 Address: 0xE0080FFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 581 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9 CSTF 4.13.9.1 CM4_CSTF_CSTFCTL Description: Funnel Control Register Address: 0xE008C000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 582 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.2 CM4_CSTF_CSTFPCTL Description: Priority Control Register Address: 0xE008C004 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 583 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.3 CM4_CSTF_ITATBDATA0 Description: Integration Register Address: 0xE008CEEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 584 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.4 CM4_CSTF_ITATBCTR2 Description: Integration Register Address: 0xE008CEF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 585 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.5 CM4_CSTF_ITATBCTR1 Description: Integration Register Address: 0xE008CEF4 Offset: 0xEF4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 586 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.6 CM4_CSTF_ITATBCTR0 Description: Integration Register Address: 0xE008CEF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 587 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.7 CM4_CSTF_ITCTRL Description: Integration Mode Control Register Address: 0xE008CF00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 588 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.8 CM4_CSTF_CLAIMSET Description: Claim Tag Set Register Address: 0xE008CFA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 589 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.9 CM4_CSTF_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE008CFA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 590 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.10 CM4_CSTF_LOCKACCESS Description: Lock Access Register Address: 0xE008CFB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 591 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.11 CM4_CSTF_LOCKSTATUS Description: Lock Status Register Address: 0xE008CFB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 592 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.12 CM4_CSTF_AUTHSTATUS Description: Authentication Status Register Address: 0xE008CFB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 593 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.13 CM4_CSTF_DEVID Description: Device ID Address: 0xE008CFC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: Default: 0x38 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 594 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.14 CM4_CSTF_DEVTYPE Description: Device Type Identifier Register Address: 0xE008CFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: 0x12 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 595 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.15 CM4_CSTF_PID4 Description: Peripheral Identification Register 4 Address: 0xE008CFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 596 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.16 CM4_CSTF_PID5 Description: Peripheral Identification Register 5 Address: 0xE008CFD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 597 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.17 CM4_CSTF_PID6 Description: Peripheral Identification Register 6 Address: 0xE008CFD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 598 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.18 CM4_CSTF_PID7 Description: Peripheral Identification Register 7 Address: 0xE008CFDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 599 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.19 CM4_CSTF_PID0 Description: Peripheral Identification Register 0 Address: 0xE008CFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 600 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.20 CM4_CSTF_PID1 Description: Peripheral Identification Register 1 Address: 0xE008CFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 601 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.21 CM4_CSTF_PID2 Description: Peripheral Identification Register 2 Address: 0xE008CFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x2B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 602 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.22 CM4_CSTF_PID3 Description: Peripheral Identification Register 3 Address: 0xE008CFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 603 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.23 CM4_CSTF_CID0 Description: Component Identification Register 0 Address: 0xE008CFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 604 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.24 CM4_CSTF_CID1 Description: Component Identification Register 1 Address: 0xE008CFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 605 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.25 CM4_CSTF_CID2 Description: Component Identification Register 2 Address: 0xE008CFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 606 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.9.26 CM4_CSTF_CID3 Description: Component Identification Register 3 Address: 0xE008CFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 607 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10 ETB 4.13.10.1 CM4_ETB_ETBRDP Description: RAM Depth Register Address: 0xE008D004 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 608 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.2 CM4_ETB_ETBSTS Description: Status Register Address: 0xE008D00C Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 609 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.3 CM4_ETB_ETBRRD Description: RAM Read Data Register Address: 0xE008D010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 610 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.4 CM4_ETB_ETBRRP Description: RAM Read Pointer Register Address: 0xE008D014 Offset: 0x14 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 611 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.5 CM4_ETB_ETBRWP Description: RAM Write Pointer Register Address: 0xE008D018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 612 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.6 CM4_ETB_ETBTRG Description: Trigger Counter Register Address: 0xE008D01C Offset: 0x1C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 613 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.7 CM4_ETB_ETBCTL Description: Control Register Address: 0xE008D020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 614 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.8 CM4_ETB_ETBRWD Description: RAM Write Data Register Address: 0xE008D024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 615 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.9 CM4_ETB_ETBFFSR Description: Formatter and Flush Status Register Address: 0xE008D300 Offset: 0x300 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 616 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.10 CM4_ETB_ETBFFCR Description: Formatter and Flush Control Register Address: 0xE008D304 Offset: 0x304 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 617 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.11 CM4_ETB_ITMISCOP0 Description: Integration Register Address: 0xE008DEE0 Offset: 0xEE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 618 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.12 CM4_ETB_ITTRFLINACK Description: Integration Register Address: 0xE008DEE4 Offset: 0xEE4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 619 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.13 CM4_ETB_ITTRFLIN Description: Integration Register Address: 0xE008DEE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 620 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.14 CM4_ETB_ITATBDATA0 Description: Integration Register Address: 0xE008DEEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 621 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.15 CM4_ETB_ITATBCTR2 Description: Integration Register Address: 0xE008DEF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 622 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.16 CM4_ETB_ITATBCTR1 Description: Integration Register Address: 0xE008DEF4 Offset: 0xEF4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 623 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.17 CM4_ETB_ITATBCTR0 Description: Integration Register Address: 0xE008DEF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 624 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.18 CM4_ETB_ITCTRL Description: Integration Mode Control Register Address: 0xE008DF00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 625 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.19 CM4_ETB_CLAIMSET Description: Claim Tag Set Register Address: 0xE008DFA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
Page 626 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.20 CM4_ETB_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE008DFA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
Page 627 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.21 CM4_ETB_LOCKACCESS Description: Lock Access Register Address: 0xE008DFB0 Offset: 0xFB0 Retention: Retained IsDeepSleep: Comment: This is used to enable write access to device registers. If LOCKSTATUS[0] == 0x0 then this register is not present. Default: Bit-field Table Bits...
Page 628 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.22 CM4_ETB_LOCKSTATUS Description: Lock Status Register Address: 0xE008DFB4 Offset: 0xFB4 Retention: Retained IsDeepSleep: Comment: This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism.
Page 629 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.23 CM4_ETB_AUTHSTATUS Description: Authentication Status Register Address: 0xE008DFB8 Offset: 0xFB8 Retention: Retained IsDeepSleep: Comment: Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register Default: Bit-field Table Bits...
Page 630 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.24 CM4_ETB_DEVID Description: Device ID Address: 0xE008DFC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: This register is implementation-defined for each Part Number and Designer. This indicates the capabilities of the component. The entire 32-bit field can be used because the data width is determined by the particular component.
Page 631 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.25 CM4_ETB_DEVTYPE Description: Device Type Identifier Register Address: 0xE008DFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: 0x21 Bit-field Table Bits Name SUB_TYPE [7:4] CLASS [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 632 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.26 CM4_ETB_PID4 Description: Peripheral Identification Register 4 Address: 0xE008DFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 633 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.27 CM4_ETB_PID5 Description: Peripheral Identification Register 5 Address: 0xE008DFD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 634 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.28 CM4_ETB_PID6 Description: Peripheral Identification Register 6 Address: 0xE008DFD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 635 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.29 CM4_ETB_PID7 Description: Peripheral Identification Register 7 Address: 0xE008DFDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 636 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.30 CM4_ETB_PID0 Description: Peripheral Identification Register 0 Address: 0xE008DFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 637 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.31 CM4_ETB_PID1 Description: Peripheral Identification Register 1 Address: 0xE008DFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 638 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.32 CM4_ETB_PID2 Description: Peripheral Identification Register 2 Address: 0xE008DFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x3B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 639 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.33 CM4_ETB_PID3 Description: Peripheral Identification Register 3 Address: 0xE008DFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 640 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.34 CM4_ETB_CID0 Description: Component Identification Register 0 Address: 0xE008DFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 641 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.35 CM4_ETB_CID1 Description: Component Identification Register 1 Address: 0xE008DFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 642 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.36 CM4_ETB_CID2 Description: Component Identification Register 2 Address: 0xE008DFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 643 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.10.37 CM4_ETB_CID3 Description: Component Identification Register 3 Address: 0xE008DFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 644 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11 TPIU 4.13.11.1 CM4_TPIU_TPIU_SSPSR Description: Supported Parallel Port Size Register Address: 0xE008E000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 645 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.2 CM4_TPIU_TPIU_CSPSR Description: Current Parallel Port Size Register Address: 0xE008E004 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 646 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.3 CM4_TPIU_TPIU_ACPR Description: Asynchronous Clock Prescaler Register Address: 0xE008E010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 647 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.4 CM4_TPIU_TPIU_SPPR Description: Selected Pin Protocol Register Address: 0xE008E0F0 Offset: 0xF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 648 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.5 CM4_TPIU_TPIU_FFSR Description: Formatter and Flush Status Register Address: 0xE008E300 Offset: 0x300 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 649 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.6 CM4_TPIU_TPIU_FFCR Description: Formatter and Flush Control Register Address: 0xE008E304 Offset: 0x304 Retention: Retained IsDeepSleep: Comment: Default: 0x102 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 650 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.7 CM4_TPIU_TPIU_FSCR Description: Formatter Synchronization Counter Register Address: 0xE008E308 Offset: 0x308 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 651 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.8 CM4_TPIU_TRIGGER Description: TRIGGER register Address: 0xE008EEE8 Offset: 0xEE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 652 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.9 CM4_TPIU_FIFO_DATA_0 Description: Integration ETM Data Address: 0xE008EEEC Offset: 0xEEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 653 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.10 CM4_TPIU_ITATBCTR2 Description: Integration Register Address: 0xE008EEF0 Offset: 0xEF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 654 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.11 CM4_TPIU_ITATBCTR0 Description: Integration Register Address: 0xE008EEF8 Offset: 0xEF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name Default or...
Page 655 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.12 CM4_TPIU_FIFO_DATA_1 Description: Integration ITM Data Address: 0xE008EEFC Offset: 0xEFC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields Bits Name...
Page 656 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.13 CM4_TPIU_ITCTRL Description: Integration Mode Control Register Address: 0xE008EF00 Offset: 0xF00 Retention: Retained IsDeepSleep: Comment: This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving.
Page 657 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.14 CM4_TPIU_CLAIMSET Description: Claim Tag Set Register Address: 0xE008EFA0 Offset: 0xFA0 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
Page 658 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.15 CM4_TPIU_CLAIMCLR Description: Claim Tag Clear Register Address: 0xE008EFA4 Offset: 0xFA4 Retention: Retained IsDeepSleep: Comment: This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
Page 659 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.16 CM4_TPIU_DEVID Description: Device ID Address: 0xE008EFC8 Offset: 0xFC8 Retention: Retained IsDeepSleep: Comment: This register is implementation-defined for each Part Number and Designer. This indicates the capabilities of the component. The entire 32-bit field can be used because the data width is determined by the particular component.
Page 660 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.17 CM4_TPIU_DEVTYPE Description: Device Type Identifier Register Address: 0xE008EFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: 0x11 Bit-field Table Bits Name SUB_TYPE [7:4] CLASS [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 661 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.18 CM4_TPIU_PID4 Description: Peripheral Identification Register 4 Address: 0xE008EFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 662 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.19 CM4_TPIU_PID5 Description: Peripheral Identification Register 5 Address: 0xE008EFD4 Offset: 0xFD4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 663 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.20 CM4_TPIU_PID6 Description: Peripheral Identification Register 6 Address: 0xE008EFD8 Offset: 0xFD8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 664 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.21 CM4_TPIU_PID7 Description: Peripheral Identification Register 7 Address: 0xE008EFDC Offset: 0xFDC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 665 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.22 CM4_TPIU_PID0 Description: Peripheral Identification Register 0 Address: 0xE008EFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0x23 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 666 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.23 CM4_TPIU_PID1 Description: Peripheral Identification Register 1 Address: 0xE008EFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB9 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 667 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.24 CM4_TPIU_PID2 Description: Peripheral Identification Register 2 Address: 0xE008EFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: 0x3B Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 668 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.25 CM4_TPIU_PID3 Description: Peripheral Identification Register 3 Address: 0xE008EFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECOREVNUM [7:4] None [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 669 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.26 CM4_TPIU_CID0 Description: Component Identification Register 0 Address: 0xE008EFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 670 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.27 CM4_TPIU_CID1 Description: Component Identification Register 1 Address: 0xE008EFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x90 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 671 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.28 CM4_TPIU_CID2 Description: Component Identification Register 2 Address: 0xE008EFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24] Bit-fields...
Page 672 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.11.29 CM4_TPIU_CID3 Description: Component Identification Register 3 Address: 0xE008EFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 673 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12 ROMTABLE 4.13.12.1 CM4_ROMTABLE_TRC_CTI Description: CM4 CoreSight ROM Table Peripheral #0 Address: 0xE00FF000 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF81003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 674 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.2 CM4_ROMTABLE_TRC_CSTF Description: CM4 CoreSight ROM Table Peripheral #1 Address: 0xE00FF004 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF8D003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 675 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.3 CM4_ROMTABLE_TRC_ETB Description: CM4 CoreSight ROM Table Peripheral #2 Address: 0xE00FF008 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF8E003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 676 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.4 CM4_ROMTABLE_TRC_TPIU Description: CM4 CoreSight ROM Table Peripheral #3 Address: 0xE00FF00C Offset: Retention: Retained IsDeepSleep: Comment: Default: 0xFFF8F003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 677 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.5 CM4_ROMTABLE_CM4 Description: CM4 CoreSight ROM Table Peripheral #4 Address: 0xE00FF010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: 0xFFF80003 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 678 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.6 CM4_ROMTABLE_CSMT Description: CM4 CoreSight ROM Table Memory Type Address: 0xE00FFFCC Offset: 0xFCC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name VALUE [31:24]...
Page 679 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.7 CM4_ROMTABLE_PID4 Description: CM4 CoreSight ROM Table Peripheral ID #4 Address: 0xE00FFFD0 Offset: 0xFD0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 680 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.8 CM4_ROMTABLE_PID0 Description: CM4 CoreSight ROM Table Peripheral ID #0 Address: 0xE00FFFE0 Offset: 0xFE0 Retention: Retained IsDeepSleep: Comment: Default: 0xC0 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 681 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.9 CM4_ROMTABLE_PID1 Description: CM4 CoreSight ROM Table Peripheral ID #1 Address: 0xE00FFFE4 Offset: 0xFE4 Retention: Retained IsDeepSleep: Comment: Default: 0xB4 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 682 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.10 CM4_ROMTABLE_PID2 Description: CM4 CoreSight ROM Table Peripheral ID #2 Address: 0xE00FFFE8 Offset: 0xFE8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 683 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.11 CM4_ROMTABLE_PID3 Description: CM4 CoreSight ROM Table Peripheral ID #3 Address: 0xE00FFFEC Offset: 0xFEC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 684 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.12 CM4_ROMTABLE_CID0 Description: CM4 CoreSight ROM Table Component ID #0 Address: 0xE00FFFF0 Offset: 0xFF0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 685 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.13 CM4_ROMTABLE_CID1 Description: CM4 CoreSight ROM Table Component ID #1 Address: 0xE00FFFF4 Offset: 0xFF4 Retention: Retained IsDeepSleep: Comment: Default: 0x10 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 686 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.14 CM4_ROMTABLE_CID2 Description: CM4 CoreSight ROM Table Component ID #2 Address: 0xE00FFFF8 Offset: 0xFF8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits Name...
Page 687 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 4.13.12.15 CM4_ROMTABLE_CID3 Description: CM4 CoreSight ROM Table Component ID #3 Address: 0xE00FFFFC Offset: 0xFFC Retention: Retained IsDeepSleep: Comment: Default: 0xB1 Bit-field Table Bits Name VALUE [7:0] Bits Name VALUE [15:8] Bits Name VALUE [23:16] Bits...
Page 688 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5 CPUSS Description CPU subsystem (CPUSS) Base Address 0x40200000 Size 0x10000 Slave Num MMIO2 - 0 Register Name Address Permission Description CPUSS_IDENTITY 0x40200000 FULL Identity CPUSS_CM4_STATUS 0x40200004 FULL CM4 status CPUSS_CM4_CLOCK_CTL 0x40200008 FULL CM4 clock control CPUSS_CM4_CTL...
Page 689 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_BUFF_CTL 0x40201500 FULL Buffer control CPUSS_SYSTICK_CTL 0x40201600 FULL SysTick timer control CPUSS_CAL_SUP_SET 0x40201800 FULL Calibration support set and read CPUSS_CAL_SUP_CLR 0x40201804 FULL Calibration support clear and reset CPUSS_CM0_PC_CTL 0x40202000 READ CM0+ protection context control...
Page 690 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL51 0x402080CC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL52 0x402080D0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL53 0x402080D4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL54 0x402080D8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL55 0x402080DC FULL CM0+ system interrupt control...
Page 691 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL114 0x402081C8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL115 0x402081CC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL116 0x402081D0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL117 0x402081D4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL118 0x402081D8 FULL CM0+ system interrupt control...
Page 692 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL177 0x402082C4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL178 0x402082C8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL179 0x402082CC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL180 0x402082D0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL181 0x402082D4 FULL CM0+ system interrupt control...
Page 693 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL240 0x402083C0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL241 0x402083C4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL242 0x402083C8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL243 0x402083CC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL244 0x402083D0 FULL CM0+ system interrupt control...
Page 694 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL303 0x402084BC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL304 0x402084C0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL305 0x402084C4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL306 0x402084C8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL307 0x402084CC FULL CM0+ system interrupt control...
Page 695 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM0_SYSTEM_INT_CTL366 0x402085B8 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL367 0x402085BC FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL368 0x402085C0 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL369 0x402085C4 FULL CM0+ system interrupt control CPUSS_CM0_SYSTEM_INT_CTL370 0x402085C8 FULL CM0+ system interrupt control...
Page 696 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL46 0x4020A0B8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL47 0x4020A0BC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL48 0x4020A0C0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL49 0x4020A0C4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL50 0x4020A0C8 FULL CM4 system interrupt control...
Page 697 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL109 0x4020A1B4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL110 0x4020A1B8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL111 0x4020A1BC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL112 0x4020A1C0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL113 0x4020A1C4 FULL CM4 system interrupt control...
Page 698 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL172 0x4020A2B0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL173 0x4020A2B4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL174 0x4020A2B8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL175 0x4020A2BC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL176 0x4020A2C0 FULL CM4 system interrupt control...
Page 699 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL235 0x4020A3AC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL236 0x4020A3B0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL237 0x4020A3B4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL238 0x4020A3B8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL239 0x4020A3BC FULL CM4 system interrupt control...
Page 700 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL298 0x4020A4A8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL299 0x4020A4AC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL300 0x4020A4B0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL301 0x4020A4B4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL302 0x4020A4B8 FULL CM4 system interrupt control...
Page 701 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CPUSS_CM4_SYSTEM_INT_CTL361 0x4020A5A4 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL362 0x4020A5A8 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL363 0x4020A5AC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL364 0x4020A5B0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL365 0x4020A5B4 FULL CM4 system interrupt control...
Page 702 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1 Register Details 5.1.1 CPUSS_IDENTITY Description: Identity Address: 0x40200000 Offset: Retention: Not Retained IsDeepSleep: Comment: This register is typically used by SW that is executed on different bus masters or with different protection contexts.
Page 703 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.2 CPUSS_CM4_STATUS Description: CM4 status Address: 0x40200004 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: 0x13 Bit-field Table Bits Name None [7:5] None [3:2] SLEEPDEEP SLEEPING _DONE [1:1] [0:0] [4:4] Bits Name None [15:8] Bits Name...
Page 704 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.3 CPUSS_CM4_CLOCK_CTL Description: CM4 clock control Address: 0x40200008 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name FAST_INT_DIV [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name Default or...
Page 705 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.4 CPUSS_CM4_CTL Description: CM4 control Address: 0x4020000C Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name IDC_MASK None [30:29] IXC_MASK UFC_MASK DZC_MASK...
Page 706 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt.
Page 707 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.5 CPUSS_CM4_INT0_STATUS Description: CM4 interrupt 0 status Address: 0x40200100 Offset: 0x100 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 708 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.6 CPUSS_CM4_INT1_STATUS Description: CM4 interrupt 1 status Address: 0x40200104 Offset: 0x104 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 709 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.7 CPUSS_CM4_INT2_STATUS Description: CM4 interrupt 2 status Address: 0x40200108 Offset: 0x108 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 710 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.8 CPUSS_CM4_INT3_STATUS Description: CM4 interrupt 3 status Address: 0x4020010C Offset: 0x10C Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 711 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.9 CPUSS_CM4_INT4_STATUS Description: CM4 interrupt 4 status Address: 0x40200110 Offset: 0x110 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 712 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.10 CPUSS_CM4_INT5_STATUS Description: CM4 interrupt 5 status Address: 0x40200114 Offset: 0x114 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 713 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.11 CPUSS_CM4_INT6_STATUS Description: CM4 interrupt 6 status Address: 0x40200118 Offset: 0x118 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 714 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.12 CPUSS_CM4_INT7_STATUS Description: CM4 interrupt 7 status Address: 0x4020011C Offset: 0x11C Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 715 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.13 CPUSS_CM4_VECTOR_TABLE_BASE Description: CM4 vector table base Address: 0x40200200 Offset: 0x200 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [9:8] Bits Name ADDR22 [23:16] Bits Name ADDR22 [31:24] Bit-fields...
Page 716 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.14 CPUSS_CM4_NMI_CTL Description: CM4 NMI control Address: 0x40200240 Offset: 0x240 Retention: Retained IsDeepSleep: Comment: Note that multiple (four) CM4_NMI_CTL registers exist, allowing for multiple (four) system interrupts to be connected to the CPU NMI. The four selected system interrupts are logically OR'd into a single CPU NMI input.
Page 717 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.15 CPUSS_CM0_CTL Description: CM0+ control Address: 0x40201000 Offset: 0x1000 Retention: Retained IsDeepSleep: Comment: Default: 0xFA050002 Bit-field Table Bits Name None [7:2] ENABLED [1:1] _STALL [0:0] Bits Name None [15:8] Bits Name VECTKEYSTAT [23:16] Bits Name...
Page 718 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.16 CPUSS_CM0_STATUS Description: CM0+ status Address: 0x40201004 Offset: 0x1004 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] SLEEPDEEP SLEEPING [1:1] [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name...
Page 719 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.17 CPUSS_CM0_CLOCK_CTL Description: CM0+ clock control Address: 0x40201008 Offset: 0x1008 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name SLOW_INT_DIV [15:8] Bits Name None [23:16] Bits Name PERI_INT_DIV [31:24] Bit-fields Bits Name...
Page 720 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.18 CPUSS_CM0_INT0_STATUS Description: CM0+ interrupt 0 status Address: 0x40201100 Offset: 0x1100 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 721 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.19 CPUSS_CM0_INT1_STATUS Description: CM0+ interrupt 1 status Address: 0x40201104 Offset: 0x1104 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 722 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.20 CPUSS_CM0_INT2_STATUS Description: CM0+ interrupt 2 status Address: 0x40201108 Offset: 0x1108 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 723 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.21 CPUSS_CM0_INT3_STATUS Description: CM0+ interrupt 3 status Address: 0x4020110C Offset: 0x110C Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 724 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.22 CPUSS_CM0_INT4_STATUS Description: CM0+ interrupt 4 status Address: 0x40201110 Offset: 0x1110 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 725 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.23 CPUSS_CM0_INT5_STATUS Description: CM0+ interrupt 5 status Address: 0x40201114 Offset: 0x1114 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 726 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.24 CPUSS_CM0_INT6_STATUS Description: CM0+ interrupt 6 status Address: 0x40201118 Offset: 0x1118 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 727 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.25 CPUSS_CM0_INT7_STATUS Description: CM0+ interrupt 7 status Address: 0x4020111C Offset: 0x111C Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SYSTEM_INT_IDX [7:0] Bits Name None [15:10] SYSTEM_INT_IDX [9:8] Bits Name None [23:16] Bits Name...
Page 728 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.26 CPUSS_CM0_VECTOR_TABLE_BASE Description: CM0+ vector table base Address: 0x40201120 Offset: 0x1120 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name ADDR24 [15:8] Bits Name ADDR24 [23:16] Bits Name ADDR24 [31:24] Bit-fields...
Page 729 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.27 CPUSS_CM0_NMI_CTL Description: CM0+ NMI control Address: 0x40201140 Offset: 0x1140 Retention: Retained IsDeepSleep: Comment: Note that multiple (four) CM0_NMI_CTL registers exist, allowing for multiple (four) system interrupts to be connected to the CPU NMI. The four selected system interrupts are logically OR'd into a single CPU NMI input.
Page 730 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.28 CPUSS_CM4_PWR_CTL Description: CM4 power control Address: 0x40201200 Offset: 0x1200 Retention: Retained IsDeepSleep: Comment: This register controls the CM4 power state. Please note that this register must not be modified while the CM4 is executing; doing so may corrupt/abort pending bus transaction by the CM4 and cause unexpected behaviors in the system, including deadlock.
Page 731 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.29 CPUSS_CM4_PWR_DELAY_CTL Description: CM4 power control Address: 0x40201204 Offset: 0x1204 Retention: Retained IsDeepSleep: Comment: Default: 0x12C Bit-field Table Bits Name UP [7:0] Bits Name None [15:10] UP [9:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 732 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.30 CPUSS_RAM0_CTL0 Description: RAM 0 control Address: 0x40201300 Offset: 0x1300 Retention: Retained IsDeepSleep: Comment: This register is for the CPUSS system SRAM controller 0. Default: 0x30001 Bit-field Table Bits Name None [7:2] SLOW_WS [1:0] Bits Name...
Page 733 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.31 CPUSS_RAM0_STATUS Description: RAM 0 status Address: 0x40201304 Offset: 0x1304 Retention: Retained IsDeepSleep: Comment: This register is for the CPUSS system SRAM controller 0. Default: Bit-field Table Bits Name None [7:1] _EMPTY [0:0] Bits...
Page 734 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.32 CPUSS_RAM0_PWR_MACRO_CTL Description: RAM 0 power control Address: 0x40201340 Offset: 0x1340 Retention: Retained IsDeepSleep: Comment: These registers control the system SRAM 0 power states of a single macro. System SRAM 0 consists of up to sixteen 32 kB macros.
Page 735 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.33 CPUSS_RAM1_CTL0 Description: RAM 1 control Address: 0x40201380 Offset: 0x1380 Retention: Retained IsDeepSleep: Comment: This register is for the CPUSS system SRAM controller 1. Default: 0x30001 Bit-field Table Bits Name None [7:2] SLOW_WS [1:0] Bits Name...
Page 736 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.34 CPUSS_RAM1_STATUS Description: RAM 1 status Address: 0x40201384 Offset: 0x1384 Retention: Retained IsDeepSleep: Comment: This register is for the CPUSS system SRAM controller 1. Default: Bit-field Table Bits Name None [7:1] _EMPTY [0:0] Bits...
Page 737 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.35 CPUSS_RAM1_PWR_CTL Description: RAM 1 power control Address: 0x40201388 Offset: 0x1388 Retention: Retained IsDeepSleep: Comment: This register controls the system SRAM 1 power states. System SRAM 1 consists of a single power partition.
Page 738 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.36 CPUSS_RAM_PWR_DELAY_CTL Description: Power up delay used for all SRAM power domains Address: 0x402013C0 Offset: 0x13C0 Retention: Retained IsDeepSleep: Comment: Default: 0x96 Bit-field Table Bits Name UP [7:0] Bits Name None [15:10] UP [9:8] Bits Name...
Page 739 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.37 CPUSS_ROM_CTL Description: ROM control Address: 0x402013C4 Offset: 0x13C4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] SLOW_WS [1:0] Bits Name None [15:10] FAST_WS [9:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 740 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.38 CPUSS_ECC_CTL Description: ECC control Address: 0x402013C8 Offset: 0x13C8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name WORD_ADDR [7:0] Bits Name WORD_ADDR [15:8] Bits Name WORD_ADDR [23:16] Bits Name PARITY [31:25] WORD _ADDR [24:24]...
Page 741 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.39 CPUSS_PRODUCT_ID Description: Product identifier and version (same as CoreSight RomTables) Address: 0x40201400 Offset: 0x1400 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name FAMILY_ID [7:0] Bits Name None [15:12] FAMILY_ID [11:8] Bits Name MINOR_REV [23:20]...
Page 742 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.40 CPUSS_DP_STATUS Description: Debug port status Address: 0x40201410 Offset: 0x1410 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:3] SWJ_JTAG _SEL [2:2] _DEBUG _CONNE _EN [1:1] CTED [0:0] Bits Name None [15:8]...
Page 743 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.41 CPUSS_AP_CTL Description: Access port control Address: 0x40201414 Offset: 0x1414 Retention: Retained IsDeepSleep: Comment: This register enables individual test controller access ports (AP). Note that the system AP is further controlled by a AP specific MPU, the SMPU and PPUs. The system AP MPU may be programmed to provide no or limited test controller access capabilities.
Page 744 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum SYS_DISABLE RW1S Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.
Page 745 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.42 CPUSS_BUFF_CTL Description: Buffer control Address: 0x40201500 Offset: 0x1500 Retention: Retained IsDeepSleep: Comment: The ARM CM0+ and CM4 CPUs use bufferable write transfers to the peripherals by default. As a result, CPU completion of the write transfer does not guarantee that the write transfer reached its destination, as the transfer may be buffered/posted in the bus infrastructure.
Page 746 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.43 CPUSS_SYSTICK_CTL Description: SysTick timer control Address: 0x40201600 Offset: 0x1600 Retention: Retained IsDeepSleep: Comment: The CPUSS SYSTICK_CTL MMIO NOREF, SKEW, TENMS register fields are reflected in the CPU's SysTick timer calibration register: SYST_CALIB (the CLOCK_SOURCE field is NOT reflected and only SW accessible through the CPUSS SYSTICK_CTL MMIO register).
Page 747 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.44 CPUSS_CAL_SUP_SET Description: Calibration support set and read Address: 0x40201800 Offset: 0x1800 Retention: Retained IsDeepSleep: Comment: For ETAS support Default: Bit-field Table Bits Name DATA [7:0] Bits Name DATA [15:8] Bits Name DATA [23:16] Bits...
Page 748 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.45 CPUSS_CAL_SUP_CLR Description: Calibration support clear and reset Address: 0x40201804 Offset: 0x1804 Retention: Retained IsDeepSleep: Comment: Read side effect: reset on read (even when read from debug host) Default: Bit-field Table Bits Name DATA [7:0]...
Page 749 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.46 CPUSS_CM0_PC_CTL Description: CM0+ protection context control Address: 0x40202000 Offset: 0x2000 Retention: Retained IsDeepSleep: Comment: The CM0_PC_CTL and CM0_Pci_HANDLER register are typically initialized by the boot code. Default: Bit-field Table Bits Name None [7:4] VALID [3:0]...
Page 750 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.47 CPUSS_CM0_PC0_HANDLER Description: CM0+ protection context 0 handler Address: 0x40202040 Offset: 0x2040 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 751 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.48 CPUSS_CM0_PC1_HANDLER Description: CM0+ protection context 1 handler Address: 0x40202044 Offset: 0x2044 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 752 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.49 CPUSS_CM0_PC2_HANDLER Description: CM0+ protection context 2 handler Address: 0x40202048 Offset: 0x2048 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 753 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.50 CPUSS_CM0_PC3_HANDLER Description: CM0+ protection context 3 handler Address: 0x4020204C Offset: 0x204C Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 754 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.51 CPUSS_PROTECTION Description: Protection status Address: 0x402020C4 Offset: 0x20C4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:3] STATE [2:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 755 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.52 CPUSS_TRIM_ROM_CTL Description: ROM trim control Address: 0x40202100 Offset: 0x2100 Retention: Retained IsDeepSleep: Comment: This register is used to trim ALL ROM memories in the device. Different operating Voltages may require different trim settings. Default: Bit-field Table Bits...
Page 756 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.53 CPUSS_TRIM_RAM_CTL Description: RAM trim control Address: 0x40202104 Offset: 0x2104 Retention: Retained IsDeepSleep: Comment: This register is used to trim ALL RAM memories in the device. Different operating Voltages may require different trim settings. Default: Bit-field Table Bits...
Page 757 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 0:31 TRIM RAM_TRIM For ARM RAMs the bits are defined as follows _DEFAULT [2:0] EMA: Extra Margin Adjustment (0 is the fastest setting) [4:3] EMAW: Extra Margin Adjustment for Writes (0 is the fastest setting) [7:5] CTL_BIAS: Control the bias circuit in the SRAM power switches for SRAMC0: 0=OFF, 7=max...
Page 758 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.54 CPUSS_CM0_SYSTEM_INT_CTL Description: CM0+ system interrupt control Address: 0x40208000 Offset: 0x8000 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:3] CPU_INT_IDX [2:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name CPU_INT...
Page 759 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 5.1.55 CPUSS_CM4_SYSTEM_INT_CTL Description: CM4 system interrupt control Address: 0x4020A000 Offset: 0xA000 Retention: Retained IsDeepSleep: Comment: Only present when SYSTEM_IRQ_PRESENT is '1' Default: Bit-field Table Bits Name None [7:3] CPU_INT_IDX [2:0] Bits Name None [15:8] Bits...
Page 760 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 6 CRYPTO Description Cryptography component Base Address 0x40100000 Size 0x10000 Slave Num MMIO1 - 0 7 CXPI Description CXPI Base Address 0x40510000 Size 0x10000 Slave Num MMIO5 - 1 Register Name Address Permission Description CXPI0_ERROR_CTL...
Page 761 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description CXPI0_CH1_INTR_MASKED 0x405181CC FULL Interrupt masked 7.3 CH 2 This instance is not available in the following part numbers: CYT2BL3BAS, CYT2BL3BAE, CYT2BL3CAS, CYT2BL3CAE. Register Name Address Permission Description CXPI0_CH2_CTL0 0x40518200 FULL Control 0...
Page 762 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5 Register Details 7.5.1 CXPI_ERROR_CTL Description: Error control Address: 0x40510000 Offset: Retention: Retained IsDeepSleep: Comment: This register supports error functionality: it enables HW injected channel transmitter errors. The receiver should detect these errors and report these errors through activation of corresponding interrupt causes.
Page 763 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum ENABLED Error injection enable: '0': Disabled. '1': Enabled. Technical Reference Manual 002-29852 Rev. *B 2022-04-18...
Page 764 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.2 CXPI_TEST_CTL Description: Test control Address: 0x40510004 Offset: Retention: Retained IsDeepSleep: Comment: This register support test functionality. Default: Bit-field Table Bits Name None [7:5] CH_IDX [4:0] Bits Name None [15:8] Bits Name None [23:17] MODE...
Page 765 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MODE Test mode: '0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external cxpi transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device.
Page 766 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3 CH 7.5.3.1 CXPI_CH_CTL0 Description: Control 0 Address: 0x40518000 Offset: Retention: Retained IsDeepSleep: Comment: This register contains controls for CXPI such as modes, offset, or master/slave. This register is programmed before the start of a transaction and not to be change inflight of any transaction.
Page 767 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum FILTER_EN RX filter enable (for 'cxpi_rx_in') '0': No filter '1': Median 3 (default value) operates on the last three 'cxpi_rx_in' values. The sequences '000', '001', '010', and '100' result in a filtered value '0'.
Page 768 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum BIT_ERROR_IGNORE Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted. '1': Message transfer is NOT aborted. Note: This field does NOT effect the reporting of the bit error through INTR/STATUS.TX_BIT_ERROR;...
Page 769 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.2 CXPI_CH_CTL1 Description: Control 1 Address: 0x40518004 Offset: Retention: Retained IsDeepSleep: Comment: This register contains controls on configuring different timing controls at Data link layer. This register is programmed before the start of a transaction and not to be change inflight of any transaction.
Page 770 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 22:30 T_OFFSET The value of offset that is used for sampling the 'rx'. The value of this counter is used in HW as below. - 0 : means 1 clock after detecting falling edge of 'rx' - 1 : means 2 clocks after detecting falling edge of 'rx' - 7 : means 8 clocks after detecting falling edge of 'rx' - 15 : means 16 clocks after detecting falling edge of...
Page 771 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.3 CXPI_CH_CTL2 Description: Control 2 Address: 0x40518008 Offset: Retention: Retained IsDeepSleep: Comment: This register contains fields for number of retries. These registers are programmed before the start of a transaction and not to be change inflight of any transaction.
Page 772 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 30:31 TIMEOUT_SEL Timeout Select. '0' - Timeout check is disabled. HW clears timeout counter. '1' - Timeout check is enabled and HW will refer to TIMEOUT_LENGTH as number of Tbits allowed between header and response.
Page 773 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.4 CXPI_CH_STATUS Description: Status Address: 0x4051800C Offset: Retention: Not Retained IsDeepSleep: Comment: The register fields are not retained. This is to ensure that they come up as '0' after coming out of DeepSleep system power mode.
Page 774 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RX_BUSY Receiver busy. - Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. - Set to '0' on successful completion of previous commands or when an error is detected.
Page 775 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.5 CXPI_CH_CMD Description: Command Address: 0x40518010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The register fields are retained. When a CXPI channel is disabled (CTL0.ENABLED is set to '0'), HW sets all the register fields to '0'. The following restrictions apply when programming the commands: - If both TX_HEADER and RX_HEADER are set to 1'b1 together with both IFS_WAIT and RXPIDZERO_CHECK_EN set to 1'b0, TX_HEADER will have higher precedence.
Page 776 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Name None [15:10] _RESPON _HEADER SE [9:9] [8:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name Default or Description Enum TX_HEADER SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error (such as bit error if bit_ignore=0,...
Page 777 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum SLEEP RW1S RW1C SW sets this field to '1' to direct HW to sleep mode. HW transits from Normal to Sleep upon SLEEP=1 and both TX and RX is idle. HW sets this field to '0' when it is in Sleep mode.
Page 778 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum IFS_WAIT RW1C SW sets this field to '1' to wait for IFS. HW clears this field to '0' after it detects logical '1' based on IFS. HW will keep this field to '1' if it detects logical '0' before fulfilling the number of logical '1' required.
Page 779 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.6 CXPI_CH_TX_RX_STATUS Description: TX/RX status Address: 0x40518040 Offset: 0x40 Retention: Not Retained IsDeepSleep: Comment: Default: 0x5000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:18] RX_IN TX_IN [17:17] [16:16]...
Page 780 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.7 CXPI_CH_TXPID_FI Description: TXPID and Frame Information Address: 0x40518050 Offset: 0x50 Retention: Retained IsDeepSleep: Comment: This registers holds information on TX's PID, FI and DLCEXT Default: Bit-field Table Bits Name PID [7:0] Bits Name FI [15:8]...
Page 781 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.8 CXPI_CH_RXPID_FI Description: RXPID and Frame Information Address: 0x40518054 Offset: 0x54 Retention: Not Retained IsDeepSleep: Comment: This register holds information on RX's PID, Frame Information, and DLCEXT. Default: Bit-field Table Bits Name PID [7:0] Bits...
Page 782 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.9 CXPI_CH_CRC Description: Address: 0x40518058 Offset: 0x58 Retention: Not Retained IsDeepSleep: Comment: This register holds the CRC bytes for RX and TX. Default: Bit-field Table Bits Name RXCRC1 [7:0] Bits Name RXCRC2 [15:8] Bits Name...
Page 783 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.10 CXPI_CH_TX_FIFO_CTL Description: TX FIFO control Address: 0x40518080 Offset: 0x80 Retention: Not Retained IsDeepSleep: Comment: This is the transmit fifo control register Default: Bit-field Table Bits Name None [7:5] TRIGGER_LEVEL [4:0] Bits Name None [15:8]...
Page 784 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.11 CXPI_CH_TX_FIFO_STATUS Description: TX FIFO status Address: 0x40518084 Offset: 0x84 Retention: Not Retained IsDeepSleep: Comment: This is the transmit fifo control register Default: Bit-field Table Bits Name None [7:5] USED [4:0] Bits Name None [15:8]...
Page 785 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.12 CXPI_CH_TX_FIFO_WR Description: TX FIFO write Address: 0x40518088 Offset: 0x88 Retention: Not Retained IsDeepSleep: Comment: This register supports 32-bit access only Default: Bit-field Table Bits Name DATA [7:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 786 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.13 CXPI_CH_RX_FIFO_CTL Description: RX FIFO control Address: 0x405180A0 Offset: 0xA0 Retention: Not Retained IsDeepSleep: Comment: This register contains RX FIFO control Default: Bit-field Table Bits Name None [7:5] TRIGGER_LEVEL [4:0] Bits Name None [15:8] Bits...
Page 787 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.14 CXPI_CH_RX_FIFO_STATUS Description: RX FIFO status Address: 0x405180A4 Offset: 0xA4 Retention: Not Retained IsDeepSleep: Comment: This register contains RX FIFO control Default: Bit-field Table Bits Name None [7:5] USED [4:0] Bits Name None [15:8] Bits...
Page 788 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.15 CXPI_CH_RX_FIFO_RD Description: RX FIFO read Address: 0x405180A8 Offset: 0xA8 Retention: Not Retained IsDeepSleep: Comment: This register supports a single 32-bit access to read data fields. Default: Bit-field Table Bits Name DATA [7:0] Bits Name...
Page 789 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.16 CXPI_CH_RX_FIFO_RD_SILENT Description: RX FIFO silent read Address: 0x405180AC Offset: 0xAC Retention: Not Retained IsDeepSleep: Comment: This register supports a single 32-bit access to read data fields. Default: Bit-field Table Bits Name DATA [7:0] Bits...
Page 790 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.17 CXPI_CH_INTR Description: Interrupt Address: 0x405180C0 Offset: 0xC0 Retention: Not Retained IsDeepSleep: Comment: The register fields are not retained. This is to ensure that they come up as '0' after coming out of DeepSleep system power mode.
Page 791 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TX_HEADER_DONE RW1C RW1S HW sets this field to '1', when a frame header (PID field or PType field) is transmitted (the CMD.TX_HEADER is completed). Specifically: - For PID transmission only and without prior transmission of PTYPE, when followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this...
Page 792 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TX_HEADER_ARB_LOST RW1C RW1S HW sets this field to '1', when it detects arbitration lost after the number of retries has exceed the maximum allowed retries. Note: The ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated and...
Page 793 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RX_OVERFLOW RW1C RW1S HW sets this field to '1', when the RX data is _ERROR overwritten by HW before the SW reads from it. In CXPI spec, this error is denoted as overrun error.
Page 794 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.18 CXPI_CH_INTR_SET Description: Interrupt set Address: 0x405180C4 Offset: 0xC4 Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. Default: Bit-field Table Bits Name None [7:5] TX_FIFO_T None [2:2] RIGGER _WAKEUP _RESPON...
Page 795 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TIMEOUT RW1S Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). TX_HEADER_ARB_LOST RW1S Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).
Page 796 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.19 CXPI_CH_INTR_MASK Description: Interrupt mask Address: 0x405180C8 Offset: 0xC8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:5] TX_FIFO_T None [2:2] RIGGER _WAKEUP _RESPON _HEADER [4:4] _DONE SE_DONE _DONE [3:3] [1:1] [0:0]...
Page 797 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum TX_DATA_LENGTH Mask for corresponding field in INTR register. _ERROR RX_OVERFLOW Mask for corresponding field in INTR register. _ERROR TX_OVERFLOW_ERROR RW Mask for corresponding field in INTR register. RX_UNDERFLOW Mask for corresponding field in INTR register.
Page 798 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 7.5.3.20 CXPI_CH_INTR_MASKED Description: Interrupt masked Address: 0x405180CC Offset: 0xCC Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers. This register allows SW to read the status of all mask enabled interrupt causes with a single load operation, rather than two load operations: one for INTR and one for INTR_MASK.
Page 799 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum RX_HEADER_PID_DONE R Logical AND of corresponding INTR and INTR_MASK fields. TXRX_COMPLETE Logical AND of corresponding INTR and INTR_MASK fields. TIMEOUT Logical AND of corresponding INTR and INTR_MASK fields.
Page 800 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8 DMAC Description DMAC Base Address 0x402A0000 Size 0x10000 Slave Num MMIO2 - 9 Register Name Address Permission Description DMAC_CTL 0x402A0000 FULL Control DMAC_ACTIVE 0x402A0008 FULL Active channels 8.1 CH 0 Register Name Address Permission Description...
Page 801 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DMAC_CH2_TR_CMD 0x402A1228 FULL Channle software trigger DMAC_CH2_DESCR_STATUS 0x402A1240 FULL Channel descriptor status DMAC_CH2_DESCR_CTL 0x402A1260 FULL Channel descriptor control DMAC_CH2_DESCR_SRC 0x402A1264 FULL Channel descriptor source DMAC_CH2_DESCR_DST 0x402A1268 FULL Channel descriptor destination DMAC_CH2_DESCR_X_SIZE 0x402A126C FULL...
Page 802 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5 Register Details 8.5.1 DMAC_CTL Description: Control Address: 0x402A0000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name ENABLED None [30:24] [31:31]...
Page 803 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.2 DMAC_ACTIVE Description: Active channels Address: 0x402A0008 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ACTIVE [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name Default or...
Page 804 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3 CH 8.5.3.1 DMAC_CH_CTL Description: Channel control Address: 0x402A1000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name PC [7:4] None [3:3] B [2:2] NS [1:1] P [0:0] Bits Name None [15:10] PRIO [9:8] Bits...
Page 805 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
Page 806 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.2 DMAC_CH_IDX Description: Channel current indices Address: 0x402A1010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name X [7:0] Bits Name X [15:8] Bits Name Y [23:16] Bits Name Y [31:24] Bit-fields Bits Name...
Page 807 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.3 DMAC_CH_SRC Description: Channel current source address Address: 0x402A1014 Offset: 0x14 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 808 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.4 DMAC_CH_DST Description: Channel current destination address Address: 0x402A1018 Offset: 0x18 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 809 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.5 DMAC_CH_CURR Description: Channel current descriptor pointer Address: 0x402A1020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [1:0] Bits Name PTR [15:8] Bits Name PTR [23:16] Bits Name PTR [31:24] Bit-fields...
Page 810 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.6 DMAC_CH_TR_CMD Description: Channle software trigger Address: 0x402A1028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] ACTIVATE [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 811 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.7 DMAC_CH_DESCR_STATUS Description: Channel descriptor status Address: 0x402A1040 Offset: 0x40 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name VALID None [30:24]...
Page 812 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.8 DMAC_CH_DESCR_CTL Description: Channel descriptor control Address: 0x402A1060 Offset: 0x60 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_CTL of the currently active descriptor. Default: Bit-field Table Bits Name TR_IN_TYPE [7:6] TR_OUT_TYPE [5:4] INTR_TYPE [3:2] WAIT_FOR_DEACT [1:0] Bits...
Page 813 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum INTR_TYPE Undefined Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer. '1': An interrupt is generated after a single 1D transfer or a memory copy transfer - If the descriptor type is 'single', the interrupt is generated after a single transfer.
Page 814 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum DATA_PREFETCH Undefined Source data prefetch: '0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. '1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO.
Page 815 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum DST_TRANSFER_SIZE Undefined Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width.
Page 816 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.9 DMAC_CH_DESCR_SRC Description: Channel descriptor source Address: 0x402A1064 Offset: 0x64 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_SRC of the currently active descriptor. Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits...
Page 817 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.10 DMAC_CH_DESCR_DST Description: Channel descriptor destination Address: 0x402A1068 Offset: 0x68 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_DST of the currently active descriptor. Default: Bit-field Table Bits Name ADDR [7:0] Bits Name ADDR [15:8] Bits...
Page 818 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.11 DMAC_CH_DESCR_X_SIZE Description: Channel descriptor X size Address: 0x402A106C Offset: 0x6C Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_X_SIZE of the currently active descriptor. Default: Bit-field Table Bits Name X_COUNT [7:0] Bits Name X_COUNT [15:8]...
Page 819 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.12 DMAC_CH_DESCR_X_INCR Description: Channel descriptor X increment Address: 0x402A1070 Offset: 0x70 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_X_INCR of the currently active descriptor. Default: Bit-field Table Bits Name SRC_X [7:0] Bits Name SRC_X [15:8]...
Page 820 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.13 DMAC_CH_DESCR_Y_SIZE Description: Channel descriptor Y size Address: 0x402A1074 Offset: 0x74 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_Y_SIZE of the currently active descriptor. Default: Bit-field Table Bits Name Y_COUNT [7:0] Bits Name Y_COUNT [15:8]...
Page 821 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.14 DMAC_CH_DESCR_Y_INCR Description: Channel descriptor Y increment Address: 0x402A1078 Offset: 0x78 Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_Y_INCR of the currently active descriptor. Default: Bit-field Table Bits Name SRC_Y [7:0] Bits Name SRC_Y [15:8]...
Page 822 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.15 DMAC_CH_DESCR_NEXT Description: Channel descriptor next pointer Address: 0x402A107C Offset: 0x7C Retention: Not Retained IsDeepSleep: Comment: Copy of DESCR_NEXT_PTR of the currently active descriptor. For a single transfer descriptor type, this register is at offset 0x0c. For a 1D transfer descriptor type, this register is at offset 0x14.
Page 823 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.16 DMAC_CH_INTR Description: Interrupt Address: 0x402A1080 Offset: 0x80 Retention: Not Retained IsDeepSleep: Comment: The register fields are not retained. This is to ensure that they come up as '0' after coming out of DeepSleep system power mode.
Page 824 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.17 DMAC_CH_INTR_SET Description: Interrupt set Address: 0x402A1084 Offset: 0x84 Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. Default: Bit-field Table Bits Name DESCR ACTIVE CURR_PTR DST_BUS SRC_BUS COMPLETIO _BUS...
Page 825 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.18 DMAC_CH_INTR_MASK Description: Interrupt mask Address: 0x402A1088 Offset: 0x88 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DESCR ACTIVE CURR_PTR DST_BUS SRC_BUS COMPLETIO _BUS _NULL [5:5] _MISAL _MISAL _ERROR _ERROR N [0:0] _ERROR _DISABLED...
Page 826 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 8.5.3.19 DMAC_CH_INTR_MASKED Description: Interrupt masked Address: 0x402A108C Offset: 0x8C Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers. This register allows SW to read the status of all mask enabled interrupt causes with a single load operation, rather than two load operations: one for INTR and one for INTR_MASK.
Page 827 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9 DW 9.1 DW 0 Description Datawire Controller Base Address 0x40280000 Size 0x10000 Slave Num MMIO2 - 7 9.1.1 0 Register Name Address Permission Description DW0_CTL0 0x40280000 FULL Control DW0_STATUS0 0x40280004 FULL Status DW0_ACT_DESCR_CTL0 0x40280020 FULL...
Page 828 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT2_CH_CURR_PTR 0x4028808C FULL Channel current descriptor pointer DW0_CH_STRUCT2_INTR 0x40288090 FULL Interrupt DW0_CH_STRUCT2_INTR_SET 0x40288094 FULL Interrupt set DW0_CH_STRUCT2_INTR_MASK 0x40288098 FULL Interrupt mask DW0_CH_STRUCT2_INTR_MASKED 0x4028809C FULL Interrupt masked DW0_CH_STRUCT2_SRAM_DATA0 0x402880A0 FULL SRAM data 0...
Page 829 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT6_TR_CMD 0x402881A8 FULL Channel software trigger 9.1.1.8 CH_STRUCT 7 Register Name Address Permission Description DW0_CH_STRUCT7_CH_CTL 0x402881C0 FULL Channel control DW0_CH_STRUCT7_CH_STATUS 0x402881C4 FULL Channel status DW0_CH_STRUCT7_CH_IDX 0x402881C8 FULL Channel current indices DW0_CH_STRUCT7_CH_CURR_PTR 0x402881CC FULL...
Page 830 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT11_CH_CURR_PTR 0x402882CC FULL Channel current descriptor pointer DW0_CH_STRUCT11_INTR 0x402882D0 FULL Interrupt DW0_CH_STRUCT11_INTR_SET 0x402882D4 FULL Interrupt set DW0_CH_STRUCT11_INTR_MASK 0x402882D8 FULL Interrupt mask DW0_CH_STRUCT11_INTR_MASKED 0x402882DC FULL Interrupt masked DW0_CH_STRUCT11_SRAM_DATA0 0x402882E0 FULL SRAM data 0...
Page 831 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT15_TR_CMD 0x402883E8 FULL Channel software trigger 9.1.1.17 CH_STRUCT 16 Register Name Address Permission Description DW0_CH_STRUCT16_CH_CTL 0x40288400 FULL Channel control DW0_CH_STRUCT16_CH_STATUS 0x40288404 FULL Channel status DW0_CH_STRUCT16_CH_IDX 0x40288408 FULL Channel current indices DW0_CH_STRUCT16_CH_CURR_PTR 0x4028840C FULL...
Page 832 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT20_CH_CURR_PTR 0x4028850C FULL Channel current descriptor pointer DW0_CH_STRUCT20_INTR 0x40288510 FULL Interrupt DW0_CH_STRUCT20_INTR_SET 0x40288514 FULL Interrupt set DW0_CH_STRUCT20_INTR_MASK 0x40288518 FULL Interrupt mask DW0_CH_STRUCT20_INTR_MASKED 0x4028851C FULL Interrupt masked DW0_CH_STRUCT20_SRAM_DATA0 0x40288520 FULL SRAM data 0...
Page 833 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT24_TR_CMD 0x40288628 FULL Channel software trigger 9.1.1.26 CH_STRUCT 25 Register Name Address Permission Description DW0_CH_STRUCT25_CH_CTL 0x40288640 FULL Channel control DW0_CH_STRUCT25_CH_STATUS 0x40288644 FULL Channel status DW0_CH_STRUCT25_CH_IDX 0x40288648 FULL Channel current indices DW0_CH_STRUCT25_CH_CURR_PTR 0x4028864C FULL...
Page 834 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT29_CH_CURR_PTR 0x4028874C FULL Channel current descriptor pointer DW0_CH_STRUCT29_INTR 0x40288750 FULL Interrupt DW0_CH_STRUCT29_INTR_SET 0x40288754 FULL Interrupt set DW0_CH_STRUCT29_INTR_MASK 0x40288758 FULL Interrupt mask DW0_CH_STRUCT29_INTR_MASKED 0x4028875C FULL Interrupt masked DW0_CH_STRUCT29_SRAM_DATA0 0x40288760 FULL SRAM data 0...
Page 835 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT33_TR_CMD 0x40288868 FULL Channel software trigger 9.1.1.35 CH_STRUCT 34 Register Name Address Permission Description DW0_CH_STRUCT34_CH_CTL 0x40288880 FULL Channel control DW0_CH_STRUCT34_CH_STATUS 0x40288884 FULL Channel status DW0_CH_STRUCT34_CH_IDX 0x40288888 FULL Channel current indices DW0_CH_STRUCT34_CH_CURR_PTR 0x4028888C FULL...
Page 836 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT38_CH_CURR_PTR 0x4028898C FULL Channel current descriptor pointer DW0_CH_STRUCT38_INTR 0x40288990 FULL Interrupt DW0_CH_STRUCT38_INTR_SET 0x40288994 FULL Interrupt set DW0_CH_STRUCT38_INTR_MASK 0x40288998 FULL Interrupt mask DW0_CH_STRUCT38_INTR_MASKED 0x4028899C FULL Interrupt masked DW0_CH_STRUCT38_SRAM_DATA0 0x402889A0 FULL SRAM data 0...
Page 837 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT42_TR_CMD 0x40288AA8 FULL Channel software trigger 9.1.1.44 CH_STRUCT 43 Register Name Address Permission Description DW0_CH_STRUCT43_CH_CTL 0x40288AC0 FULL Channel control DW0_CH_STRUCT43_CH_STATUS 0x40288AC4 FULL Channel status DW0_CH_STRUCT43_CH_IDX 0x40288AC8 FULL Channel current indices DW0_CH_STRUCT43_CH_CURR_PTR 0x40288ACC FULL...
Page 838 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT47_CH_CURR_PTR 0x40288BCC FULL Channel current descriptor pointer DW0_CH_STRUCT47_INTR 0x40288BD0 FULL Interrupt DW0_CH_STRUCT47_INTR_SET 0x40288BD4 FULL Interrupt set DW0_CH_STRUCT47_INTR_MASK 0x40288BD8 FULL Interrupt mask DW0_CH_STRUCT47_INTR_MASKED 0x40288BDC FULL Interrupt masked DW0_CH_STRUCT47_SRAM_DATA0 0x40288BE0 FULL SRAM data 0...
Page 839 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT51_TR_CMD 0x40288CE8 FULL Channel software trigger 9.1.1.53 CH_STRUCT 52 Register Name Address Permission Description DW0_CH_STRUCT52_CH_CTL 0x40288D00 FULL Channel control DW0_CH_STRUCT52_CH_STATUS 0x40288D04 FULL Channel status DW0_CH_STRUCT52_CH_IDX 0x40288D08 FULL Channel current indices DW0_CH_STRUCT52_CH_CURR_PTR 0x40288D0C FULL...
Page 840 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT56_CH_CURR_PTR 0x40288E0C FULL Channel current descriptor pointer DW0_CH_STRUCT56_INTR 0x40288E10 FULL Interrupt DW0_CH_STRUCT56_INTR_SET 0x40288E14 FULL Interrupt set DW0_CH_STRUCT56_INTR_MASK 0x40288E18 FULL Interrupt mask DW0_CH_STRUCT56_INTR_MASKED 0x40288E1C FULL Interrupt masked DW0_CH_STRUCT56_SRAM_DATA0 0x40288E20 FULL SRAM data 0...
Page 841 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT60_TR_CMD 0x40288F28 FULL Channel software trigger 9.1.1.62 CH_STRUCT 61 Register Name Address Permission Description DW0_CH_STRUCT61_CH_CTL 0x40288F40 FULL Channel control DW0_CH_STRUCT61_CH_STATUS 0x40288F44 FULL Channel status DW0_CH_STRUCT61_CH_IDX 0x40288F48 FULL Channel current indices DW0_CH_STRUCT61_CH_CURR_PTR 0x40288F4C FULL...
Page 842 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT65_CH_CURR_PTR 0x4028904C FULL Channel current descriptor pointer DW0_CH_STRUCT65_INTR 0x40289050 FULL Interrupt DW0_CH_STRUCT65_INTR_SET 0x40289054 FULL Interrupt set DW0_CH_STRUCT65_INTR_MASK 0x40289058 FULL Interrupt mask DW0_CH_STRUCT65_INTR_MASKED 0x4028905C FULL Interrupt masked DW0_CH_STRUCT65_SRAM_DATA0 0x40289060 FULL SRAM data 0...
Page 843 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT69_TR_CMD 0x40289168 FULL Channel software trigger 9.1.1.71 CH_STRUCT 70 Register Name Address Permission Description DW0_CH_STRUCT70_CH_CTL 0x40289180 FULL Channel control DW0_CH_STRUCT70_CH_STATUS 0x40289184 FULL Channel status DW0_CH_STRUCT70_CH_IDX 0x40289188 FULL Channel current indices DW0_CH_STRUCT70_CH_CURR_PTR 0x4028918C FULL...
Page 844 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT74_CH_CURR_PTR 0x4028928C FULL Channel current descriptor pointer DW0_CH_STRUCT74_INTR 0x40289290 FULL Interrupt DW0_CH_STRUCT74_INTR_SET 0x40289294 FULL Interrupt set DW0_CH_STRUCT74_INTR_MASK 0x40289298 FULL Interrupt mask DW0_CH_STRUCT74_INTR_MASKED 0x4028929C FULL Interrupt masked DW0_CH_STRUCT74_SRAM_DATA0 0x402892A0 FULL SRAM data 0...
Page 845 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT78_TR_CMD 0x402893A8 FULL Channel software trigger 9.1.1.80 CH_STRUCT 79 Register Name Address Permission Description DW0_CH_STRUCT79_CH_CTL 0x402893C0 FULL Channel control DW0_CH_STRUCT79_CH_STATUS 0x402893C4 FULL Channel status DW0_CH_STRUCT79_CH_IDX 0x402893C8 FULL Channel current indices DW0_CH_STRUCT79_CH_CURR_PTR 0x402893CC FULL...
Page 846 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT83_CH_CURR_PTR 0x402894CC FULL Channel current descriptor pointer DW0_CH_STRUCT83_INTR 0x402894D0 FULL Interrupt DW0_CH_STRUCT83_INTR_SET 0x402894D4 FULL Interrupt set DW0_CH_STRUCT83_INTR_MASK 0x402894D8 FULL Interrupt mask DW0_CH_STRUCT83_INTR_MASKED 0x402894DC FULL Interrupt masked DW0_CH_STRUCT83_SRAM_DATA0 0x402894E0 FULL SRAM data 0...
Page 847 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW0_CH_STRUCT87_TR_CMD 0x402895E8 FULL Channel software trigger 9.1.1.89 CH_STRUCT 88 Register Name Address Permission Description DW0_CH_STRUCT88_CH_CTL 0x40289600 FULL Channel control DW0_CH_STRUCT88_CH_STATUS 0x40289604 FULL Channel status DW0_CH_STRUCT88_CH_IDX 0x40289608 FULL Channel current indices DW0_CH_STRUCT88_CH_CURR_PTR 0x4028960C FULL...
Page 848 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Slave Num MMIO2 - 8 9.2.1 0 Register Name Address Permission Description DW1_CTL0 0x40290000 FULL Control DW1_STATUS0 0x40290004 FULL Status DW1_ACT_DESCR_CTL0 0x40290020 FULL Active descriptor control DW1_ACT_DESCR_SRC0 0x40290024 FULL Active descriptor source DW1_ACT_DESCR_DST0 0x40290028 FULL Active descriptor destination...
Page 849 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.2.1.4 CH_STRUCT 3 Register Name Address Permission Description DW1_CH_STRUCT3_CH_CTL 0x402980C0 FULL Channel control DW1_CH_STRUCT3_CH_STATUS 0x402980C4 FULL Channel status DW1_CH_STRUCT3_CH_IDX 0x402980C8 FULL Channel current indices DW1_CH_STRUCT3_CH_CURR_PTR 0x402980CC FULL Channel current descriptor pointer DW1_CH_STRUCT3_INTR 0x402980D0 FULL Interrupt...
Page 850 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW1_CH_STRUCT7_INTR_SET 0x402981D4 FULL Interrupt set DW1_CH_STRUCT7_INTR_MASK 0x402981D8 FULL Interrupt mask DW1_CH_STRUCT7_INTR_MASKED 0x402981DC FULL Interrupt masked DW1_CH_STRUCT7_SRAM_DATA0 0x402981E0 FULL SRAM data 0 DW1_CH_STRUCT7_SRAM_DATA1 0x402981E4 FULL SRAM data 1 DW1_CH_STRUCT7_TR_CMD 0x402981E8 FULL Channel software trigger...
Page 851 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.2.1.13 CH_STRUCT 12 Register Name Address Permission Description DW1_CH_STRUCT12_CH_CTL 0x40298300 FULL Channel control DW1_CH_STRUCT12_CH_STATUS 0x40298304 FULL Channel status DW1_CH_STRUCT12_CH_IDX 0x40298308 FULL Channel current indices DW1_CH_STRUCT12_CH_CURR_PTR 0x4029830C FULL Channel current descriptor pointer DW1_CH_STRUCT12_INTR 0x40298310 FULL Interrupt...
Page 852 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW1_CH_STRUCT16_INTR_SET 0x40298414 FULL Interrupt set DW1_CH_STRUCT16_INTR_MASK 0x40298418 FULL Interrupt mask DW1_CH_STRUCT16_INTR_MASKED 0x4029841C FULL Interrupt masked DW1_CH_STRUCT16_SRAM_DATA0 0x40298420 FULL SRAM data 0 DW1_CH_STRUCT16_SRAM_DATA1 0x40298424 FULL SRAM data 1 DW1_CH_STRUCT16_TR_CMD 0x40298428 FULL Channel software trigger...
Page 853 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.2.1.22 CH_STRUCT 21 Register Name Address Permission Description DW1_CH_STRUCT21_CH_CTL 0x40298540 FULL Channel control DW1_CH_STRUCT21_CH_STATUS 0x40298544 FULL Channel status DW1_CH_STRUCT21_CH_IDX 0x40298548 FULL Channel current indices DW1_CH_STRUCT21_CH_CURR_PTR 0x4029854C FULL Channel current descriptor pointer DW1_CH_STRUCT21_INTR 0x40298550 FULL Interrupt...
Page 854 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW1_CH_STRUCT25_INTR_SET 0x40298654 FULL Interrupt set DW1_CH_STRUCT25_INTR_MASK 0x40298658 FULL Interrupt mask DW1_CH_STRUCT25_INTR_MASKED 0x4029865C FULL Interrupt masked DW1_CH_STRUCT25_SRAM_DATA0 0x40298660 FULL SRAM data 0 DW1_CH_STRUCT25_SRAM_DATA1 0x40298664 FULL SRAM data 1 DW1_CH_STRUCT25_TR_CMD 0x40298668 FULL Channel software trigger...
Page 855 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.2.1.31 CH_STRUCT 30 Register Name Address Permission Description DW1_CH_STRUCT30_CH_CTL 0x40298780 FULL Channel control DW1_CH_STRUCT30_CH_STATUS 0x40298784 FULL Channel status DW1_CH_STRUCT30_CH_IDX 0x40298788 FULL Channel current indices DW1_CH_STRUCT30_CH_CURR_PTR 0x4029878C FULL Channel current descriptor pointer DW1_CH_STRUCT30_INTR 0x40298790 FULL Interrupt...
Page 856 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW1_CH_STRUCT34_INTR_SET 0x40298894 FULL Interrupt set DW1_CH_STRUCT34_INTR_MASK 0x40298898 FULL Interrupt mask DW1_CH_STRUCT34_INTR_MASKED 0x4029889C FULL Interrupt masked DW1_CH_STRUCT34_SRAM_DATA0 0x402988A0 FULL SRAM data 0 DW1_CH_STRUCT34_SRAM_DATA1 0x402988A4 FULL SRAM data 1 DW1_CH_STRUCT34_TR_CMD 0x402988A8 FULL Channel software trigger...
Page 857 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.2.1.40 CH_STRUCT 39 Register Name Address Permission Description DW1_CH_STRUCT39_CH_CTL 0x402989C0 FULL Channel control DW1_CH_STRUCT39_CH_STATUS 0x402989C4 FULL Channel status DW1_CH_STRUCT39_CH_IDX 0x402989C8 FULL Channel current indices DW1_CH_STRUCT39_CH_CURR_PTR 0x402989CC FULL Channel current descriptor pointer DW1_CH_STRUCT39_INTR 0x402989D0 FULL Interrupt...
Page 858 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description DW1_CH_STRUCT43_INTR_SET 0x40298AD4 FULL Interrupt set DW1_CH_STRUCT43_INTR_MASK 0x40298AD8 FULL Interrupt mask DW1_CH_STRUCT43_INTR_MASKED 0x40298ADC FULL Interrupt masked DW1_CH_STRUCT43_SRAM_DATA0 0x40298AE0 FULL SRAM data 0 DW1_CH_STRUCT43_SRAM_DATA1 0x40298AE4 FULL SRAM data 1 DW1_CH_STRUCT43_TR_CMD 0x40298AE8 FULL Channel software trigger...
Page 859 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3 Register Details 9.3.1 DW_CTL Description: Control Address: 0x40280000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] ECC_INJ_E ECC_EN N [1:1] [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits...
Page 860 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.2 DW_STATUS Description: Status Address: 0x40280004 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name PC [7:4] None [3:3] B [2:2] NS [1:1] P [0:0] Bits Name None [15:12] PREEMPTAB None PRIO [9:8]...
Page 861 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.3 DW_ACT_DESCR_CTL Description: Active descriptor control Address: 0x40280020 Offset: 0x20 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DATA [7:0] Bits Name DATA [15:8] Bits Name DATA [23:16] Bits Name DATA [31:24] Bit-fields...
Page 862 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum 0:31 DATA Undefined Copy of DESCR_CTL of the currently active descriptor. [1:0] WAIT_FOR_DEACT Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active.
Page 863 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum (Continuation) - If the descriptor type is 'single', the trigger results in the execution of a single transfer. - If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer.
Page 864 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum (Continuation) '1': 1D transfer. The DESCR_X_CTL register is present, the DESCR_Y_CTL is not present and DESCR_NEXT_PTR is at offset 0x10. A 1D transfer consists out of DESCR_X_CTL.X_COUNT single transfers.
Page 865 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.4 DW_ACT_DESCR_SRC Description: Active descriptor source Address: 0x40280024 Offset: 0x24 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DATA [7:0] Bits Name DATA [15:8] Bits Name DATA [23:16] Bits Name DATA [31:24] Bit-fields...
Page 866 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.5 DW_ACT_DESCR_DST Description: Active descriptor destination Address: 0x40280028 Offset: 0x28 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DATA [7:0] Bits Name DATA [15:8] Bits Name DATA [23:16] Bits Name DATA [31:24] Bit-fields...
Page 867 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.6 DW_ACT_DESCR_X_CTL Description: Active descriptor X loop control Address: 0x40280030 Offset: 0x30 Retention: Not Retained IsDeepSleep: Comment: If the currently active descriptor has not X_CTL register, this MMIO register provides undefined information. Default: Bit-field Table Bits...
Page 868 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.7 DW_ACT_DESCR_Y_CTL Description: Active descriptor Y loop control Address: 0x40280034 Offset: 0x34 Retention: Not Retained IsDeepSleep: Comment: If the currently active descriptor has not Y_CTL register, this MMIO register provides undefined information. Default: Bit-field Table Bits...
Page 869 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.8 DW_ACT_DESCR_NEXT_PTR Description: Active descriptor next pointer Address: 0x40280038 Offset: 0x38 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [1:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24]...
Page 870 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.9 DW_ACT_SRC Description: Active source Address: 0x40280040 Offset: 0x40 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SRC_ADDR [7:0] Bits Name SRC_ADDR [15:8] Bits Name SRC_ADDR [23:16] Bits Name SRC_ADDR [31:24] Bit-fields Bits Name...
Page 871 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.10 DW_ACT_DST Description: Active destination Address: 0x40280044 Offset: 0x44 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DST_ADDR [7:0] Bits Name DST_ADDR [15:8] Bits Name DST_ADDR [23:16] Bits Name DST_ADDR [31:24] Bit-fields Bits Name...
Page 872 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.11 DW_ECC_CTL Description: ECC control Address: 0x40280080 Offset: 0x80 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name WORD_ADDR [7:0] Bits Name None [15:10] WORD_ADDR [9:8] Bits Name None [23:16] Bits Name PARITY [31:25] None...
Page 873 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.12 DW_CRC_CTL Description: CRC control Address: 0x40280100 Offset: 0x100 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] DATA _REVERSE [0:0] Bits Name None [15:9] _REVERSE [8:8] Bits Name None [23:16] Bits Name...
Page 874 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.13 DW_CRC_DATA_CTL Description: CRC data control Address: 0x40280110 Offset: 0x110 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DATA_XOR [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name...
Page 875 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.14 DW_CRC_POL_CTL Description: CRC polynomial control Address: 0x40280120 Offset: 0x120 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name POLYNOMIAL [7:0] Bits Name POLYNOMIAL [15:8] Bits Name POLYNOMIAL [23:16] Bits Name POLYNOMIAL [31:24] Bit-fields Bits Name...
Page 876 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.15 DW_CRC_LFSR_CTL Description: CRC LFSR control Address: 0x40280130 Offset: 0x130 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name LFSR32 [7:0] Bits Name LFSR32 [15:8] Bits Name LFSR32 [23:16] Bits Name LFSR32 [31:24] Bit-fields Bits Name...
Page 877 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.16 DW_CRC_REM_CTL Description: CRC remainder control Address: 0x40280140 Offset: 0x140 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name REM_XOR [7:0] Bits Name REM_XOR [15:8] Bits Name REM_XOR [23:16] Bits Name REM_XOR [31:24] Bit-fields Bits Name...
Page 878 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.17 DW_CRC_REM_RESULT Description: CRC remainder result Address: 0x40280148 Offset: 0x148 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name REM [7:0] Bits Name REM [15:8] Bits Name REM [23:16] Bits Name REM [31:24] Bit-fields...
Page 879 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18 CH_STRUCT 9.3.18.1 DW_CH_STRUCT_CH_CTL Description: Channel control Address: 0x40288000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name PC [7:4] None [3:3] B [2:2] NS [1:1] P [0:0] Bits Name None [15:12] PREEMPTAB None...
Page 880 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum Undefined Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
Page 881 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.2 DW_CH_STRUCT_CH_STATUS Description: Channel status Address: 0x40288004 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:4] INTR_CAUSE [3:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name PENDING None [30:24]...
Page 882 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.3 DW_CH_STRUCT_CH_IDX Description: Channel current indices Address: 0x40288008 Offset: Retention: Retained IsDeepSleep: Comment: Note that this register is retained during DeepSleep system power mode. Default: Bit-field Table Bits Name X_IDX [7:0] Bits Name Y_IDX [15:8]...
Page 883 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.4 DW_CH_STRUCT_CH_CURR_PTR Description: Channel current descriptor pointer Address: 0x4028800C Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [1:0] Bits Name ADDR [15:8] Bits Name ADDR [23:16] Bits Name ADDR [31:24] Bit-fields Bits Name...
Page 884 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.5 DW_CH_STRUCT_INTR Description: Interrupt Address: 0x40288010 Offset: 0x10 Retention: Not Retained IsDeepSleep: Comment: The register fields are not retained. This is to ensure that they come up as '0' after coming out of DeepSleep system power mode.
Page 885 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.6 DW_CH_STRUCT_INTR_SET Description: Interrupt set Address: 0x40288014 Offset: 0x14 Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. Default: Bit-field Table Bits Name None [7:1] CH [0:0] Bits Name None [15:8]...
Page 886 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.7 DW_CH_STRUCT_INTR_MASK Description: Interrupt mask Address: 0x40288018 Offset: 0x18 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] CH [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 887 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.8 DW_CH_STRUCT_INTR_MASKED Description: Interrupt masked Address: 0x4028801C Offset: 0x1C Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers. This register allows SW to read the status of all mask enabled interrupt causes with a single load operation, rather than two load operations: one for INTR and one for INTR_MASK.
Page 888 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.9 DW_CH_STRUCT_SRAM_DATA0 Description: SRAM data 0 Address: 0x40288020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: SRAM_DATA0 and SRAM_DATA1 are provided for ECC fault injection functionality. These register should NOT be used to control regular functionality (except that they can be used for initialization of DW SRAMs).
Page 889 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.10 DW_CH_STRUCT_SRAM_DATA1 Description: SRAM data 1 Address: 0x40288024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name DATA [7:0] Bits Name DATA [15:8] Bits Name DATA [23:16] Bits Name DATA [31:24] Bit-fields Bits Name...
Page 890 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 9.3.18.11 DW_CH_STRUCT_TR_CMD Description: Channel software trigger Address: 0x40288028 Offset: 0x28 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] ACTIVATE [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 891 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 10 EFUSE Description EFUSE MXS40 registers Base Address 0x402C0000 Size 0x200 Slave Num MMIO2 - 10 11 EFUSE_DATA Description eFUSE memory Base Address 0x402C0800 Size 0x200 Slave Num MMIO2 - 10 Register Name Address Permission Description...
Page 892 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 11.1 Register Details 11.1.1 EFUSE_DATA_CUSTOMER_DATA Description: Available EFUSE bits for customer usage.They can be programmed in NORMAL protection state via CMx/DAP and in SECURE protection state via CMx. Address: 0x402C0868 Offset: 0x68 Retention: Retained...
Page 893 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12 EVTGEN Description Event generator Base Address 0x403F0000 Size 0x1000 Slave Num MMIO3 - 4 Register Name Address Permission Description EVTGEN0_CTL 0x403F0000 FULL Control EVTGEN0_COMP0_STATUS 0x403F0004 FULL Comparator structures comparator 0 status EVTGEN0_COMP1_STATUS 0x403F0008 FULL Comparator structures comparator 1 status...
Page 894 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.7 COMP_STRUCT 6 Register Name Address Permission Description EVTGEN0_COMP_STRUCT6_COMP_CTL 0x403F08C0 FULL Comparator control EVTGEN0_COMP_STRUCT6_COMP0 0x403F08C4 FULL Comparator 0 (Active functionality) EVTGEN0_COMP_STRUCT6_COMP1 0x403F08C8 FULL Comparator 1 (DeepSleep functionality) 12.8 COMP_STRUCT 7 Register Name Address Permission Description EVTGEN0_COMP_STRUCT7_COMP_CTL...
Page 895 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12 Register Details 12.12.1 EVTGEN_CTL Description: Control Address: 0x403F0000 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name ENABLED None [30:24] [31:31]...
Page 896 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.2 EVTGEN_COMP0_STATUS Description: Comparator structures comparator 0 status Address: 0x403F0004 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COMP0_OUT [7:0] Bits Name COMP0_OUT [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 897 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.3 EVTGEN_COMP1_STATUS Description: Comparator structures comparator 1 status Address: 0x403F0008 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COMP1_OUT [7:0] Bits Name COMP1_OUT [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 898 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.4 EVTGEN_COUNTER_STATUS Description: Counter status Address: 0x403F0010 Offset: 0x10 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name VALID None [30:24] [31:31]...
Page 899 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.5 EVTGEN_COUNTER Description: Counter Address: 0x403F0014 Offset: 0x14 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT32 [7:0] Bits Name INT32 [15:8] Bits Name INT32 [23:16] Bits Name INT32 [31:24] Bit-fields Bits Name Default or...
Page 900 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.6 EVTGEN_RATIO_CTL Description: Ratio control Address: 0x403F0020 Offset: 0x20 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:19] DYNAMIC_MODE [18:16] Bits Name VALID DYNAMIC...
Page 901 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum VALID RW1S Ratio value valid: '0': Invalid. '1': Valid. The RATIO register fields INT16 and FRAC8 are only valid when VALID is '1'. Technical Reference Manual 002-29852 Rev.
Page 902 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.7 EVTGEN_RATIO Description: Ratio Address: 0x403F0024 Offset: 0x24 Retention: Retained IsDeepSleep: Comment: This register contains a ratio value expressing the relative frequency of the DeepSleep clock clk_lf wrt. the Active clock clk_ref_div. Specifically, this registers contains the average number of clk_ref_div cycles per clk_lf cycle.
Page 903 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.8 EVTGEN_REF_CLOCK_CTL Description: Reference clock control Address: 0x403F0030 Offset: 0x30 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT_DIV [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name...
Page 904 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.9 EVTGEN_INTR Description: Interrupt Address: 0x403F0700 Offset: 0x700 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COMP0 [7:0] Bits Name COMP0 [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name Default or...
Page 905 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.10 EVTGEN_INTR_SET Description: Interrupt set Address: 0x403F0704 Offset: 0x704 Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. For debug purposes, SW can write a '1' to activate a specific interrupt cause (this allows for debug of the SW ISR, without relying on HW to activate the interrupt cause).
Page 906 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.11 EVTGEN_INTR_MASK Description: Interrupt mask Address: 0x403F0708 Offset: 0x708 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COMP0 [7:0] Bits Name COMP0 [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name Default or...
Page 907 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.12 EVTGEN_INTR_MASKED Description: Interrupt masked Address: 0x403F070C Offset: 0x70C Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects 'a bitwise AND' between the INTR and INTR_MASK registers. Default: Bit-field Table Bits Name COMP0 [7:0]...
Page 908 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.13 EVTGEN_INTR_DPSLP Description: DeepSleep interrupt Address: 0x403F0710 Offset: 0x710 Retention: Retained IsDeepSleep: Comment: The interrupt causes are deactivated when the IP is disabled (CTL.ENABLED is '0'). Default: Bit-field Table Bits Name COMP1 [7:0] Bits Name...
Page 909 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.14 EVTGEN_INTR_DPSLP_SET Description: DeepSleep interrupt set Address: 0x403F0714 Offset: 0x714 Retention: Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. For debug purposes, SW can write a '1' to activate a specific interrupt cause (this allows for debug of the SW ISR, without relying on HW to activate the interrupt cause).
Page 910 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.15 EVTGEN_INTR_DPSLP_MASK Description: DeepSleep interrupt mask Address: 0x403F0718 Offset: 0x718 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name COMP1 [7:0] Bits Name COMP1 [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields Bits Name...
Page 911 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.16 EVTGEN_INTR_DPSLP_MASKED Description: DeepSleep interrupt masked Address: 0x403F071C Offset: 0x71C Retention: Retained IsDeepSleep: Comment: When read, this register reflects 'a bitwise AND' between the INTR and INTR_MASK registers. Default: Bit-field Table Bits Name COMP1 [7:0]...
Page 912 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.17 COMP_STRUCT 12.12.17.1 EVTGEN_COMP_STRUCT_COMP_CTL Description: Comparator control Address: 0x403F0800 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] COMP1 COMP0 _EN [1:1] _EN [0:0] Bits Name None [15:8] Bits Name None [23:17]...
Page 913 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.17.2 EVTGEN_COMP_STRUCT_COMP0 Description: Comparator 0 (Active functionality) Address: 0x403F0804 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT32 [7:0] Bits Name INT32 [15:8] Bits Name INT32 [23:16] Bits Name INT32 [31:24] Bit-fields Bits Name...
Page 914 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 12.12.17.3 EVTGEN_COMP_STRUCT_COMP1 Description: Comparator 1 (DeepSleep functionality) Address: 0x403F0808 Offset: Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name INT32 [7:0] Bits Name INT32 [15:8] Bits Name INT32 [23:16] Bits Name INT32 [31:24] Bit-fields Bits Name...
Page 915 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13 FAULT Description Fault structures Base Address 0x40210000 Size 0x10000 Slave Num MMIO2 - 1 13.1 STRUCT 0 Register Name Address Permission Description FAULT_STRUCT0_CTL 0x40210000 FULL Fault control FAULT_STRUCT0_STATUS 0x4021000C FULL Fault status FAULT_STRUCT0_DATA0 0x40210010 FULL...
Page 916 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description FAULT_STRUCT2_INTR_MASK 0x402102C8 FULL Interrupt mask FAULT_STRUCT2_INTR_MASKED 0x402102CC FULL Interrupt masked 13.4 STRUCT 3 Register Name Address Permission Description FAULT_STRUCT3_CTL 0x40210300 FULL Fault control FAULT_STRUCT3_STATUS 0x4021030C FULL Fault status FAULT_STRUCT3_DATA0 0x40210310 FULL...
Page 917 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5 Register Details 13.5.1 STRUCT 13.5.1.1 FAULT_STRUCT_CTL Description: Fault control Address: 0x40210000 Offset: Retention: Retained IsDeepSleep: Comment: This register uses DeepSleep reset. Therefore, a DeepSleep reset (possibly as a result of CTL.RESET_EN) resets this register (including setting CTL.RESET_EN to '0').
Page 918 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.2 FAULT_STRUCT_STATUS Description: Fault status Address: 0x4021000C Offset: Retention: Retained IsDeepSleep: Comment: This register uses cold reset (and is NOT affected by Active or DeepSleep reset). This allows for failure analysis after a warm reset (DeepSleep reset). Default: Bit-field Table Bits...
Page 919 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MPU_13 Bus master 13 MPU. See MPU_0 description. MPU_14 Bus master 14 MPU. See MPU_0 description. MPU_15 Bus master 15 MPU. See MPU_0 description. CM4_SYS_MPU CM4 system bus AHB-Lite interface MPU.
Page 920 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum GROUP_FAULT_5 Peripheral group 5 fault detection. See GROUP_FAULT_0 description. GROUP_FAULT_6 Peripheral group 6 fault detection. See GROUP_FAULT_0 description. GROUP_FAULT_7 Peripheral group 7 fault detection. See GROUP_FAULT_0 description.
Page 921 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum FLASHC_CM0_CA_C Flash controller, CM0+ cache, correctable ECC error: _ECC DATA0[26:0]: Violating address. DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0). DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
Page 922 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum CAN0_C_ECC CAN controller 0 MRAM correctable ECC error: DATA0[15:0]: Violating address. DATA0[22:16]: ECC violating data[38:32] from MRAM. DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F DATA1[31:0]: ECC violating data[31:0] from MRAM.
Page 923 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum VALID RW1S Valid indication: '0': Invalid. '1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset,...
Page 924 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.3 FAULT_STRUCT_DATA Description: Fault data Address: 0x40210010 Offset: 0x10 Retention: Retained IsDeepSleep: Comment: The DATA registers capture fault information. These register use cold reset (and are NOT affected by Active or DeepSleep reset). This allows for failure analysis after a warm reset (DeepSleep reset).
Page 925 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.4 FAULT_STRUCT_PENDING0 Description: Fault pending 0 Address: 0x40210040 Offset: 0x40 Retention: Not Retained IsDeepSleep: Comment: The PENDING0, PENDING1, PENDING2 registers specify pending (not captured) fault sources. The fault source for which data is captured in DATA0 through DATA3 and which is validated by STATUS.VALID and identified by STATUS.IDX is NOT included in this list of pending fault sources.
Page 926 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.5 FAULT_STRUCT_PENDING1 Description: Fault pending 1 Address: 0x40210044 Offset: 0x44 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SOURCE [7:0] Bits Name SOURCE [15:8] Bits Name SOURCE [23:16] Bits Name SOURCE [31:24] Bit-fields...
Page 927 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.6 FAULT_STRUCT_PENDING2 Description: Fault pending 2 Address: 0x40210048 Offset: 0x48 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SOURCE [7:0] Bits Name SOURCE [15:8] Bits Name SOURCE [23:16] Bits Name SOURCE [31:24] Bit-fields...
Page 928 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.7 FAULT_STRUCT_MASK0 Description: Fault mask 0 Address: 0x40210050 Offset: 0x50 Retention: Retained IsDeepSleep: Comment: The MASK0, MASK1, MASK2 registers specify 'enables' for fault sources. Only 'enabled' fault sources will be captured by this fault structure (and result in STATUS.VALID and INTR.FAULT being set to '1').
Page 929 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.8 FAULT_STRUCT_MASK1 Description: Fault mask 1 Address: 0x40210054 Offset: 0x54 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SOURCE [7:0] Bits Name SOURCE [15:8] Bits Name SOURCE [23:16] Bits Name SOURCE [31:24] Bit-fields Bits Name...
Page 930 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.9 FAULT_STRUCT_MASK2 Description: Fault mask 2 Address: 0x40210058 Offset: 0x58 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name SOURCE [7:0] Bits Name SOURCE [15:8] Bits Name SOURCE [23:16] Bits Name SOURCE [31:24] Bit-fields Bits Name...
Page 931 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.10 FAULT_STRUCT_INTR Description: Interrupt Address: 0x402100C0 Offset: 0xC0 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] FAULT [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 932 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.11 FAULT_STRUCT_INTR_SET Description: Interrupt set Address: 0x402100C4 Offset: 0xC4 Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects the INTR register. For debug purposes, SW can write a '1' to activate a specific interrupt cause (this allows for debug of the SW ISR, without relying on HW to activate the interrupt cause).
Page 933 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.12 FAULT_STRUCT_INTR_MASK Description: Interrupt mask Address: 0x402100C8 Offset: 0xC8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] FAULT [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 934 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 13.5.1.13 FAULT_STRUCT_INTR_MASKED Description: Interrupt masked Address: 0x402100CC Offset: 0xCC Retention: Not Retained IsDeepSleep: Comment: When read, this register reflects 'a bitwise AND' between the INTR and INTR_MASK registers. Default: Bit-field Table Bits Name None [7:1]...
Page 935 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14 FLASHC Description Flash controller Base Address 0x40240000 Size 0x10000 Slave Num MMIO2 - 4 Register Name Address Permission Description FLASHC_FLASH_CTL 0x40240000 FULL Control FLASHC_FLASH_PWR_CTL 0x40240004 FULL Flash power control FLASHC_FLASH_CMD 0x40240008 FULL Command FLASHC_ECC_CTL...
Page 936 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2 Register Details 14.2.1 FLASHC_FLASH_CTL Description: Control Address: 0x40240000 Offset: Retention: Retained IsDeepSleep: Comment: Default: 0x110000 Bit-field Table Bits Name None [7:4] MAIN_WS [3:0] Bits Name None [15:14] WORK MAIN None [11:10] WORK MAIN_MAP _BANK...
Page 937 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum MAIN_ECC_INJ_EN Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface...
Page 938 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error.
Page 939 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.2 FLASHC_FLASH_PWR_CTL Description: Flash power control Address: 0x40240004 Offset: Retention: Retained IsDeepSleep: Comment: This register controls Flash memory power control input pins 'enable' and 'enable_hv'. Flash memory can turned OFF through SW in LPACTIVE power mode by making ENABLE=0 and ENABLE_HV=0.
Page 940 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.3 FLASHC_FLASH_CMD Description: Command Address: 0x40240008 Offset: Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] BUFF_INV INV [0:0] [1:1] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 941 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.4 FLASHC_ECC_CTL Description: ECC control Address: 0x402402A0 Offset: 0x2A0 Retention: Retained IsDeepSleep: Comment: Note that for cache SRAM and FLASH work interface ECC, the word address is for a 32-bit word. For FLASH main interface ECC, the word address is for a 64-bit word. Default: Bit-field Table Bits...
Page 942 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.5 FLASHC_FM_SRAM_ECC_CTL0 Description: eCT Flash SRAM ECC control 0 Address: 0x402402B0 Offset: 0x2B0 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name ECC_INJ_DATA [7:0] Bits Name ECC_INJ_DATA [15:8] Bits Name ECC_INJ_DATA [23:16] Bits Name...
Page 943 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.6 FLASHC_FM_SRAM_ECC_CTL1 Description: eCT Flash SRAM ECC control 1 Address: 0x402402B4 Offset: 0x2B4 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:7] ECC_INJ_PARITY [6:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 944 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.7 FLASHC_FM_SRAM_ECC_CTL2 Description: eCT Flash SRAM ECC control 2 Address: 0x402402B8 Offset: 0x2B8 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name CORRECTED_DATA [7:0] Bits Name CORRECTED_DATA [15:8] Bits Name CORRECTED_DATA [23:16] Bits Name...
Page 945 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.8 FLASHC_FM_SRAM_ECC_CTL3 Description: eCT Flash SRAM ECC control 3 Address: 0x402402BC Offset: 0x2BC Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:5] ECC_INJ_E None [3:1] N [4:4] _ENABLE [0:0] Bits Name None [15:9]...
Page 946 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.9 FLASHC_CM0_CA_CTL0 Description: CM0+ cache control Address: 0x40240400 Offset: 0x400 Retention: Retained IsDeepSleep: Comment: Default: 0xC0000001 Bit-field Table Bits Name None [7:2] RAM_ECC RAM_ECC _INJ_EN _EN [0:0] [1:1] Bits Name None [15:8] Bits Name None [23:18]...
Page 947 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.10 FLASHC_CM0_CA_CTL1 Description: CM0+ cache control Address: 0x40240404 Offset: 0x404 Retention: Retained IsDeepSleep: Comment: This register controls the CM0 Cache SRAM power states. CM0 Cache SRAM consists of a single power partition. Default: 0xFA050003 Bit-field Table...
Page 948 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.11 FLASHC_CM0_CA_CTL2 Description: CM0+ cache control Address: 0x40240408 Offset: 0x408 Retention: Retained IsDeepSleep: Comment: Default: 0x12C Bit-field Table Bits Name PWRUP_DELAY [7:0] Bits Name None [15:10] PWRUP_DELAY [9:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 949 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.12 FLASHC_CM0_CA_STATUS0 Description: CM0+ cache status 0 Address: 0x40240440 Offset: 0x440 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALID32 [7:0] Bits Name VALID32 [15:8] Bits Name VALID32 [23:16] Bits Name VALID32 [31:24] Bit-fields...
Page 950 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.13 FLASHC_CM0_CA_STATUS1 Description: CM0+ cache status 1 Address: 0x40240444 Offset: 0x444 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TAG [7:0] Bits Name TAG [15:8] Bits Name TAG [23:16] Bits Name TAG [31:24] Bit-fields...
Page 951 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.14 FLASHC_CM0_CA_STATUS2 Description: CM0+ cache status 2 Address: 0x40240448 Offset: 0x448 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] LRU [5:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 952 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.15 FLASHC_CM0_STATUS Description: CM0+ interface status Address: 0x40240460 Offset: 0x460 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] WORK MAIN_INTE _INTE RNAL_ERR RNAL_ERR [0:0] [1:1] Bits Name None [15:8] Bits Name None [23:16]...
Page 953 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.16 FLASHC_CM4_CA_CTL0 Description: CM4 cache control Address: 0x40240480 Offset: 0x480 Retention: Retained IsDeepSleep: Comment: Default: 0xC0000001 Bit-field Table Bits Name None [7:2] RAM_ECC RAM_ECC _INJ_EN _EN [0:0] [1:1] Bits Name None [15:8] Bits Name None [23:18]...
Page 954 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.17 FLASHC_CM4_CA_CTL1 Description: CM4 cache control Address: 0x40240484 Offset: 0x484 Retention: Retained IsDeepSleep: Comment: This register controls the CM4 Cache SRAM power states. CM4 Cache SRAM consists of a single power partition. Default: 0xFA050003 Bit-field Table...
Page 955 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.18 FLASHC_CM4_CA_CTL2 Description: CM4 cache control Address: 0x40240488 Offset: 0x488 Retention: Retained IsDeepSleep: Comment: Default: 0x12C Bit-field Table Bits Name PWRUP_DELAY [7:0] Bits Name None [15:10] PWRUP_DELAY [9:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 956 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.19 FLASHC_CM4_CA_STATUS0 Description: CM4 cache status 0 Address: 0x402404C0 Offset: 0x4C0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name VALID32 [7:0] Bits Name VALID32 [15:8] Bits Name VALID32 [23:16] Bits Name VALID32 [31:24] Bit-fields...
Page 957 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.20 FLASHC_CM4_CA_STATUS1 Description: CM4 cache status 1 Address: 0x402404C4 Offset: 0x4C4 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name TAG [7:0] Bits Name TAG [15:8] Bits Name TAG [23:16] Bits Name TAG [31:24] Bit-fields...
Page 958 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.21 FLASHC_CM4_CA_STATUS2 Description: CM4 cache status 2 Address: 0x402404C8 Offset: 0x4C8 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:6] LRU [5:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 959 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.22 FLASHC_CM4_STATUS Description: CM4 interface status Address: 0x402404E0 Offset: 0x4E0 Retention: Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:2] WORK MAIN_INTE _INTE RNAL_ERR RNAL_ERR [0:0] [1:1] Bits Name None [15:8] Bits Name None [23:16]...
Page 960 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.23 FLASHC_CRYPTO_BUFF_CTL Description: Cryptography buffer control Address: 0x40240500 Offset: 0x500 Retention: Retained IsDeepSleep: Comment: Default: 0x40000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None PREF_EN...
Page 961 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.24 FLASHC_DW0_BUFF_CTL Description: Datawire 0 buffer control Address: 0x40240580 Offset: 0x580 Retention: Retained IsDeepSleep: Comment: Default: 0x40000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None...
Page 962 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.25 FLASHC_DW1_BUFF_CTL Description: Datawire 1 buffer control Address: 0x40240600 Offset: 0x600 Retention: Retained IsDeepSleep: Comment: Default: 0x40000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None...
Page 963 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.26 FLASHC_DMAC_BUFF_CTL Description: DMA controller buffer control Address: 0x40240680 Offset: 0x680 Retention: Retained IsDeepSleep: Comment: Default: 0x40000000 Bit-field Table Bits Name None [7:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None...
Page 964 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27 FM_CTL_ECT 14.2.27.1 FLASHC_FM_CTL Description: Flash Macro Control Address: 0x4024F000 Offset: Retention: Not Retained IsDeepSleep: Comment: The register fields are related to C interface functionality Default: Bit-field Table Bits Name None [7:5] FM_MODE [4:0] Bits Name...
Page 965 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum FM_MODE Flash macro mode selection: d0: Read/Idle - Normal mode, read array enabled d1: Not Used - the 1st analog POR is done by enable/enable_hv d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG, rd, redu, etc..) d3 - POR IRAM MMR Download - Downloads from...
Page 966 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.2 FLASHC_FM_CODE_MARGIN Description: Flash Macro Margin Mode on Code Flash Address: 0x4024F004 Offset: Retention: Not Retained IsDeepSleep: Comment: This register shell be used when Margin read is applied to the s40ect Flash IP. One should set the DCS trim that serves as the reference current to the area between 4-8uA (around the 6uA normal static ref current) and set the enable.
Page 967 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.3 FLASHC_FM_ADDR Description: Flash Macro Address Address: 0x4024F008 Offset: Retention: Not Retained IsDeepSleep: Comment: This register specifies the flash memory address till the byte resolution. This register defines the address space for both Code and Work Flash and it works according to the address scheme tables defined below (also used as the address definition for R-bus ( code_r_addr and work_r_addr) This FM_ADDR should be used whenever a user mode embedded operation is done on the...
Page 968 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.4 FLASHC_INTR Description: Interrupt Address: 0x4024F020 Offset: 0x20 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] INTR [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24] Bit-fields...
Page 969 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.5 FLASHC_INTR_SET Description: Interrupt Set Address: 0x4024F024 Offset: 0x24 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] INTR_SET [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 970 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.6 FLASHC_INTR_MASK Description: Interrupt Mask Address: 0x4024F028 Offset: 0x28 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] INTR _MASK [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 971 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.7 FLASHC_INTR_MASKED Description: Interrupt Masked Address: 0x4024F02C Offset: 0x2C Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] INTR _MASKED [0:0] Bits Name None [15:8] Bits Name None [23:16] Bits Name None [31:24]...
Page 972 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.8 FLASHC_ECC_OVERRIDE Description: ECC Data In override information and control bits Address: 0x4024F030 Offset: 0x30 Retention: Not Retained IsDeepSleep: Comment: The replacement can be either to the Code syndrome or the work flash syndrome. It knows to replace only 8 bits (per 64) in code flash OR 7 bits (per 32) in work flash, therefore this option is valid only for pgm64 command (Code) or pgm32 command (Work) Default:...
Page 973 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.9 FLASHC_FM_DATA Description: Flash macro data_in[31 to 0] both Code and Work Flash Address: 0x4024F040 Offset: 0x40 Retention: Not Retained IsDeepSleep: Comment: These registers support aligned 32-bit accesses. The usage of this register should follow the PGM sequence defined (and implemented by API).
Page 974 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.10 FLASHC_BOOKMARK Description: Bookmark register - keeps the current FW HV seq Address: 0x4024F064 Offset: 0x64 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name BOOKMARK [7:0] Bits Name BOOKMARK [15:8] Bits Name BOOKMARK [23:16]...
Page 975 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.11 FLASHC_MAIN_FLASH_SAFETY Description: Main (Code) Flash Security enable Address: 0x4024F400 Offset: 0x400 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] MAINFLASH WRITEENABL E [0:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 976 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.12 FLASHC_STATUS Description: Status read from Flash Macro Address: 0x4024F404 Offset: 0x404 Retention: Not Retained IsDeepSleep: Comment: Read out by the CPUSS to understand the Flash Macro status Default: 0x80000000 Bit-field Table Bits Name None [7:7]...
Page 977 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Bits Name Default or Description Enum POR_1B_ECC Indicates internal ECC found 1b error while _CORRECTED downloading info in POR from NVM to VM and fixed it. Valid after 2nd, 3rd and 4th POR phases (FUR, IREM &...
Page 978 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 14.2.27.13 FLASHC_WORK_FLASH_SAFETY Description: Work Flash Security enable Address: 0x4024F500 Offset: 0x500 Retention: Not Retained IsDeepSleep: Comment: Default: Bit-field Table Bits Name None [7:1] WORKFLASH WRITEENABL E [0:0] Bits Name None [15:8] Bits Name None [23:16]...
Page 979 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15 GPIO Description GPIO port control/configuration Base Address 0x40310000 Size 0x10000 Slave Num MMIO3 - 1 Register Name Address Permission Description GPIO_INTR_CAUSE0 0x40314000 FULL Interrupt port cause register 0 GPIO_VDD_ACTIVE 0x40314010 FULL Extern power supply detection register GPIO_VDD_INTR 0x40314014 FULL...
Page 980 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT1_INTR 0x40310094 FULL Port interrupt status register Note:EDGE4 EDGE5 EDGE6 EDGE7 IN_IN4 IN_IN5 IN_IN6 IN_IN7 are not available for this register GPIO_PRT1_INTR_MASK 0x40310098 FULL Port interrupt mask register Note:EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT1_INTR_MASKED...
Page 981 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT3_OUT 0x40310180 FULL Port output data register Note:OUT6 OUT7 are not available for this register GPIO_PRT3_OUT_CLR 0x40310184 FULL Port output data clear register GPIO_PRT3_OUT_SET 0x40310188 FULL Port output data set register GPIO_PRT3_OUT_INV 0x4031018C FULL...
Page 982 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT4_CFG_IN_AUTOLVL 0x40310258 FULL Port input buffer AUTOLVL configuration register Note:VTRIP_SEL5_1 VTRIP_SEL6_1 VTRIP_SEL7_1 are not available for this register 15.6 PRT 5 Register Name Address Permission Description GPIO_PRT5_OUT 0x40310280 FULL Port output data register...
Page 983 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT7_IN 0x40310390 FULL Port input state register GPIO_PRT7_INTR 0x40310394 FULL Port interrupt status register GPIO_PRT7_INTR_MASK 0x40310398 FULL Port interrupt mask register GPIO_PRT7_INTR_MASKED 0x4031039C FULL Port interrupt masked status register GPIO_PRT7_INTR_SET 0x403103A0 FULL Port interrupt set register...
Page 984 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT9_INTR_MASK 0x40310498 FULL Port interrupt mask register Note:EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT9_INTR_MASKED 0x4031049C FULL Port interrupt masked status register Note:EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT9_INTR_SET 0x403104A0 FULL...
Page 985 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT11_INTR_MASKED 0x4031059C FULL Port interrupt masked status register Note:EDGE3 EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT11_INTR_SET 0x403105A0 FULL Port interrupt set register Note:EDGE3 EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT11_INTR_CFG...
Page 986 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.15 PRT 14 Register Name Address Permission Description GPIO_PRT14_OUT 0x40310700 FULL Port output data register GPIO_PRT14_OUT_CLR 0x40310704 FULL Port output data clear register GPIO_PRT14_OUT_SET 0x40310708 FULL Port output data set register GPIO_PRT14_OUT_INV 0x4031070C FULL Port output data invert register...
Page 987 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT16_OUT_CLR 0x40310804 FULL Port output data clear register GPIO_PRT16_OUT_SET 0x40310808 FULL Port output data set register GPIO_PRT16_OUT_INV 0x4031080C FULL Port output data invert register GPIO_PRT16_IN 0x40310810 FULL Port input state register Note:IN4 IN5 IN6 IN7 are not available for this register GPIO_PRT16_INTR...
Page 988 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers Register Name Address Permission Description GPIO_PRT18_INTR_SET 0x40310920 FULL Port interrupt set register GPIO_PRT18_INTR_CFG 0x40310940 FULL Port interrupt configuration register GPIO_PRT18_CFG 0x40310944 FULL Port configuration register GPIO_PRT18_CFG_IN 0x40310948 FULL Port input buffer configuration register GPIO_PRT18_CFG_OUT 0x4031094C FULL Port output buffer configuration register...
Page 989 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.22 PRT 21 Register Name Address Permission Description GPIO_PRT21_OUT 0x40310A80 FULL Port output data register GPIO_PRT21_OUT_CLR 0x40310A84 FULL Port output data clear register GPIO_PRT21_OUT_SET 0x40310A88 FULL Port output data set register GPIO_PRT21_OUT_INV 0x40310A8C FULL Port output data invert register...
Page 990 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25 Register Details 15.25.1 GPIO_INTR_CAUSE0 Description: Interrupt port cause register 0 Address: 0x40314000 Offset: 0x4000 Retention: Retained IsDeepSleep: Comment: This register provides interrupt status corresponding to ports 0 to 31 Default: Bit-field Table Bits Name...
Page 991 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.2 GPIO_VDD_ACTIVE Description: Extern power supply detection register Address: 0x40314010 Offset: 0x4010 Retention: Retained IsDeepSleep: Comment: This register provides external power supply status Default: Bit-field Table Bits Name VDDIO_ACTIVE [7:0] Bits Name VDDIO_ACTIVE [15:8] Bits...
Page 992 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.3 GPIO_VDD_INTR Description: Supply detection interrupt register Address: 0x40314014 Offset: 0x4014 Retention: Retained IsDeepSleep: Comment: An interrupt cause is cleared (set to '0') by writing a '1' to the corresponding bit field. It is not recommended to write 0xFF to clear all interrupt causes, as a new interrupt cause may have occurred between reading the register and clearing.
Page 993 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.4 GPIO_VDD_INTR_MASK Description: Supply detection interrupt mask register Address: 0x40314018 Offset: 0x4018 Retention: Retained IsDeepSleep: Comment: This register configures the supply detection interrupts for all supplies. This register only masks the forwarding of interrupts to the CPU(s), it does not enable/disable the logging of interrupts into the VDD_INTR register.
Page 994 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.5 GPIO_VDD_INTR_MASKED Description: Supply detection interrupt masked register Address: 0x4031401C Offset: 0x401C Retention: Retained IsDeepSleep: Comment: This register contains the AND-ed values of VDD_INTR and VDD_INTR_MASK registers Default: Bit-field Table Bits Name VDDIO_ACTIVE [7:0] Bits...
Page 995 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.6 GPIO_VDD_INTR_SET Description: Supply detection interrupt set register Address: 0x40314020 Offset: 0x4020 Retention: Retained IsDeepSleep: Comment: Allows firmware or debugger to set interrupt bits in the VDD_INTR register by writing a '1' to the corresponding bit field.
Page 996 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.7 PRT 15.25.7.1 GPIO_PRT_OUT Description: Port output data register Address: 0x40310000 Offset: Retention: Retained IsDeepSleep: Comment: Used to read and write the output data for the IO pins in the port. A register write changes the output data to the written value.
Page 997 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.7.2 GPIO_PRT_OUT_CLR Description: Port output data clear register Address: 0x40310004 Offset: Retention: Retained IsDeepSleep: Comment: Used to clear output data of specific IO pins in the corresponding port to '0', without affecting the output data of the other IO pads in the port.
Page 998 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.7.3 GPIO_PRT_OUT_SET Description: Port output data set register Address: 0x40310008 Offset: Retention: Retained IsDeepSleep: Comment: Used to set output data of specific IO pins in the corresponding port to '1', without affecting the output data of the other IO pads in the port.
Page 999 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.7.4 GPIO_PRT_OUT_INV Description: Port output data invert register Address: 0x4031000C Offset: Retention: Retained IsDeepSleep: Comment: Used to invert output data of specific IO pins in the corresponding port, without affecting the output data of the other IO pads in the port.
Page 1000 TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers 15.25.7.5 GPIO_PRT_IN Description: Port input state register Address: 0x40310010 Offset: 0x10 Retention: Not Retained IsDeepSleep: Comment: Used to read current pin status for IO pins that have their input buffer enabled (see CFG_IN). Default: Bit-field Table Bits...

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