Page 1 (features) of a specific TLE985xQX derivative (derivative device), please refer to the respective Data Sheet. For simplicity, the various device types are referenced by the collective term TLE985xQX throughout this manual. * Arm and Cortex are registered trademarks of Arm Limited, UK User Manual Rev. 2.0 www.infineon.com 2023-08-09...
Page 2: Table Of Contents
MOTIX™ TLE985xQX Table of Contents Overview ............... 15 Block Diagram .
Page 3 MOTIX™ TLE985xQX 6.8.1.1 Data Storage Registers ............. . . 81 System Control Unit - Digital Modules (SCU-DM) .
Page 4 MOTIX™ TLE985xQX 7.6.5 NMI Event Flags Handling ............. . 163 General Port Control .
Page 5 MOTIX™ TLE985xQX Features ................256 Introduction .
Page 6 MOTIX™ TLE985xQX 12.3.1 Interrupt Node Assignment ............318 12.3.1.1 Interrupt Node 0 and 1 - GPT12 Timer Module .
Page 7 MOTIX™ TLE985xQX 13.10.1 Math Module Registers ..............389 Watchdog Timer (WDT1) .
Page 8 MOTIX™ TLE985xQX 16.3.8.3 GPT1 Auxiliary Timers T2/T4 Control Registers ......... 477 16.3.8.4 Encoding .
Page 9 MOTIX™ TLE985xQX 18.3.3 T12 Compare Mode ..............538 18.3.3.1 Compare Channels .
Page 10 MOTIX™ TLE985xQX 19.3.1 Mode 0, 8-Bit Shift Register, Fixed Baud Rate ..........640 19.3.2 Mode 1, 8-Bit UART, Variable Baud Rate .
Page 11 MOTIX™ TLE985xQX 21.5.2 Configuration Register ..............689 21.5.3 Baud Rate Timer Reload Register .
Page 12 MOTIX™ TLE985xQX 24.2 Introduction ................781 24.2.1 Block Diagram .
Page 13 MOTIX™ TLE985xQX 26.3.1.3 Overtemperature Detection ............934 26.3.1.4 ON-State Open Load Detection .
Page 14 MOTIX™ TLE985xQX 27.3.10.1 Clock Generator of Driver Supply ........... . . 961 27.3.11 Adjustable Voltage Monitoring .
Page 15: Overview
MOTIX™ TLE985xQX Overview Overview • 32-bit Arm® Cortex®*-M0 Core – 40 MHz clock frequency – one clock per machine cycle architecture – single cycle multiplier • On-chip memory – up to 96 KB Flash (product variant dependent, including EEPROM) – 4 KB EEPROM (emulated in Flash) –...
Page 16 MOTIX™ TLE985xQX Overview – Stop Mode with cyclic sense option • Power-on and undervoltage/brownout reset generator • Overtemperature protection incl. shutdown • Short circuit protection for all voltage regulators and actuators (High Side Switch) • Loss of clock detection with fail safe mode for power switches •...
Page 17: Block Diagram
MOTIX™ TLE985xQX Block Diagram Block Diagram P0.0 DEBUG INTERFACE FLASH SRAM Cortex systembus slave slave slave Multilayer AHB Matrix slave slave PBA0 PBA1 * P2.0, ...P2.7 (AN0, … AN7) ADC10B MON 1...4 VBAT_SENSE P0.0 – P0.x UART1 GPIO P1.0 – P1.x DPP1 UART2 P2.0 –...
Page 18: General Device Information
MOTIX™ TLE985xQX General Device Information General Device Information Pin Configurations P2.7 37 24 P0.0 23 TMS/DAP1 P2.3 38 22 P0.1 P2.1 39 P2.2 40 21 GNDP P2.0 41 20 MON4 VDDC 42 19 MON3 TLE 985x GNDA 43 18 MON2 VDDP 44 17 MON1 VDDEXT 45...
Page 19: Pin Definitions And Functions
MOTIX™ TLE985xQX General Device Information Pin Definitions and Functions After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings: • Pull-up enabled only (PU) • Pull-down enabled only (PD) • Input with both pull-up and pull-down disabled (I) •...
Page 20 MOTIX™ TLE985xQX General Device Information Table 1 Pin Definitions and Functions (cont’d) Symbol Type Reset Function Number State P1.4 GPIO General Purpose IO Alternate function mapping see Table 211 Port 2 Port 2 is a 5-Bit general purpose input-only port. Alternate functions can be assigned and are listed in the Port description.
Page 21 MOTIX™ TLE985xQX General Device Information Table 1 Pin Definitions and Functions (cont’d) Symbol Type Reset Function Number State CP2H – Charge Pump Capacity 2 High, connect external C CP2L – Charge Pump Capacity 2 Low, connect external C – Charge Pump Capacity –...
Page 22: Modes Of Operations
MOTIX™ TLE985xQX Modes of Operations Modes of Operations This highly integrated circuit contains analog and digital functional blocks. For system and interface control an embedded 32-Bit Arm® Cortex®-M0 microcontroller is included. For internal and external power supply purposes, on-chip low drop-out regulators are existent. An internal oscillator (no external components necessary) provides a cost effective and suitable clock in particular for LIN slave nodes.
Page 23 MOTIX™ TLE985xQX Modes of Operations Reset Mode The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable, the Active Mode is entered .
Page 24 MOTIX™ TLE985xQX Modes of Operations Table 2 Power Mode Configurations (cont’d) Module/function Active Mode Sleep Mode Stop Mode Comment Bridge Driver ON/OFF – LIN TRx ON/OFF wake-up only / OFF wake-up only/ – MONx (wake-up) n.a. disabled/static/ disabled/static/ cyclic: combined with cyclic cyclic HS=on...
Page 25: Device Register Types
MOTIX™ TLE985xQX Device Register Types Device Register Types The following register types are used within this device. List see in Table Table 3 Register Types Type can be modified by Description Error response Hard Firmware Soft on write access ware ware read-only flag set when HW = 1, clear on read, with...
Page 26: Power Management Unit (Pmu)
MOTIX™ TLE985xQX Power Management Unit (PMU) Power Management Unit (PMU) Features • System modes control (startup, sleep, stop and active) • Power management (cyclic wake, cyclic sense) • Control of system voltage regulators with diagnosis (overload, short, overvoltage) • Fail safe mode detection and operation in case of system errors •...
Page 27: Block Diagram
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.2.1 Block Diagram The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules more detailed. Power Down Supply VDDP Power Supply Generation Unit (PGU) VDDC e.g. for WDT 1 LP_CLK Peripherals LDO for External Supply...
Page 28 MOTIX™ TLE985xQX Power Management Unit (PMU) Table 4 Description of PMU Submodules (cont’d) Mod. Modules Functions Name Peripherals Peripheral Blocks of PMU These blocks include the analog peripherals to ensure a stable and fail safe PMU startup and operation (bandgap, bias). Power Supply Voltage regulators for VDDP and This block includes the voltage regulators for the pad...
Page 29: Pmu Modes Overview
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.2.2 PMU Modes Overview The following state diagram shows the available modes of the device. > 4V and V ramp up < 3V and V ramp down LIN-wake or MON-wake or start-up cyclic -wake VDDC =stable and error_supp<5 VDDC / VDDP = fail...
Page 30 MOTIX™ TLE985xQX Power Management Unit (PMU) Sleep Mode The Sleep Mode is the power saving mode where the lowest power consumption is achieved. In this mode the PMU resets all system functionalities and switches off all voltage supplies (VDDP, VDDC, VDDEXT) which are generated in the PMU.
Page 31 MOTIX™ TLE985xQX Power Management Unit (PMU) PMCON0 LP_CLK2 (100 kHz) LP_CLK (20 MHz) VDDC 1.5V VDDP Active Sleep SYSTEM_STATE Timing_Diagram_Sleep_Mode_Entry_Customer.vsd Figure 6 Sleep Mode Entry Timing The Sleep Mode is terminated by a LIN dominant pulse or a corresponding (rising edge / falling edge) activity at the MON input.
Page 32 MOTIX™ TLE985xQX Power Management Unit (PMU) startup sequences in a synchronous way. A successful startup sequence enters the startup Mode automatically. The wake-up procedure described is the default setup of the PMU. The Sleep Mode can be terminated by synchronous wake-up events too. If this is desired, the PMU must be configured by setting the corresponding SFRs.
Page 33 MOTIX™ TLE985xQX Power Management Unit (PMU) Stop Mode The objective of the Stop Mode is to provide a data retention feature for the embedded MCU and the special function registers (XSFRs). In the Stop Mode the core supply voltage VDDC goes from 1.5 V to 0.9 V with the objective to reduce leakage current as much as possible.
Page 34 MOTIX™ TLE985xQX Power Management Unit (PMU) separated in Cyclic Sense and wake-up after time-out (Cyclic Wake). Both of these wake-up procedures work similarly to the Sleep-exit. In Cyclic Sense mode, both the MONx inputs as well as the GPIOs can be evaluated and a transition will cause a termination of the Stop Mode.
Page 35: Power Supply Generation
MOTIX™ TLE985xQX Power Management Unit (PMU) Power Supply Generation (PGU) As shown in the diagram below the Power Supply Generation consists of the following modules: Submodules of PSG are: • Power Down Supply: independent analog supply voltage generation for Power Control Unit logic, for VDDP Regulator and for VDDC Regulator.
Page 36 MOTIX™ TLE985xQX Power Management Unit (PMU) Features • 5 V low-drop voltage regulator • Overcurrent Monitoring and Shutdown with MCU signalling (Interrupt) • Overvoltage monitoring with MCU signalling (Interrupt) • Undervoltage monitoring with MCU signalling (Interrupt) • Undervoltage monitoring with Reset (UnderVoltage Reset, V DDPUV •...
Page 37: Voltage Regulator 1.5V (Vddc)
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.3.2 Voltage Regulator 1.5V (VDDC) This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, digital peripherals and other chip internal analog 1.5 V functions (e.g. ADC). Features •...
Page 38: External Voltage Regulator 5.0V (Vddext)
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.3.3 External Voltage Regulator 5.0V (VDDEXT) This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used e.g. to supply an external sensor, LEDs or potentiometers. Features •...
Page 39: Power-On Reset Concept
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.3.4 Power-on Reset Concept ca. 4V 1.5V Power Down RESET_N LP_Clk VDDP ca. 3.5V VDDC 1.5V fail stable SUPPLY_STATUS RESET_PIN PMU_RESET_STS Down Start-up Active SYSTEM_STATE Figure 13 Power-on Reset Concept User Manual Rev. 2.0 2023-08-09...
Page 40: Pmu Register Overview
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.3.5 PMU Register Overview The PMU registers must be accessed wordwise. Otherwise a hardfault is triggered. Table 5 Register Address Space for PMU Registers Module Base Address End Address Note 50004000 50004FFF Power Management Unit Registers The registers are addressed wordwise.
Page 41 MOTIX™ TLE985xQX Power Management Unit (PMU) PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ PMU_ 5V_O 5V_O OVER 1V5_ 1V5_ 5V_F 5V_O 5V_O OVER 1V5_ 1V5_ 1V5_ VER* VER* TEM* OVE* OVE* AIL* VER* VER* TEMP FAI* OVE* OVE* Field...
Page 42 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description PMU_5V_OVERVOLT Overvoltage at VDDP regulator This bit is set by hardware and can only be cleared by software. No overvoltage, Overvoltage, PMU_OVERTEMP PMU Overtemperature This bit is set by hardware and can only be cleared by software.
Page 43 MOTIX™ TLE985xQX Power Management Unit (PMU) VDDP [V] OV_PREWARN UV_PREWARN UV (= Reset Threshold ) t [100ms] VDDP_OV_PREWARN VPPD_OV VDDP_UV_PREWARN VDDP_UV Figure 14 VDDP User Manual Rev. 2.0 2023-08-09...
Page 44: Vddext Control Register
MOTIX™ TLE985xQX Power Management Unit (PMU) VDDC [V] OV_PREWARN UV_PREWARN UV (= Reset Threshold ) t [100ms] VDDC_OV_PREWARN VPPC _OV VDDC_UV_PREWARN VDDC_UV Figure 15 VDDC 6.3.6.2 VDDEXT Control Register The VDDEXT can be fully controlled by the following SFR Register, including all diagnosis functions. . User Manual Rev.
Page 45 MOTIX™ TLE985xQX Power Management Unit (PMU) VDDEXT Control PMU_VDDEXT_CTRL Offset Reset Value VDDEXT Control Table 8 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE XT_* XT_* XT_* XT_* XT_* XT_* XT_* XT_* XT_* XT_* XT_* Field Bits Type Description 31:14...
Page 46 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description VDDEXT_OT_STS VDDEXT Supply Overtemperature Status Note: This bit is RESET_TYPE_3 VDDEXT not in overtemperature condition, VDDEXT in overtemperature condition, VDDEXT_UV_IS VDDEXT Supply Undervoltage Interrupt Status Note: This bit is RESET_TYPE_4 VDDEXT not in undervoltage condition, VDDEXT in undervoltage condition, VDDEXT_OT_IS...
Page 47: Power Control Unit
MOTIX™ TLE985xQX Power Management Unit (PMU) Power Control Unit The Power Control Unit is the controlling instance of the system power supply generation (PSG). It offers important fail safe features, which are described in the next chapter. 6.4.1 Power Control Unit - Fail Safe Scenarios The PMU handles several different failure scenarios, listed below and described in the following chapters: •...
Page 48: Vddext Failure
MOTIX™ TLE985xQX Power Management Unit (PMU) If one of the voltage regulators needs to deliver too much current, a stable operation of the supply voltage is not given. In this case the overcurrent detection of VDDP and VDDC will ensure that the system will enter Sleep Mode.
Page 49 MOTIX™ TLE985xQX Power Management Unit (PMU) LP_CLK VDDC 1.5V 0.9V PMU_RST_STS RESET _PIN Stop Active SYSTEM_STATE Figure 16 Stop Mode Exit Timing User Manual Rev. 2.0 2023-08-09...
Page 50: Register Definition
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.4.1.6 Register Definition Table 9 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition, PMU System Fail Register PMU_HIGHSIDE_CTRL High-Side Control Register 0000 0000 PMU_WFS WFS System Fail Register 0000 0000 PMU_OT_CTRL Overtemperature Control Register...
Page 51 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description LP_CLKWD LP_CLKWD Low power clock fail, WDT1_SEQ_FAIL External Watchdog (WDT1) Sequential Fail Indicates that Watchdog is not serviced 5 times No Fail, System working properly Sequential Watchdog Fail, 5 consecutive watchdog fails SYS_OT System Overtemperature Indication Flag...
Page 52 MOTIX™ TLE985xQX Power Management Unit (PMU) PMU_OT_CTRL Offset Reset Value Overtemperature Control Register Table 11 PMU_OT_ TH_CNF Field Bits Type Description 31:8 Reserved Always read as 0 PMU_OT_EN PMU Overtemperature Detection Enable Disable, Overtemperature detection disabled Enable, Overtemperature detection enabled PMU_OT_WAKE_EN PMU Wake On Overtemperature Enable Disable, no Wake-Up on OT condition...
Page 53: Wake-Up Management Unit (Wmu)
MOTIX™ TLE985xQX Power Management Unit (PMU) High-Side Control Register PMU_HIGHSIDE_CTRL Offset Reset Value Highside Control Register Table 12 Field Bits Type Description 31:3 Reserved Always read as 0 HS1_CYC_EN High-Side 1 switch enable for cyclic sense Disable, Enable, Reserved Always read as 0 Table 12 RESET of PMU_HIGHSIDE_CTRL...
Page 54 MOTIX™ TLE985xQX Power Management Unit (PMU) 2. None of the GPIOs is supplied during Sleep Mode, therefore wake-up is not possible through them. P0.X, P1.X PMU-WMU Figure 17 Block Diagram of Wake-up Management Unit in Cyclic Sense Mode with VDDEXT. User Manual Rev.
Page 55: Register Definition
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.5.1 Register Definition These registers are for wake-up control of all wake-up capable general purpose inputs outputs The WMU is fully controllable by the below listed SFR Registers. Table 13 Register Overview Register Short Name Register Long Name Offset Address Reset Value...
Page 56: Pmu Wake Up Configuration Register
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.5.1.1 PMU Wake Up Configuration Register This register is dedicated for the control of the PMU Peripherals Wake Configuration GPIO Port 0 Register PMU_WAKE_CNF_GPIO0 Offset Reset Value Wake Configuration GPIO Port 0 Register Table 14 CYC_ CYC_ CYC_...
Page 57 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description FA_4 Port 0_4 Wake-up on Falling Edge enable ENABLE, wake-up enabled DISABLE, wake-up disabled FA_3 Port 0_3 Wake-up on Falling Edge enable ENABLE, wake-up enabled DISABLE, wake-up disabled FA_2 Port 0_2 Wake-up on Falling Edge enable ENABLE, wake-up enabled DISABLE, wake-up disabled FA_1...
Page 58 MOTIX™ TLE985xQX Power Management Unit (PMU) Wake Configuration GPIO Port 1 Register PMU_WAKE_CNF_GPIO1 Offset Reset Value Wake Configuration GPIO Port 1 Register Table 15 CYC_ CYC_ CYC_ CYC_ FA_4 FA_2 FA_1 FA_0 RI_4 RI_2 RI_1 RI_0 Field Bits Type Description 31:21 Reserved Always read as 0...
Page 59 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description FA_0 Port 1_0 Wake-up on Falling Edge enable ENABLE, wake-up enabled DISABLE, wake-up disabled Reserved Always read as 0 RI_4 Port 1_4 Wake-up on Rising Edge enable ENABLE, wake-up enabled DISABLE, wake-up disabled Reserved Always read as 0...
Page 60 MOTIX™ TLE985xQX Power Management Unit (PMU) PMU Wake-up Timing Register These registers are for wake-up control of all wake-up capable general purpose inputs outputs PMU_CNF_WAKE_FILTER Offset Reset Value PMU Wake-up Timing Register Table 16 CNF_GPI CNF_ CNF_ O_FT MON* LIN* Field Bits Type...
Page 61: Pmu Wake Up Status Register
MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description 31:8 Reserved Always read as 0 LIN_WAKE_EN Lin Wake enable Wake Disabled, Wake enabled, Reserved Always read as 0 Reserved Always read as 0 Table 17 RESET of PMU_LIN_WAKE_EN Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 62 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description VDDEXT_UV Wake VDDEXT Undervoltage Note: this register is cleared automatically by read operation No wake-up detected, wake-up detected, VDDEXT_OT Wake VDDEXT Overtemperature Note: this register is cleared automatically by read operation No wake-up detected, wake-up detected, PMU_OT...
Page 63: Gpio Port Wake Up Status Register
MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description MON1_WAKE_STS Status of MON1 Note: this register is cleared automatically by read operation No wake-up detected, wake-up detected, Reserved Always read as 0 FAIL Wake-up after any Fail, which is a logical OR combination of PMU_OT, VDDEXT_OT, VDDEXT_UV No Wake-up occurred, Wake-up occurred,...
Page 64 MOTIX™ TLE985xQX Power Management Unit (PMU) GPIO Port wake status register PMU_GPIO_WAKE_STATUS Offset Reset Value GPIO Port wake status register Table 19 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 1_S* 1_S* 1_S* 1_S* 0_S* 0_S* 0_S* 0_S* 0_S* 0_S* Field...
Page 65 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description GPIO0_STS_5 Status of GPIO0_5 Note: This flag is cleared by read operation. No wake-up detected, wake-up detected, GPIO0_STS_4 Status of GPIO0_4 Note: This flag is cleared by read operation. No wake-up detected, wake-up detected, GPIO0_STS_3 Status of GPIO0_3...
Page 66: Cyclic Management Unit (Cmu)
MOTIX™ TLE985xQX Power Management Unit (PMU) Cyclic Management Unit (CMU) The cyclic management unit is responsible for controlling the timing sequence in cyclic sense or cyclic wake operation. The unit operates with the LP_CLK2 clock. 6.6.1 Cyclic Sense Mode To select a dedicated MONx pin for cyclic sense mode, the bits MONx_EN, MONx_CYC, and on or both of the MONx_RISE and MONx_FALL bits must be set in the PMU_MON_CNF1 register.
Page 67: Configuration Of Cyclic Sense Mode
MOTIX™ TLE985xQX Power Management Unit (PMU) Dead Cycle Sense MONx LP_CLK VDDC 1.5V 0.9V PMU_RST_STS RESET PIN HS_ON HS_CYC_ON HS_State SYSTEM_STATE Stop Stop Active Timing_Diagram_ Stop_Mode_Exit_Cyclic_Sense_Customer.vsd Figure 18 Timing Diagram for Cyclic Sense 6.6.1.1 Configuration of Cyclic Sense Mode The configuration of cyclic sense mode is shown in Figure User Manual Rev.
Page 68 MOTIX™ TLE985xQX Power Management Unit (PMU) Configure MONx for Cyclic Sense PMU_MO N_CNF1: MO Nx_EN = 1, MO Nx_CYC = 1, MO Nx_RISE = 1 and/or MONx_FALL = 1 Configure Cyclic Sense Timer PMU_SLEEP: CYC_SENSE_M03, CYC_SENSE_E01, CYC_SENSE_S_DEL Enable Cyclic Sense Mode PMU_SLEEP: CYC_SENSE_EN = 1 Configure HS Switch...
Page 69: Cyclic Wake Mode
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.6.2 Cyclic Wake Mode Cyclic Wake mode provides a synchronous wake-up after a predefined time interval in Sleep Mode or Stop Mode. Once the time interval is elapsed the PMU enters the Startup Mode and proceeds to Active Mode where the software takes over the system control.
Page 70: Cyclic Mode Configuration Registers (Cycmu)
MOTIX™ TLE985xQX Power Management Unit (PMU) 6.6.3.1 Cyclic Mode Configuration Registers (CYCMU) Cyclic Sense Mode Configuration The off time (dead time) in Cyclic Sense Mode is calculated by following formula: ⋅ ⋅ where E1E0 represents exponent, which configured register bits PMU_SLEEP.CYC_SENSE_E01<1:0>.
Page 71 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description 31:27 Reserved Always read as 0 CYC_SENSE_S_DEL 26:24 Sample Delay in Cyclic Sense Delay time after HS/VDDEXT is turned on to the time when MONx/GPIOx are sensed. 0, 18 µs typ. 1, 27 µs typ.
Page 72 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description CYC_WAKE_EN Enabling Cyclic Wake This bit enables the cyclic wake feature for the power save modes. Disable, Cyclic Wake disabled Enable, Cyclic Wake enabled EN_0V9_N Enables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode Enable, Output voltage reduction enabled Disable, Output voltage reduction disabled...
Page 73 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description CNF_ON CNF_ON Function Cyclic on time for GL1_CYC_ON and GL2_CYC_ON 50 us, 100 us, 200 us, 400 us, GL2_HOLD_ON GL2 Hold Mode On This bit enables the hold mode of GL2 Disable, Enable, GL2_CYC_ON...
Page 74: Reset Management Unit (Rmu)
MOTIX™ TLE985xQX Power Management Unit (PMU) Reset Management Unit (RMU) The RMU controls the reset behavior of the entire device. The master reset of the device is the power-on reset of the PMU itself. This reset is generated by the Power Down Supply and it is released when the battery voltage (Vs) reaches the minimum supply voltage for Active Mode.
Page 75 MOTIX™ TLE985xQX Power Management Unit (PMU) In case of a Sleep Mode exit a similar sequence used for battery ramp-up starts. If this sequence ends successfully then the PMU also releases the reset of the MCU. From the MCU point of view there is no difference to the battery ramp-up.
Page 76 MOTIX™ TLE985xQX Power Management Unit (PMU) RESET_TYPE_0 RESET_TYPE_1 RESET_TYPE_2 RESET_TYPE_3 RESET_TYPE_4 XSFR _reset_types_customer.vsd Figure 21 Reset Types of SFRS provided by the RMU Out of these above listed resets mainly five reset types are derived: • RESET_TYPE_0 contains: – PMU_VS_POR: this reset is issued when the power down supply detects undervoltage •...
Page 77: Register Definition
MOTIX™ TLE985xQX Power Management Unit (PMU) – PMU_FAIL – WDT_FAIL Every register has its own reset type listed. In the Power Management Unit SFRs following reset types are used: • RESET_TYPE_0 • RESET_TYPE_1 • RESET_TYPE_2 • RESET_TYPE_3 6.7.1 Register Definition Table 23 Register Overview Register Short Name...
Page 78 MOTIX™ TLE985xQX Power Management Unit (PMU) Reset Blind Time Register PMU_CNF_RST_TFB Offset Reset Value Reset Blind Time Register Table 24 RST_TFB Field Bits Type Description 31:2 Reserved Always read as 0 RST_TFB Reset Pin Blind Time Selection Bits These bits select the blind time for the reset input sampling.
Page 79 MOTIX™ TLE985xQX Power Management Unit (PMU) Reset Status Register The PMU_RESET_STS register shows every executed reset request. The PMU writes the corresponding register bit of an executed reset. To clear the information of the PMU_RST_STS register the user must overwrite the corresponding bit with a logic zero.
Page 80 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description PMU_ExtWDT External Watchdog (WDT1) Reset Flag No Reset, No External Watchdog reset executed Reset, External Watchdog reset executed PMU_ClkWDT Clock Watchdog (CLKWDT) Reset Flag No Reset, No Clock Watchdog reset executed Reset, Clock Watchdog reset executed PMU_LPR Low Priority Resets (see PMU_RST_STS2)
Page 81: Pmu Data Storage Area
MOTIX™ TLE985xQX Power Management Unit (PMU) PMU Data Storage Area The PMU provides the possibility for the system to store data in registers which will retain their values, when the device is set to sleep mode. In sum there are 12 x 8 Bit available. 6.8.1 Register Definition Table 26...
Page 82 MOTIX™ TLE985xQX Power Management Unit (PMU) Field Bits Type Description DATA1 15:8 DATA1 Storage Byte 2nd byte of storage area DATA0 DATA0 Storage Byte 1st byte of storage area Table 27 RESET of PMU_GPUDATA0to3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_0...
Page 83 MOTIX™ TLE985xQX Power Management Unit (PMU) DATA11 DATA10 DATA9 DATA8 Field Bits Type Description DATA11 31:24 DATA11 Storage Byte 12th byte of storage area DATA10 23:16 DATA10 Storage Byte 11th byte of storage area DATA9 15:8 DATA9 Storage Byte 10th byte of storage area DATA8 DATA8 Storage Byte 9th byte of storage area...
Page 84: System Control Unit - Digital Modules (Scu-Dm)
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) System Control Unit - Digital Modules (SCU-DM) Features • Flexible clock configuration features • Reset management of all system resets • System modes control for all power modes (active, power down, sleep) •...
Page 85: Block Diagram
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.2.1 Block Diagram on signals to digital peripherals; status signals from digital peripherals PMCU PCLK LP_CLK PCLK MI_CLK INTOSC INTISR<23:0> TFILT_CLK PMU_1V5DidPOR PMU_PIN PMU_ExtWDT PMU_IntWDT MISC Control MODPISELx PMU_SOFT PMU_Wake RESET_TYPE_3 RESET_TYPE_4 P0_POCONy.PDMx Port Control...
Page 86 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) – PMU_SOFT; Software reset – PMU_Wake; Stop Mode exit with reset – Reset_Type_3; Peripheral reset (contains all resets) – Reset_Type_4; Peripheral reset (without SOFT and WDT reset) • Port Control: – P0_POCONy.PDMx; driver strength control –...
Page 87: Scu Register Overview
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.2.2 SCU Register Overview This chapter contains an overview of all SCU Registers. 7.2.2.1 Register Map Table 31 lists the addresses of the SCU SFRs. Table 30 shows the SCU module base address. Table 30 Register Address Space Module...
Page 88 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 31 Register Overview SCU Module (cont’d) Register Short Name Register Long Name Offset Address Reset Value SCU_SYS_STRTUP_ST System Startup Status Register Table 106 SCU_WDTREL Watchdog Timer Reload Register Table 97 SCU_WDTWINB Watchdog Window-Boundary Count Table 100...
Page 89 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 31 Register Overview SCU Module (cont’d) Register Short Name Register Long Name Offset Address Reset Value SCU_EDCSCLR Error Detection and Correction Status Clear Table 103 Register SCU_STACK_OVFCLR Stack Overflow Status Clear Register Table 114 SCU_STACK_OVF_CTR Stack Overflow Control Register...
Page 90: Clock Generation Unit
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Clock Generation Unit The Clock Generation Unit (CGU) provides a flexible clock generation for TLE985xQX. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption.
Page 91: Clock Control Unit
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.2 Clock Control Unit The Clock Control Unit (CCU) receives the clock from the internal input clock f , or the low-precision input INTOSC clock f . In normal operation, the system is expected to run on the f clock output.
Page 92 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Analog Subsystem / PBA0 / PBA1 UART 1/2, Timer 2/21, Baudgen 1/2 ADC1_CLK_DIV DPP1_CLK_DIV ADC1_CLK DPP1_CLK DPP1 PCLK2 BRDRV_TFILT_DIV BRDRV_TFILT_CLK BRDRV_CLK_DIV Bridge Driver BRDRV_CLK PCLK2 Clock APCLK2FAC Control Unit TFILT_CLK TFILT_CLK Analog Peripherals MI_CLK...
Page 93: Clock Tree
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.2.1 Clock Tree PBA1 PCLK SCU_DM - AHB PCLK SCU_DM / BaudRateGen PCLK PCLK UART1 / 2 - AHB UART1 / 2 - Kernel PCLK Timer 2 -AHB PBA1 PBA1 Timer 2 - Kernel SCU_PM PCLK PCLK...
Page 94: Startup Control For System Clock
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.2.2 Startup Control for System Clock Typically when the TLE985xQX starts up after reset, the LP_CLK is selected by hardware to provide the system frequency f . CPU runs based on this system frequency during startup operation by boot firmware (unless otherwise specified and configured by firmware).
Page 95: Cgu Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.4 CGU Registers The registers of the clock generation unit for oscillator control are not affected by the watchdog timer (WDT) reset and soft reset. Therefore the system clock configuration and frequency is maintained across these types of reset.
Page 96: System Clock Control Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.4.1 System Clock Control Registers The clock source for the system is selected via register SYSCON0. System Control Register 0 SCU_SYSCON0 Offset Reset Value System Control Register 0 Table 32 SYSCLKS NVMCLKF Field Bits...
Page 97 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description NVMCLKFAC NVM Access Clock Factor This bit field defines the factor by which the system clock is divided down, with respect to the synchronous NVMACCCLK clock. Note: Can only be changed via dedicated BROM routine. div 1, Divide by 1 div 2, Divide by 2 div 3, Divide by 3...
Page 98 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Clock Control Register 2 SCU_CMCON2 Offset Reset Value Clock Control Register 2 Table 33 PBA0 CLK* rwpw Field Bits Type Description 31:1 Reserved This bit field is always read as zero. PBA0CLKREL rwpw PBA0 Clock Divider...
Page 99: Analog Peripherals Clock Control Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.4.2 Analog Peripherals Clock Control Registers The clock frequency for the analog modules is selected via register APCLK. The APCLK is used as operating clock for all analog peripherals. For this reason it is important to choose always the required frequency range, if system clock is changed.
Page 100 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Analog Peripheral Clock Register The clock source for the analog modules is selected via register APCLK. SCU_APCLK Offset Reset Value Analog Peripheral Clock Register Table 35 CPCL CPCL BGCL BGCL K_D* K_S* K_D* K_S*...
Page 101 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description APCLK2FAC 12:8 Slow Down Clock Divider for TFILT_CLK Generation This setting is effective only when the APCLK_SET = 1. There are 32 possible clock divider values according to the following examples: 00000 div 1, f...
Page 102 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description APCLK1FAC Analog Module Clock Factor This bit field defines the factor by which the system clock is divided down, with respect to the synchronous MI_CLK clock. Note: The setting is only overtaken if APCLK2FAC setting is greater or equal than APCLK1FAC div 1, Divide by 1...
Page 103 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) ADC1 Peripheral Clock Register SCU_ADC1_CLK Offset Reset Value ADC1 Peripheral Clock Register Table 37 DPP1_CL ADC1_CLK_DIV K_DIV Field Bits Type Description 31:10 Reserved Returns 0 if read; should be written with 0. DPP1_CLK_DIV ADC1 Post processing clock divider This bit field defines the factor by which the system clock...
Page 104 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 37 RESET of SCU_ADC1_CLK Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000 RESET_TYPE_4 TRIM_100_TP 00000000 RESET User Manual Rev. 2.0 2023-08-09...
Page 105 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) BRDRV Peripheral Clock Register SCU_BRDRV_CLK Offset Reset Value BDrv Peripheral Clock Register Table 38 BRDRV_C BRDRV_TFILT_DIV LK_DIV Field Bits Type Description 31:13 Reserved Returns 0 if read; should be written with 0. User Manual Rev.
Page 106 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description BRDRV_TFILT_DIV 12:8 Slow Down Clock Divider for TFILT_CLK Generation This setting is effective only when the APCLK_SET = 1. There are 32 possible clock divider values according to the following examples: 00000 div 1, f...
Page 107 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description BRDRV_CLK_DIV Bridge Driver Module Clock Factor This bit field defines the factor by which the system clock is divided down, with respect to the synchronous MI_CLK clock. Note: The setting is only overtaken if BRDRV_TFILT_DIV setting is greater or equal...
Page 108 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Analog Peripheral Clock Status Register The clock source for the analog modules is selected via register APCLK. SCU_APCLK_STS Offset Reset Value Analog Peripheral Clock Status Register Table 39 BRDR APCL V_C* K3S* APCLK2S APCL...
Page 109 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description APCLK2STS Analog Peripherals Clock Status This bit field reflects the analog peripheral clock source status that is used as system clock for the analog module operation. The implemented clock watchdog (see Chapter SCU_PM) is monitoring the frequency of the analog subsystem.
Page 110 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description APCLK1STS Analog Peripherals Clock Status This bit field reflects the analog peripheral clock source status that is used as system clock for the analog module operation. The implemented clock watchdog (see Chapter SCU_PM) is monitoring the frequency of the analog subsystem.
Page 111 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Analog Peripheral Clock Status Clear Register The clock source for the analog modules is selected via register APCLK. SCU_APCLK_SCLR Offset Reset Value Analog Peripheral Clock Status Clear Table 40 Register APCL K3S* APCL APCL...
Page 112: External Clock Control Register
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.3.4.3 External Clock Control Register This register controls the setting of external clock for CLKOUT. Clock Output Control Register SCU_COCON Offset Reset Value Clock Output Control Register Table 41 COUT COUT TLEN COREL Field...
Page 113 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description COUTS0 Clock Out Source Select Bit 0 This bit takes effect only when COUTS1 is set to 1. This bit must always be set to 1. If it is set to 1, the clock output frequency is determined by the settings of the COREL bit field.
Page 114: Reset Control
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Reset Control This section describes the types of reset and the effects of each reset on the TLE985xQX. 7.4.1 Types of Reset The following reset types are recognized by the TLE985xQX. •...
Page 115: Module Reset Behavior
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.4.3 Module Reset Behavior Table 42 gives an overview on how the various modules or functions of the TLE985xQX are affected with respect to the reset type. A “n” means that the module/function is reset to its default state. Refer to Table 42 for effective reset as priority.
Page 116: Functional Description Of Reset Types
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.4.4 Functional Description of Reset Types This section describes the definition and controls depending on the reset source. 7.4.4.1 Power-On / Brown-out Reset Power-on reset is the highest level reset whereby the whole system is powered up and reset. Brown-out reset occurs when any required voltage drops below its minimum threshold.
Page 117: Reset Register Description
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.4.5 Reset Register Description Reset Control Register SCU_RSTCON Offset Reset Value Reset Control Register Table 43 LOCK LOCK UP_* rwpw Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. LOCKUP_EN rwpw Lockup Reset Enable Flag...
Page 118: Booting Scheme
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 43 RESET of SCU_RSTCON Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000 RESET_TYPE_4 RESET_TYPE_3 00000000 RESET_TYPE_3 7.4.6 Booting Scheme After any power-on reset, brown-out reset, hardware reset, WDT1 reset or wake-up reset, the pins TMS, P0.0, P0.2 together choose different modes.
Page 119: Power Management
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Power Management This section describes the features and functionality provided for power management of the device. 7.5.1 Overview The TLE985xQX power-management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application.
Page 120: Functional Description
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) In Sleep Mode, the power supply to the whole MCU subsystem is removed. On detection of wake-up event, a system reset is generated and the MCU is reset to default configuration then restart operation as initialized. The priority for entry to the power-save modes starting from the highest is Sleep Mode, Stop Mode, then Slow Down Mode.
Page 121 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Active Mode Set Flag PMCON0.PD Send Event Execute WFE instruction to Stop Mode clear Event Latch Execute WFE instruction to Stop Mode enter Stop Mode Stop Mode Figure 29 Stop Mode Entry Programming Sequence Exiting Stop Mode Stop Mode can be exited by active edge on the enabled wake-up pin(s) or by asserting the hard reset pin.
Page 122: Sleep Mode
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.5.2.2.1 Usage of Arm® Cortex®-M0 Core Low Power Modes for Stop and Sleep Mode The Arm® Cortex®-M0 Core provides two low power modes, which are Sleep and Deep sleep. For stop mode of the system the Deep sleep will be used.
Page 123: Register Description
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.5.3 Register Description Power Mode Control Register 0 SCU_PMCON0 Offset Reset Value Power Mode Control Register 0 Table 45 rwpw rwh1 rwh1 Field Bits Type Description 31:4 Reserved Returns 0 if read; should be written with 0. rwpw Slow Down Mode Enable.
Page 124: Interrupt Management
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Management This section describes the management of interrupts by the system control unit. 7.6.1 Overview The Interrupt Management sub-module in the SCU controls the non-core-generated interrupt requests to the core. The core has one non-maskable interrupt (NMI) node and total 24 maskable interrupt nodes. Figure 30 shows the block diagram of the Interrupt Management sub-module.
Page 125: Extended Interrupts
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) EINTx EXINTx IRCONy INTx IEN0/1 EXINTx EXICON0/1/2 Figure 31 Interrupt Request Generation of External and Peripheral Interrupts 7.6.1.2 Extended Interrupts Extended interrupts are for non-core on-chip peripherals for core-external trigger of interrupt requests to the core.
Page 126: Interrupt Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.6.3 Interrupt Registers Interrupt registers are used for interrupt node enable, external interrupt control, interrupt flags and interrupt priority setting. Table 46 Register Address Space Module Base Address End Address Note 50005000 50005FFF Table 47...
Page 127: Interrupt Node Enable Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.6.3.1 Interrupt Node Enable Registers Register IEN0 contains the global interrupt masking bit (EA), which can be cleared to block all pending interrupt requests at once. The NMI interrupt vector is shared by a number of sources, each of which can be enabled or disabled individually via register NMICON.
Page 128 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Enable Register 0 SCU_IEN0 Offset Reset Value Interrupt Enable Register 0 Table 48 Field Bits Type Description Global Interrupt Mask disable, All pending interrupt requests (except NMI) are blocked from the core. enable, Pending interrupt requests are not blocked from the core.
Page 129 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Vector Table Reallocation Register SCU_VTOR Offset Reset Value Vector Table Reallocation Register Table 49 VTOR_BY rwpw Field Bits Type Description 31:2 Reserved Returns 0 if read; should be written with 0. VTOR_BYP rwpw Vector Table Bypass Mode...
Page 130 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) NMI Control Register SCU_NMICON Offset Reset Value NMI Control Register Table 50 NMIS NMIS NMIE NMIM NMIO NMIO NMIW Field Bits Type Description 31:9 Reserved Returns 0 if read; should be written with 0. NMISTOF Stack Overflow NMI Enable disable, Stack overflow NMI is disabled.
Page 131: External Interrupt Control Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.6.3.2 External Interrupt Control Registers The external interrupts, EXT_INT[2:0], are driven into SCU from the ports. External interrupts can be positive, negative or double edge triggered. Register EXICON0 specifies the active edge for the external interrupt. If the external interrupt is positive (negative) edge triggered, the external source must hold the request pin low (high) for at least one CCLK cycle, and then hold it high (low) for at least one CCLK cycle to ensure that the transition is recognized.
Page 132 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description EXINT0 External Interrupt 0 Trigger Select enable, Interrupt disabled. rising, Interrupt on rising edge. falling, Interrupt on falling edge. both, Interrupt on both rising and falling edge. Table 51 RESET of SCU_EXICON0...
Page 133 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description MON2 MON2 Input Trigger Select disable, external interrupt MON is disabled. rising, Interrupt on rising edge. falling, Interrupt on falling edge. both, Interrupt on both rising and falling edge. MON1 MON1 Input Trigger Select disable, external interrupt MON is disabled.
Page 134: Interrupt Flag Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.6.3.3 Interrupt Flag Registers The interrupt flags for the different interrupt sources are located in several special function registers. This section describes the interrupt flags located in system registers or external interrupts belonging to system. Other interrupt flags located in respective module registers are described in the specific module chapter.
Page 135 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description EXINT0F Interrupt Flag for External Interrupt 0x on falling edge This bit is set by hardware and can only be cleared by software. Int, Interrupt on falling edge event has not occurred. no Int, Interrupt on falling edge event has occurred.
Page 136 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description EXINT1RC Interrupt Flag for External Interrupt 1x on rising edge not cleared, Interrupt event is not cleared. cleared, Interrupt event is cleared EXINT0FC Interrupt Flag for External Interrupt 0x on falling edge not cleared, Interrupt event is not cleared.
Page 137 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description MON4R Interrupt Flag for MON4x on rising edge This bit is set by hardware and can only be cleared by software. No Int, Interrupt on rising edge event has not occurred.
Page 138 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 1 Clear SCU_IRCON1CLR Offset Reset Value Interrupt Request 1 Clear Register Table 57 MON4 MON4 MON3 MON3 MON2 MON2 MON1 MON1 Field Bits Type Description 31:10 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 139 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 57 RESET of SCU_IRCON1CLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 140 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 2 SCU_IRCON2 Offset Reset Value Interrupt Request Register 2 Table 58 RIR1 TIR1 EIR1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 141 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 2 Clear SCU_IRCON2CLR Offset Reset Value Interrupt Request 2 Clear Register Table 59 RIR1 TIR1 EIR1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 142 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 3 SCU_IRCON3 Offset Reset Value Interrupt Request Register 3 Table 60 RIR2 TIR2 EIR2 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 143 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 3 Clear SCU_IRCON3CLR Offset Reset Value Interrupt Request 3 Clear Register Table 61 RIR2 TIR2 EIR2 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 144 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 4 SCU_IRCON4 Offset Reset Value Interrupt Request Register 4 Table 62 CCU6 CCU6 CCU6 CCU6 Field Bits Type Description 31:21 Reserved Returns 0 if read; should be written with 0. CCU6SR3 Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by...
Page 145 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 62 RESET of SCU_IRCON4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 146 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 4 Clear SCU_IRCON4CLR Offset Reset Value Interrupt Request 4 Clear Register Table 63 CCU6 CCU6 SR3C SR2C CCU6 CCU6 SR1C SR0C Field Bits Type Description 31:21 Reserved Returns 0 if read; should be written with 0. CCU6SR3C Interrupt Flag 1 for CCU6 Not Cleared, Interrupt event is not cleared.
Page 147 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 5 SCU_IRCON5 Offset Reset Value Interrupt Request Register 5 Table 64 WAKE Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. WAKEUP Interrupt Flag for Wakeup This bit is set by hardware and can only be cleared by software.
Page 148 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Interrupt Request Register 5 Clear SCU_IRCON5CLR Offset Reset Value Interrupt Request 5 Clear Register Table 65 WAKE Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. WAKEUPC Clear Flag for Wakeup Interrupt Not Cleared, Interrupt event is not cleared.
Page 149 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Timer and Counter Control/Status Register SCU_GPT12IRC Offset Reset Value Timer and Counter Control/Status Register Table 66 GPT1 GPT2 GPT2 GPT1 GPT1 GPT1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 150 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 66 RESET of SCU_GPT12IRC Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 151 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Timer and Counter Control/Status Register SCU_GPT12ICLR Offset Reset Value Timer and Counter Control/Status Clear Table 67 Register GPT1 GPT2 GPT2 GPT1 GPT1 GPT1 2CRC Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 152 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 67 RESET of SCU_GPT12ICLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 153 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) NMI Status Register Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. These include all the flags of NMISR register: FNMIWDT, FNMIOT, FNMIOWD, FNMIMAP, and indirectly, FNMIECC and FNMISUP. In the case of NMIs with shared source i.e.
Page 154 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description FNMIOWD Oscillator Watchdog NMI Flag This bit is set by hardware and can only be cleared by software. no Int, No oscillator watchdog NMI has occurred. Int, Oscillator watchdog event has occurred. FNMIOT Overtemperature NMI Flag This bit is set by hardware and can only be cleared by...
Page 155 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) NMI Status Register Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. These include all the flags of NMISR register: FNMIWDT, FNMIOT, FNMIOWD, FNMIMAP, and indirectly, FNMIECC and FNMISUP. In the case of NMIs with shared source i.e.
Page 156: Interrupt Related Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.6.4 Interrupt Related Registers Several interrupt related registers are located in the SCU. 7.6.4.1 Interrupt Event Enable Control The following registers collect the interrupt enable bits for all interrupt events which do not have enable bits on their respective module level.
Page 157 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 70 RESET of SCU_MODIEN1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 158 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Peripheral Interrupt Enable Register 2 SCU_MODIEN2 Offset Reset Value Peripheral Interrupt Enable Register 2 Table 71 TIEN RIEN EXIN TIEN RIEN T2_* Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. TIEN2 UART 2 Transmit Interrupt Enable Disable, Transmit interrupt is disabled...
Page 159 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Peripheral Interrupt Enable Register 3 SCU_MODIEN3 Offset Reset Value Peripheral Interrupt Enable Register 3 Table 72 Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. External Interrupt Enable Disable, disabled Enable, enabled...
Page 160 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Peripheral Interrupt Enable Register 4 SCU_MODIEN4 Offset Reset Value Peripheral Interrupt Enable Register 4 Table 73 Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. External Interrupt Enable Disable, disabled Enable, enabled...
Page 161 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Monitoring Input Interrupt Enable Register SCU_MONIEN Offset Reset Value Monitoring Input Interrupt Enable Register Table 74 MON4 MON3 MON2 MON1 Field Bits Type Description 31:5 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 162 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) General Purpose Timer 12 Interrupt Enable Register SCU_GPT12IEN Offset Reset Value General Purpose Timer 12 Interrupt Enable Table 75 Register CRIE T6IE T5IE T4IE T3IE T2IE Field Bits Type Description 31:6 Reserved Returns 0 if read;...
Page 163: Nmi Event Flags Handling
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) • NMICON • NMISR • IRCON0, IRCON1, IRCON3, IRCON4 • EXICON0 • MODIEN1, MODIEN2 All registers, except MODIENx, are described in the Interrupt System Chapter 12.9. 7.6.5 NMI Event Flags Handling Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset.
Page 164: General Port Control
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) General Port Control The SCU contains control registers for the selection of: • alternate input functions of UART, Timers and External Interrupts (Section 7.7.2) • port output driver strength and temperature compensation (Section 7.7.3) For functional description of GPIO ports, refer to...
Page 165: Input Pin Function Selection
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 77 Timer21 Input Signal Selection MODPISEL1. MODPISEL2. MODPISEL2. Description T21EXCON T21EXISCNF T21EXIS Bit Field Bit Field Bit Field MON4 lin_rxd_i reserved cc6_ch0 cc6_ch1 cc6_cout60 cc6_cout61 cc6_cout62 cc6_cout63 7.7.2 Input Pin Function Selection MODPISELx registers control the selection of the input pin functions.
Page 166 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description SSC12_M_SCK_OUTSEL Output selection for SSC12_M_SCK Chapter 15.4. SSC1, SSC1_M_SCK SSC2, SSC2_M_SCK 15:8 Reserved Returns 0 if read; should be written with 0. U_TX_CONDIS UART1 TxD Connection Disable Enable, UART1-TX-Output -LIN Transmitter TX Input Connection available.
Page 167 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description EXINT0IS External Interrupt 0 Input Select EXINT0_0, External Interrupt Input EXINT0_0 is selected. EXINT0_1, External Interrupt Input EXINT0_1 is selected. EXINT0_2, External Interrupt Input EXINT0_2 is selected. EXINT0_3, External Interrupt Input EXINT0_3 is selected.
Page 168 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Peripheral Input Select Register 1 SCU_MODPISEL1 Offset Reset Value Peripheral Input Select Register 1 Table 79 T21E T2EX XCON Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. T21EXCON Timer 21 External Input Control MODPISEL, Timer 21 Input T21EX is selected...
Page 169 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Peripheral Input Select Register 2 SCU_MODPISEL2 Offset Reset Value Peripheral Input Select Register 2 Table 80 T21EXIS T2EXISC T21EXIS T2EXIS T21IS T2IS Field Bits Type Description 31:12 Reserved Returns 0 if read; should be written with 0. T21EXISCNF 11:10 Timer 21 External Input Select Configuration...
Page 170 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description T2IS Timer 2 Input Select T2_0, Timer 2 Input T2_0 is selected. T2_1, Timer 2 Input T2_1 is selected. T2_2, Timer 2 Input T2_2 is selected. RES, Reserved. Table 80 RESET of SCU_MODPISEL2...
Page 171: Port Output Control
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.7.3 Port Output Control Px_POCONy registers controls the output driver strength for each of the bidirectional port pin through the bit field PDMn, where x denotes the port number and n denotes the pin number. Port Output Control Register SCU_P0_POCON0 Offset...
Page 172 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description P0_PDM4 18:16 P0.4 Port Driver Mode Code Driver Strength and Edge Shape Strong-sharp, Strong driver and sharp edge mode Strong-med, Strong driver and medium edge mode Strong-soft , Strong driver and soft edge mode Weak, Weak driver Medium, Medium driver Medium, Medium driver...
Page 173 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description Reserved Returns 0 if read; should be written with 0. P0_PDM0 P0.0 Port Driver Mode Code Driver Strength and Edge Shape Strong-sharp, Strong driver and sharp edge mode Strong-med, Strong driver and medium edge mode Strong-soft , Strong driver and soft edge mode Weak, Weak driver...
Page 174 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Port Output Control Register SCU_P1_POCON0 Offset Reset Value Port Output Control Register Table 82 P1_PDM4 P1_PDM2 P1_PDM1 P1_PDM0 Field Bits Type Description 31:19 Reserved Returns 0 if read; should be written with 0. P1_PDM4 18:16 P1.4 Port Driver Mode...
Page 175 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description P1_PDM1 P1.1 Port Driver Mode Code Driver Strength and Edge Shape not used, Not used not used, Not used not used, Not Used Weak, Weak driver Medium, Medium driver Medium, Medium driver Medium, Medium driver Weak, Weak driver...
Page 176 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Temperature Compensation Control Register The TCCR register controls the temperature compensation of all the GPIO output port pins with strong drivers, i.e. on a device level. The TCCR register has no effect on output port pins that operate in the weak and medium driver modes.
Page 177: Gpt12 T3In/T4In Input Pin Function Selection
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.7.4 GPT12 T3IN/T4IN Input Pin Function Selection GPT12PISEL register control the selection of the input pin functions of T3INB and T4IND in GPT12. GPT12 Peripheral Input Select Register SCU_GPT12PISEL Offset Reset Value GPT12 Peripheral Input Select Register Table 84 GPT1...
Page 178: Differential Unit Trigger Enable
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 84 RESET of SCU_GPT12PISEL Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 Differential Unit Trigger Enable The Differential Unit inside DPP1 module requires enable signals for telling the processing when to accept and calculate a new result based on an incoming trigger signal.
Page 179: Differential Unit Trigger
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) GPT12_aux cc6_ch0 cc6_ch1 cc6_ch2 cout6_ch0 cout6_ch1 cout6_ch2 gpt12_t3 cout6_ch3 SCU_MODPISEL4.DU4TRIGEN cc6_ch0 cc6_ch1 cc6_ch2 cout6_ch0 cout6_ch1 DPP1 cout6_ch2 gpt12_t3 cout6_ch3 SCU_MODPISEL4.DU3TRIGEN DU Unit du_ext_en_i cc6_ch0 cc6_ch1 cc6_ch2 cout6_ch0 cout6_ch1 cout6_ch2 gpt12_t3 cout6_ch3 SCU_MODPISEL4.DU2TRIGEN cc6_ch0 cc6_ch1...
Page 180: Differential Unit Trigger Register
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.8.1.1 Differential Unit Trigger register Peripheral Input Select Register 4 SCU_MODPISEL4 Offset Reset Value Peripheral Input Select Register 4 Table 85 DU4TRIGGEN DU3TRIGGEN DU2TRIGGEN DU1TRIGGEN Field Bits Type Description 31:27 Reserved Returns 0 if read;...
Page 181 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description DU3TRIGGEN 18:16 Differential Unit Trigger Enable Note: These bits configure the enable input of the differential unit. CC60, CC60 is selected. CC61, CC61 is selected. CC62, CC62 is selected. COUT60, COUT60 is selected.
Page 182: Flexible Peripheral Management
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Flexible Peripheral Management The Flexible Peripheral Management sub-module provides the system designer greater control on the operational status of each individual digital peripheral. Peripherals which are not required for a particular functionality can be disabled by programming the assigned register bits which would gate off the clock inputs.
Page 183: Peripheral Management Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.9.1 Peripheral Management Registers Peripheral Management Control Register SCU_PMCON Offset Reset Value Peripheral Management Control Register Table 86 T21_ SSC2 GPT1 T2_D CCU_ SSC1 ADC1 _DIS 2_D* _DIS _DIS Field Bits Type Description 31:11...
Page 184 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description ADC1_DIS ADC1 Disable Request. Active high. Enable, ADC1 is in normal operation. (default) Disable, Request to disable the ADC. Table 86 RESET of SCU_PMCON Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 185: Module Suspend Control
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.10 Module Suspend Control When the On-Chip Debug Support (Debug Mode) is in Monitor Mode (halted_o from Arm® debug), timers in certain modules in TLE985xQX can be suspended based on the settings of their corresponding module suspend bits in register MODSUSP.
Page 186 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description T2_SUSP Timer2 Debug Suspend Bit No Suspend, Timer2 will not be suspended. Suspend, Timer2 will be suspended. T13SUSP Timer 13 Debug Suspend Bit When suspended, additionally the T13 PWM output is set to inactive level.
Page 187: Baud-Rate Generator
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.11 Baud-rate Generator The baud-rate generator in SCU is used to generate the baud rate for the UART module. See Chapter 19.6 the functional description. The SCU contains two of this registers. One is dedicated for UART1 and the other for UART2.
Page 188 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 88 RESET of SCU_BCON1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 189: Baud-Rate Generator Timer/Reload Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Baud Rate Control Register 2 SCU_BCON2 Offset Reset Value Baud Rate Control Register 2 Table 89 BR2_ BR2_PRE Field Bits Type Description 31:4 Reserved Returns 0 if read; should be written with 0. BR2_PRE Prescaler Bit Selects the input clock for f...
Page 190 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) BG should only be written if R = 0. Also this register should be present twice. One is for UART1 and the other for UART2. Baud Rate Timer/Reload Register, Low Byte 1 SCU_BGL1 Offset Reset Value...
Page 191 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Baud Rate Timer/Reload Register, Low Byte 2 SCU_BGL2 Offset Reset Value Baud Rate Timer/Reload Register, Low Byte Table 91 BG2_FD_SEL Field Bits Type Description 31:5 Reserved Returns 0 if read; should be written with 0. BG2_FD_SEL Fractional Divider Selection Selects the fractional divider to be n/32, where n is the...
Page 192 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Baud Rate Timer/Reload Register SCU_BG1 Offset Reset Value Baud Rate Timer/Reload Register Table 92 BG1_TIM_VALUE BG1_BR_VALUE Field Bits Type Description 31:27 Reserved Returns 0 if read; should be written with 0. BG1_TIM_VALUE 26:16 Baud Rate Timer Value...
Page 193 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Baud Rate Timer/Reload Register SCU_BG2 Offset Reset Value Baud Rate Timer/Reload Register Table 93 BG2_TIM_VALUE BG2_BR_VALUE Field Bits Type Description 31:27 Reserved Returns 0 if read; should be written with 0. BG2_TIM_VALUE 26:16 Baud Rate Timer Value...
Page 194: Lin Break And Sync Byte Detection
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.12 LIN Break and Sync Byte Detection Hardware logic is implemented in the SCU to support LIN Break and Synch Byte detection. See Chapter 19.7 for the functional description. BCON1 BGL1 cpu_fbr1_o Baudrate-Gen1 UART 1...
Page 195 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description SYNEN End of SYN Byte and SYN Byte Error Interrupts Enable Disable, End of SYN Byte and SYN Byte Error Interrupts are not enabled. Enable, End of SYN Byte and SYN Byte Error Interrupts are enabled.
Page 196 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) LIN Status Clear Register SCU_LINSCLR Offset Reset Value LIN Status Clear Register Table 95 ERRS EOFS BRKC Field Bits Type Description 31:6 Reserved Returns 0 if read; should be written with 0. ERRSYNC SYN Byte Error Interrupt Flag This bit is set by software and can only be cleared by...
Page 197: Watchdog Timer
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.13 Watchdog Timer There are two watchdog timers in the system: SCU Watchdog Timer (WDT) within TLE985xQX, and external watchdog timer (WDT1). The description in this section refers to the SCU WDT. The Watchdog Timer is a sub-module in the System Control Unit (SCU).
Page 198: Functional Description
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.13.1 Functional Description The Watchdog Timer is a 16-bit timer, which is incremented by a count rate of f /2 or f /128. This 16-bit PCLK PCLK timer is realized as two concatenated 8-bit timers. The upper 8 bits of the Watchdog Timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time.
Page 199 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) The period PWDT between servicing the Watchdog Timer and the next overflow can be determined by the following formula: (7.1) × × × WDTIN – WDTREL -------------------------------------------------------------------------------------------------- PCLK If the Window-Boundary Refresh feature of the Watchdog Timer is enabled, the period P between servicing the Watchdog Timer and the next overflow is shortened if WDTWINB is greater than WDTREL.
Page 200: Register Description
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.13.2 Register Description The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bit-addressable read-only register. The operation of the Watchdog Timer is controlled by its bit- addressable Watchdog Timer Control Register WDTCON.
Page 201 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Watchdog Timer Reload Register SCU_WDTREL Offset Reset Value Watchdog Timer Reload Register Table 97 WDTREL Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. WDTREL Watchdog Timer Reload Value (for the high byte of WDT) Table 97...
Page 202 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Watchdog Timer Control Register SCU_WDTCON Offset Reset Value Watchdog Timer Control Register Table 98 WINB WDTP WDTE WDTR WDTI Field Bits Type Description 31:6 Reserved Returns 0 if read; should be written with 0. WINBEN Watchdog Window-Boundary Enable Disable, Watchdog Window-Boundary feature is disabled.
Page 203 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 98 RESET of SCU_WDTCON Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 204 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Watchdog Timer SCU_WDT Offset Reset Value Watchdog Timer Table 99 Field Bits Type Description 31:16 Reserved Returns 0 if read; should be written with 0. 15:0 Watchdog Timer Current Value Table 99 RESET of SCU_WDT Register Reset Type...
Page 205: Error Detection And Correction Control For Memories
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Watchdog Window-Boundary Count SCU_WDTWINB Offset Reset Value Watchdog Window-Boundary Count Table 100 WDTWINB Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. WDTWINB Watchdog Window-Boundary Count Value This value is programmable.
Page 206 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) NVMI Field Bits Type Description 31:3 Reserved Returns 0 if read; should be written with 0. NVMIE NVM Double Bit ECC Error Interrupt Enable Disable, No NMI is generated when a double bit ECC error occurs reading NVM.
Page 207: Error Detection And Correction Status Register
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.14.2 Error Detection and Correction Status Register The EDCSTAT register contains the status flags of ECC errors when read these memories. The corresponding flags for the IRAM are not more necessary, because IRAM was removed. Error Detection and Correction Status Register SCU_EDCSTAT Offset...
Page 208 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 102 RESET of SCU_EDCSTAT Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 0000 0000 RESET_TYPE_4 Error Detection and Correction Status Clear Register SCU_EDCSCLR Offset Reset Value Error Detection and Correction Status Clear Table 103 Register...
Page 209 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 103 RESET of SCU_EDCSCLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 210: Miscellaneous Control
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.15 Miscellaneous Control This module consists of the Bit-Protection Scheme and general system control SFRs. 7.15.1 Bit Protection Register The Bit-Protection Scheme disallows direct software writing of selected bits (i.e. Protected bits) by the SFR PASSWD.
Page 211 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description PW_MODE Bit-Protection Scheme Control Bit These two bits cannot be written directly. To change the value between 11 and 00 , the bit field PASS must be written with 11000 , only then the MODE[1:0] will be registered.
Page 212: System Control And Status Registers
MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) 7.15.2 System Control and Status Registers The system startup status register provide information to the user about the system initialisation with the user programmable 100 TP Page at startup. These register is written by firmware. This register SYS__STS is reset by reset_type_4.
Page 213 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) NVM Protection Status Register This register reflects the NVM Protection Status. It is written by firmware only. SCU_NVM_PROT_STS Offset Reset Value NVM Protection Status Register Table 107 DAT_LIN CUS_BSL DAT_ DAT_ COD_ CUS_ DIS_...
Page 214 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description COD_LIN_PW Status of Linear Region Password / Protection Not Protected, Linear Region Password is not installed; Linear region is not protected. Protected, Linear Region Password is installed; Linear region is protected.
Page 215 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description EN_PRG_DAT_LIN NVM Protection of Data in Linear Data Sectors Protected, The data in sectors of the linearly mapped area can not be changed Not Protected, The data in sectors of the linearly mapped area can be changed (erased or written) EN_RD_DAT_LIN NVM Read Protection of Data in Linear Data Sectors...
Page 216 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Memory Access Status Register This register reflects the Memory Access Status of all System Memories. Software can only clear this register. SCU_MEM_ACC_STS Offset Reset Value Memory Access Status Register Table 108 ROM_ NVM_ NVM_...
Page 217 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Identity Register The Identity Register identifies the product and versioning. SCU_ID Offset Reset Value Identity Register Table 109 PRODID VERID Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. PRODID Product ID 10000...
Page 218 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Memory Status Register The Memory Status Register can be used in two ways. Upon the completion of the Boot ROM startup following a reset, the register stores the NVM initialization status. Subsequently, the register can be used by the user code to store the status of the NVM program and emergency program operation status.
Page 219 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Field Bits Type Description SASTATUS Service Algorithm Status Success_1, Depending on SECTORINFO, there are two possible outcomes: For SECTORINFO = 00 , NVM initialization is successful and no SA is executed. For SECTORINFO = values other than 00 , SA execution is successful and only one map error is fixed.
Page 220 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Stack Overflow Control Register SCU_STACK_OVF_CTRL Offset Reset Value Stack Overflow Control Register Table 111 STOF Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. STOF_EN Stack Overflow Enable Disable, stack overflow detection disabled.
Page 221 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Stack Overflow Address Register SCU_STACK_OVF_ADDR defines an address region inside the RAM address range which is monitored for stack overflow protection purposes. In case there is an read/write access detected in the specified region an a stack overflow NMI is generated (FSTOFNMI).
Page 222 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Table 112 RESET of SCU_STACK_OVF_ADDR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 0000 0000 RESET_TYPE_4 User Manual Rev. 2.0 2023-08-09...
Page 223 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Stack Overflow Status Register SCU_STACK_OVF_STS Offset Reset Value Stack Overflow Status Register Table 113 STOF _STS rwhxre Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. STOF_STS rwhxre Stack Overflow Status No Error, No stack overflow detected.
Page 224 MOTIX™ TLE985xQX System Control Unit - Digital Modules (SCU-DM) Stack Overflow Status Clear Register SCU_STACK_OVFCLR Offset Reset Value Stack Overflow Status Clear Register Table 114 STOF _ST* Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. STOF_STSC Clear Stack Overflow Status Not Cleared, stack overflow not cleared.
Page 225: System Control Unit - Power Modules (Scu-Pm)
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) System Control Unit - Power Modules (SCU-PM) Features • Clock Watchdog Unit (CWU): supervision of all power modules relevant clocks with NMI signalling. • Interrupt Control Unit (ICU): all system relevant interrupt flags and status flags. •...
Page 226: Clock Watchdog Unit (Cwu)
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) • ICU: – PREWARN_SUP_NMI = generation of Prewarn-Supply NMI – PREWARN_CLK_INT = generation of Prewarn-Clock Watchdog NMI – INT = generation of MISC interrupts Clock Watchdog Unit (CWU) There are two clock watchdogs available. One main purpose of them, is to monitor the derived switched capacitor clocks, which are used for analog module operation.
Page 227: Functional Description Of Clock Watchdog Module
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) CCU (SCU_PM) {1,2,3,...} APCLK2FAC CLK_2MHz QRE L1 {1,2, 3,4} CLK WDT2 APCLK1FAC LP_CLK MI_CLK QRE L2 fsys CLK WDT 3 CLK WDT1 AMCLK_SEL fsys PCLK2 PCLK AMCLK_SEL Figure 37 Block diagram of CGU including Clock Watchdogs 8.3.1.1 Functional Description of Clock Watchdog Module The clock watchdog module consists of a counter.
Page 228 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 11: fail(long window) frequency too low The ouput clkwdt_fail_o is generated out of APCLK1.APCLK1STS or APCLK2.APCLK2STS. It indicates a fail frequency(too low in a long window) of i_clk or tfilt_clk. (clkwdt_fail_o <= APCLK1.APCLK1STS = “11” or APCLK2.APCLK2STS = “11”). clkwdt_fail_o is used for shutdown of analog module and for the PMU reset generation.
Page 229: Clock Generation Unit Register
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.3.2 Clock Generation Unit Register The analog module clock generation unit is fully controllable by the register described in this chapter. Table 115 shows the module base addresses. Table 115 Register Address Space Module Base Address End Address...
Page 230 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description AMCLK2_FREQ 13:8 Current frequency of Analog Module Clock 2 (TFILT_CLK) 0.09375 Mhz * AMCLK2_FREQ Reserved Always read as 0 AMCLK1_FREQ Current frequency of Analog Module Clock System Clock (MI_CLK) 0.75 Mhz * AMCLK1_FREQ Table 117...
Page 231 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) AMCLK2_ AMCLK2_ AMCLK2_LOW_TH AMCLK2_UP_TH LOW_HYS UP_HYS AMCLK1_ AMCLK1_ AMCLK1_LOW_TH AMCLK1_UP_TH LOW_HYS UP_HYS Field Bits Type Description AMCLK2_LOW_HYS 31:30 Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis AMCLK2_LOW_TH 29:24 Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold 0.09375 Mhz * AMCLK2_LOW_TH AMCLK2_UP_HYS...
Page 232: Interrupt Control Unit (Icu)
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description 31:26 Reserved Always read as 0 STCALIB 25:0 System Tick Calibration [25]: Noref [24] Skew [23:0] Reload value to use for 10ms (100 Hz) timing STCALIB[23:0] = HCLK (in Hz) / 100 Hz - 1, e.g. 0x7A11F Table 120 RESET of SCUPM_STCALIB...
Page 233 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) VBAT_SENSE: >=1 ADC1_IRQS_2.PP_CH0_LO_IS ADC1_IRQS_2.PP_CH0_UP_IS 10Bit ADC-Voltage- Monitoring >=1 ADC1_IRQS_2.VS_LO_IS ADC1_IRQS_2.VS_UP_IS >=1 SCUPM_SY S_SUPPLY_IRQ_STS.VS_UV_IS SCUPM_SY S_SUPP LY_IRQ_STS.VS_OV_IS >=1 VDDP: >=1 SCUPM_SYS_SUPPLY_IRQ_STS.VDD5V_UV_IS SCUPM_SYS_SUPPLY_IRQ_STS.VDD5V_OV_IS VDDC: MI-Voltage-Monitoring >=1 SCUPM_SYS_SUPP LY_IRQ_STS.VDD1V5_UV_IS SCUPM_SYS_SUPPLY_IRQ_STS.VDD1V5_OV_IS VDDEXT: >=1 >=1 SCUPM_SY S_SUPP LY_IRQ_STS.VDDEXT_UV_IS SCUPM_SYS_SUPP LY_IRQ_STS.VDDEXT_OV_IS VDDP: >=1...
Page 234: Interrupt Control Unit Status Register
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.4.2 Interrupt Control Unit Status Register All analog modules interrupt functionality is described in this chapter. Table 121 Register Overview Register Short Name Register Long Name Offset Address Reset Value Interrupt Control Unit Status Register, Interrupt Control Unit Status Overview Register SCUPM_SYS_IS...
Page 235 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) System Interrupt Status Register SCUPM_SYS_IS Offset Reset Value System Interrupt Status Register Table 122 SYS_ VREF VREF SYS_ SYS_ HS_F DRV_ CP_F LIN_ SUP* 1V2* 1V2* OT_* OTW* AIL* FAI* AIL* FAI* rwhxr rwhxr...
Page 236 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description HS_FAIL_STS High Side Driver Fail Status Note: This flag is an OR combination of HS1_OT_STS and HS1_OL_STS OK, no status set FAIL, at least one status set DRV_FAIL_STS Gate Driver Fail Status Note:...
Page 237 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description CLKWDT_IS Clock Watchdog Interrupt Status OK, no interrupt status set FAIL, at least one interrupt status set SYS_OT_IS rwhxre System Overtemperature Shutdown (ADC2, Channel 8) interrupt status OK, no interrupt status set FAIL, at least one interrupt status set SYS_OTWARN_IS...
Page 238 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) System Supply Interrupt Status Register SCUPM_SYS_SUPPLY_IRQ_STS Offset Reset Value System Supply Interrupt Status Register Table 123 VDD1 VDD5 VDDE VS_O VDD1 VDD5 VDDE VS_U V5_* V_O* XT_* V_S* V5_* V_U* XT_* V_S* rwhxr rwhxr...
Page 239 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description VDDEXT_UV_STS rwhxr VDDEXT Undervoltage Status (ADC2 channel 3) No Undervoltage, occurred Undervoltage, occurred 18:17 Reserved Always read as 0 VS_UV_STS rwhxr VS Undervoltage Status (ADC2 channel 0) No Undervoltage, occurred Undervoltage, occurred Reserved...
Page 240 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description Reserved Always read as 0 VS_UV_IS rwhxre VS Undervoltage Interrupt Status (ADC2 channel 0) No Undervoltage Interrupt, occurred Undervoltage Interrupt, occurred Table 123 RESET of SCUPM_SYS_SUPPLY_IRQ_STS Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 241: Interrupt Control Unit - Interrupt Clear Register
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.4.2.2 Interrupt Control Unit - Interrupt Clear Register The Analog Module Interrupts can be cleared by their corresponding enable bits which are located in Registers: • SCUPM_SYS_SUPPLY_IRQ_CLR: Clear of Interrupts for Under- and Overvoltage detection for all system relevant supplies.
Page 242 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description VREF1V2_OV_ISC 8 Bit ADC2 Reference Overvoltage Interrupt Status Clear No clear, Clear, VREF1V2_UV_ISC 8 Bit ADC2 Reference Undervoltage Interrupt Status Clear No clear, Clear, 11:10 Reserved Always read as 0 SYS_OT_ISC System Overtemperature Shutdown Interrupt Status Clear No clear,...
Page 243 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) System Supply Interrupt Status Clear Register SCUPM_SYS_SUPPLY_IRQ_CLR Offset Reset Value System Supply Interrupt Status Clear Table 125 Register VDD1 VDD5 VDDE VS_O VDD1 VDD5 VDDE VS_U V5_* V_O* XT_* V_SC V5_* V_U* XT_* V_SC...
Page 244 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description VDDEXT_UV_SC VDDEXT Undervoltage Status clear No Clear , Clear , 18:17 Reserved Always read as 0 VS_UV_SC VS Undervoltage Status clear No Clear , Clear , Reserved Always read as 0 VDD1V5_OV_ISC VDDC Overvoltage Interrupt Status clear...
Page 245 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Table 125 RESET of SCUPM_SYS_SUPPLY_IRQ_CLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000 RESET_TYPE_4 User Manual Rev. 2.0 2023-08-09...
Page 246: Interrupt Control Unit - Interrupt Enable Register
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.4.2.3 Interrupt Control Unit - Interrupt Enable Register The Analog Module Interrupts can be enabled and disabled by there corresponding enable bits which are located in Registers: • SCUPM_SYS_SUPPLY_IRQ_CTRL: Enable of Interrupts for Under- and Overvoltage detection for all system relevant supplies.
Page 247 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Table 126 RESET of SCUPM_SYS_IRQ_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000 RESET_TYPE_4 User Manual Rev. 2.0 2023-08-09...
Page 248 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) System Supply Interrupt Control Register SCUPM_SYS_SUPPLY_IRQ_CTRL Offset Reset Value System Supply Interrupt Control Register Table 127 VDD1 VDD5 VDDE VS_O VDD1 VDD5 VDDE VS_U V5_* V_O* XT_* V_IE V5_* V_U* XT_* V_IE Field Bits...
Page 249: Power Control Unit For Power Modules (Pcu_Pm)
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description VDDEXT_UV_IE VDDEXT Undervoltage Interrupt Enable Disable, Interrupt is disabled Enable, Interrupt is enabled Reserved Always read as 0 VS_UV_IE VS Undervoltage Interrupt Enable Disable, Interrupt is disabled Enable, Interrupt is enabled Table 127 RESET of...
Page 250 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) PD_N & to analog module PD_N & to analog module Analog Peripheral Control Working Principle of PCU Figure 39 Function of AP_SUB_CTRL If the device will power up the analog modules statemachine will startup all analog modules. First of all, the reference voltage will be enabled.
Page 251: Vs-Overvoltage System Shutdown
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.5.1 VS-Overvoltage System Shutdown The PCU provides the possibility of an system shutdown in case of VS Overvoltage. This feature can be used to reduce power dissipation in case of an increased supply voltage VS. This feature can be enabled by bit SYS_VS_OV_SLM_DIS.
Page 252 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) & SYS_OTWARN_STS SYS_OTWARN_STS_gated XSFR SYS_OTWARN_PS_DIS – XSFR Bit Figure 41 Implementation of Power Module Shutdown in case of System Overtemperature Warning As it can be seen, the bit is gating the status flag VS_OTWARN_STS. If this bit is set, 1ms after the indication the system will be set into Sleep Mode.
Page 253: Power Control Unit Register
MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) 8.5.3 Power Control Unit Register The PCU is fully controllable by the below listed SFR Registers. Table 128 Register Overview Register Short Name Register Long Name Offset Address Reset Value Power Control Unit Register SCUPM_PCU_CTRL_ST Power Control Unit Control Status Register 0EE37EF3...
Page 254 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description SYS_OTWARN_PS_DI System Overtemperature Warning Power Switches Shutdown Disable Enable, Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable Disable , Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable 23:18...
Page 255 MOTIX™ TLE985xQX System Control Unit - Power Modules (SCU-PM) Field Bits Type Description CLKWDT_SD_DIS Power Modules Clock Watchdog Shutdown Disable Shutdown Enable, Power Devices will be switched off when Clock Watchdog. Shutdown Disable, Power Devices will not be shutdown when Clock Watchdog occurs Reserved Always read as 0 Table 129...
Page 256: Arm® Cortex®-M0 Core
MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Arm® Cortex®-M0 Core Features The key features of the Arm® Cortex®-M0 implemented are listed below. Processor Core. A low gate count core, with low latency interrupt processing: ® ® • Thumb + Thumb-2 Instruction Set •...
Page 257: Funtional Description
MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Cortex -M0 Processor Nested Vectored Breakpoint Cortex Interrupt and Interrupt processor Power Control Controller watchpoint core (NVIC) unit Serial-Wire Bus matrix Debug Access Port Debugger interface (SW-DP) AHB-Lite i n terface Serial-Wire Debug Interface Figure 42 Arm®...
Page 258: Registers
MOTIX™ TLE985xQX Arm® Cortex®-M0 Core 9.3.1 Registers The processor has the following 32-bit registers: • 13 general-purpose registers, R0-R12 • Stack pointer (SP), R13 alias of banked registers, SP_process and SP_main • Link register (LR), R14 • Program counter (PC), R15 •...
Page 259 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Program Status Register Register PSR is the Program Status Register. Interrupt MaskRegister Register PRIMASK is the Interrupt Mask Register. Control Register Register CONTROL is the Control Register. User Manual Rev. 2.0 2023-08-09...
Page 260: Summary Of Processor Registers
MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Summary of Processor Registers The processor has the following 32-bit registers that control functionality: Table 130 Register Address SpaceAddress Space for Processor Registers Module Base Address End Address Note E000E000 E000EFFF Arm® Cortex®-M0 Core SCS (System Control Space), Systick, NVIC Processor Registers Table 131...
Page 261 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core CPU_SYSTICK_CSR Offset Reset Value SysTick Control and Status Register Table 132 COUN TFLA CLKS TICK ENAB OURC Field Bits Type Description 31:17 Reserved COUNTFLAG Count Flag Returns 1 if timer counted to 0 since the last read of this register. 15:3 Reserved CLKSOURCE...
Page 262 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core RELOAD RELOAD Field Bits Type Description 31:24 Reserved RELOAD 23:0 Reload Value to load into the SysTick Current Value Register when the counter is enabled and when it reaches 0, see Calculating the RELOAD Value. Table 133 RESET of CPU_SYSTICK_RVR...
Page 263 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description 31:24 Reserved CURRENT 23:0 Current Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0. Table 134 RESET of CPU_SYSTICK_CVR...
Page 264 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 135 RESET of CPU_SYSTICK_CALIB Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 X0XXXXXX RESET_TYPE_3 Exact Reset Values: XX00 0000 XXXX XXXX XXXX XXXX XXXX XXXX(B) Interrupt Set-Enable Register CPU_NVIC_ISER Offset Reset Value Interrupt Set-Enable Table 136...
Page 265 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_CP Interrupt Set for Charge Pump DISABLED, no effect on write ENABLE, enables the associated interrupt Reserved Int_MATHDIV 15 Interrupt Set for Math Divider DISABLED, no effect on write ENABLE, enables the associated interrupt Int_WAKEUP Interrupt Set for WAKEUP DISABLED, no effect on write...
Page 266 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_ADC2 Interrupt Set for MU, ADC2 DISABLED, no effect on write ENABLE, enables the associated interrupt Int_GPT2 Interrupt Set for GPT2 DISABLED, no effect on write ENABLE, enables the associated interrupt Int_GPT1 Interrupt Set for GPT1 DISABLED, no effect on write...
Page 267 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_DU Interrupt Clear for Differential Unit DISABLE, on reads the associated interrupt is disabled, no effect on write ENABLE, on reads the associated interrupt is enabled, on writes the associated interrupt is disabled Int_OPA Interrupt Clear for Current Sense Amplifier DISABLE, on reads the associated interrupt is disabled, no effect...
Page 268 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_UART2 Interrupt Clear for UART2 DISABLE, on reads the associated interrupt is disabled, no effect on write ENABLE, on reads the associated interrupt is enabled, on writes the associated interrupt is disabled Int_UART1 Interrupt Clear for UART1 DISABLE, on reads the associated interrupt is disabled, no effect...
Page 269 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_ADC2 Interrupt Clear for MU, ADC2 DISABLE, on reads the associated interrupt is disabled, no effect on write ENABLE, on reads the associated interrupt is enabled, on writes the associated interrupt is disabled Int_GPT2 Interrupt Clear for GPT2 DISABLE, on reads the associated interrupt is disabled, no effect...
Page 270 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_MON Interrupt Set Pending for MON Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, the associated interrupt is pending Int_DU Interrupt Set Pending for Differential Unit Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, the associated interrupt is pending...
Page 271 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_UART1 Interrupt Set Pending for UART1 Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, the associated interrupt is pending Int_SSC2 Interrupt Set Pending for SSC2 Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, the associated interrupt is pending...
Page 272 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 138 RESET of CPU_NVIC_ISPR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 Interrupt Clear-Pending Register CPU_NVIC_ICPR Offset Reset Value Interrupt Clear-Pending Table 139 Int_ Int_ Int_ Int_ Int_ Int_ Int_ PORT...
Page 273 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_HS Interrupt Clear Pending for High-Side Switch Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending Int_BDRV Interrupt Clear Pending for Bridge Driver...
Page 274 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_SSC2 Interrupt Clear Pending for SSC2 Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending Int_SSC1 Interrupt Clear Pending for SSC1 Not Pending, on reads the associated interrupt is not pending,...
Page 275 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description Int_GPT1 Interrupt Clear Pending for GPT1 Not Pending, on reads the associated interrupt is not pending, no effect on writes Pending, on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending Table 139 RESET of CPU_NVIC_ICPR...
Page 276 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Interrupt Priority Register 1 CPU_NVIC_IPR1 Offset Reset Value Interrupt Priority Table 141 PRI_CCU PRI_CCU 6SR3 6SR2 PRI_CCU PRI_CCU 6SR1 6SR0 Field Bits Type Description PRI_CCU6SR3 31:30 Priority for CCU6 SR3 29:24 Reserved PRI_CCU6SR2 23:22 Priority for CCU6 SR2 21:16 Reserved PRI_CCU6SR1 15:14...
Page 277 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core PRI_UAR PRI_UAR PRI_SSC PRI_SSC Field Bits Type Description PRI_UART2 31:30 Priority for UART2 29:24 Reserved PRI_UART1 23:22 Priority for UART1 21:16 Reserved PRI_SSC2 15:14 Priority for SSC2 13:8 Reserved PRI_SSC1 Priority for SSC1 Reserved Table 142 RESET of CPU_NVIC_IPR2 Register Reset Type...
Page 278 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description PRI_MATHDIV 31:30 Priority for Math Divider 29:24 Reserved PRI_WAKEUP 23:22 Priority for WAKEUP 21:16 Reserved PRI_EXINT1 15:14 Priority for External Int 1 13:8 Reserved PRI_EXINT0 Priority for External Int 0 Reserved Table 143 RESET of CPU_NVIC_IPR3...
Page 279 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 144 RESET of CPU_NVIC_IPR4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 Interrupt Priority Register 5 CPU_NVIC_IPR5 Offset Reset Value Interrupt Priority Table 145 PRI_POR PRI_MON PRI_DU PRI_OPA Field Bits Type...
Page 280 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core IMPLEMENTER VARIANT CONSTANT PARTNO REVISION Field Bits Type Description IMPLEMENTER 31:24 Implementer Code Assigned by Arm®. Read as 41 for a processor implemented by Arm®. VARIANT 23:20 Variant Number Implementation defined. CONSTANT 19:16 Constant Defines the architecture of the processor. Read as 0 PARTNO 15:4 Part Number...
Page 281 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description NMIPENDSET 31 NMI Set Pending On writes, makes the NMI exception state pending. On reads, indicates the state of the exception. Note: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit.
Page 282 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Field Bits Type Description ISRPENDING Interrupt Pending Flag Excluding NMI and Faults. Not Pending, interrupt not pending Pending, interrupt is pending 21:18 Reserved VECTPENDIN 17:12 VECTPENDING Indicates the exception number of the highest priority pending enabled exception.
Page 283 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core VECTKEY ENDI SYSR VECT ANNE ESET CLRA CTI* Field Bits Type Description VECTKEY 31:16 Vector Key Register writes must write 05FA to this field, otherwise the write is ignored. On reads, returns Unknown. ENDIANNESS 15 Data Endianness Little Endian, Big Endian,...
Page 284 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core SEVO SLEE SLEE NPEN PDEE PONE Field Bits Type Description 31:5 Reserved SEVONPEND SEVONPEND Send event on pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
Page 285 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Configuration Control Register CPU_CCR Offset Reset Value Configuration Control Register Table 150 STKA UNAL LIGN IGN_ Field Bits Type Description 31:10 Reserved STKALIGN STKALIGN Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment.
Page 286 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core PRI_11 Field Bits Type Description PRI_11 31:30 Priority of System Handler 11, SVCall 29:0 Reserved Table 151 RESET of CPU_SHPR2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 System Handler Priority Register 3 CPU_SHPR3 Offset Reset Value...
Page 287 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 152 RESET of CPU_SHPR3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 System Handler Control and State Register CPU_SHCSR Offset Reset Value System Handler Control and State Register Table 153 SVCA LLPE...
Page 288: Instruction Set Summary
MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Instruction Set Summary This chapter provides the Instruction set. Table 154 shows the instructions and their cycle counts. The cycle counts are based on a system with zero wait states. Within the assembler syntax, depending on the operation, the <op2> field can be replaced with one of the following options: •...
Page 289 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 154 Instruction Set Summary (cont’d) Operation Description Mnemonic Cycles (without wait states) Rotate Rotate right ROR Rd, Rn, Rs Load Word LDR Rt, [Rn, <op2>] Halfword LDRH Rt, [Rn, <op2>] Byte LDRB Rt, [Rn, <op2>] Signed halfword LDRSH Rt, [Rn, <op2>] Signed byte...
Page 290 MOTIX™ TLE985xQX Arm® Cortex®-M0 Core Table 154 Instruction Set Summary (cont’d) Operation Description Mnemonic Cycles (without wait states) Hint Send event Wait for event 1 + W Wait for interrupt 1 + W No operation Barriers Instruction synchronization 1 + B Data memory 1 + B Data synchronization...
Page 291: Address Space Organization
MOTIX™ TLE985xQX Address Space Organization Address Space Organization The TLE985xQX manipulates operands in the following memory spaces: • Up to 96 KB (product variant dependent) of Flash memory in code space • 24 KB Boot ROM memory in code space (used for boot code and IP storage) •...
Page 292 MOTIX™ TLE985xQX Address Space Organization Table 155 Memory Map Start (hex) End (hex) Size (hex) Space Name Usage 0000_0000 0000_5FFF 6000 Code/Data BROM, 24 KB 0000_6000 10FF_FFFF Reserved Reserved 1100_0000 1101_7FFF 18000 Code/Data NVM, Up to 96 KB 1101_8000 17FF_FFFF Reserved Reserved 1800_0000...
Page 293 MOTIX™ TLE985xQX Address Space Organization Table 156 Peripheral Memory Map Bus Structure Modules Start Address End Address Peripherals 0 Reserved 40000000 40003FFF ADC1 40004000 40007FFF CCU6 4000C000 4000FFFF GPT12 40010000 40013FFF Reserved 40014000 40023FFF 40024000 40027FFF Reserved 40028000 40033FFF 40034000 40037FFF Reserved 40038000...
Page 294: Memory Control Unit
MOTIX™ TLE985xQX Memory Control Unit Memory Control Unit 11.1 Features • Provides Memory access to ROM, RAM, NVM, Config Sector through AHB-Lite Interface • MBIST for RAM • MBIST for ROM • NVM Configuration with Special Function Registers through AHB-Lite Interface •...
Page 295 MOTIX™ TLE985xQX Memory Control Unit PBA0 Memory Protection Unit Sx: Bus Slave Mx: Bus Master Bus Matrix MCU_Block_Diagram_overview.vsd Figure 45 Memory Control Unit Block View Functional Features for RAM • 4 KB RAM • Error correction code (ECC) for detection of single bit and double bit errors and dynamic correction of single bit errors •...
Page 296: Nvm Module (Flash Memory)
MOTIX™ TLE985xQX Memory Control Unit 11.3 NVM Module (Flash Memory) The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. Features • In-System Programming via LIN (Flash mode) and SWD • Error Correction Code (ECC) for detection of single Bit and double Bit errors and dynamic correction of single Bit errors on Data Block (Double words, 64 bits).
Page 297: General Definitions
MOTIX™ TLE985xQX Memory Control Unit 11.3.1.1 General Definitions Logical and Physical States Erasing The erased state of a cell is ´1´. Forcing an NVM cell to this state is called erasing. Erasing is possible with a granularity of a page (see below). Writing The written state of a cell is ´0´.
Page 298 MOTIX™ TLE985xQX Memory Control Unit Data Portions Array(n-1)*4 kB sector n-1 Spare page Page 31 Page 30 sector 1 Page 1 sector 0 Page 0 1 page = 16 user data block + 1 mapping information block Map block Data block 0 Data block 1 Data block 14 Data block 15...
Page 299: Functional Description
MOTIX™ TLE985xQX Memory Control Unit Spare Page A spare page is an additional page in a sector used in each programming routine to allow tearing-safe programming. Sector A sector consists of 32 logical and 33 physical page. 11.3.2 Functional Description The main tasks of the NVM module are reading from the memory array, writing to the assembly buffer, enabling (tearing safe) programming of a single page, provide basic in-module functionality for code protection.
Page 300: Memory Cell Array
MOTIX™ TLE985xQX Memory Control Unit Page Analog Sector Page Sector Address Sector Map-RAM Page Sector FSM + SFRs Cell Array Oscillator Assembly Buffer Protection logic Prefetch Unit AHB-Lite NVM AHB-Lite NVM Data interface SFR interface (32 bits) (8 bits) Schematic view of the NVM core module Figure 47 Schematic View of the NVM Core Module 11.3.2.2 Memory Cell Array...
Page 301: Sfr Accesses
MOTIX™ TLE985xQX Memory Control Unit Employing the integrated EEPROM emulation using the map RAM, the minimum granularity of data that can be changed in the NVM is one byte, while all other bytes in the page do not change. Assembly Buffer The assembly buffer is a RAM that can hold the content of one page including the mapblock.
Page 302: Memory Write
MOTIX™ TLE985xQX Memory Control Unit 11.3.2.5 Memory Write Data is not written to the memory array directly, but to the assembly buffer and then copied into the cell array by the write sequence. Memory writes are handled through the BootROM software, which at first copies the existing content of a page to the assembly buffer, allows the user to modify the content of the assembly buffer and afterwards executes the programming of the data to the memory field followed by a verification step.
Page 303: Code And Data Access Through The Ahb-Lite Interface
MOTIX™ TLE985xQX Memory Control Unit block level. Requirement is to provide a single bit ECC and 2 bits EDC per block, that is 1 bit correction over 64 data bits. Since the ECC protects 64bits, when a byte is written to the assembly buffer automatically an NVM internal read of the complete block is triggered, the byte and the ECC are updated and the complete block is written back to the assembly buffer.
Page 304: Bootrom Module
MOTIX™ TLE985xQX Memory Control Unit 11.4 BootROM Module The TLE985xQX BootROM module provides physical implementation of the memory module as well as needed complementary features and interface towards the core. The module provides proper access through a 32-bit AHB-Lite data interface multiplexed on Arm® Cortex®-M0 system bus for code/data access.
Page 305: Ram Module
MOTIX™ TLE985xQX Memory Control Unit 11.5 RAM Module The TLE985xQX RAM module provides physical implementation of the memory module as well as needed complementary features and interface towards the core. The module provides proper access through a 32-bit AHB-Lite data interface multiplexed on Arm® Cortex®-M0 system bus for code/data access.
Page 306: Memory Protection Unit (Mpu)
MOTIX™ TLE985xQX Memory Control Unit 11.6 Memory protection Unit (MPU) The target of the memory protection scheme is to prevent unauthorized read out of critical data and user IPs from the BootROM and NVM as well as to prevent accidental memory data modification. The TLE985xQX protection scheme is divided in 2 parts interacting togetherTLE985xQX The first memory protection scheme is firmware based and involves the blocking of all external access to the device.
Page 307: Bootrom Protection Mode
MOTIX™ TLE985xQX Memory Control Unit Linear and Data Mapped regions. While the BootROM protection mode is enabled, the NVM protection mode may be enabled as well to further prevent code read out. NVM has privilged region protection. Customer BSL region is considered to have the highest privilege, followed by Code region, then Data region.
Page 308: Nvm Protection Modes
MOTIX™ TLE985xQX Memory Control Unit • Data reading instructions executed from the BootROM can target itself, NVM or RAM • Data reading access issued by the debugger can target NVM or RAM In addition, to avoid an indirect leak of information by hacking through the debugger, breakpoints set and step through features shall be disabled on the BootROM.
Page 309 MOTIX™ TLE985xQX Memory Control Unit BootROM Customer BSL region Code Linear Data Linear Data Mapped Debugger Legend Source address space from which the data reading instruction is fetched Target address space from which data is read Figure 50 BootROM Protection Mode enabled If the BootROM and the Customer BSL protection modes are enabled: •...
Page 310 MOTIX™ TLE985xQX Memory Control Unit • Data reading accesses triggered by debugger targeting the NVM Code Linear region Figure 51 shows all the data reading instructions authorized when the BootROM, the Customer BSL region and NVM Code Linear read protections are enabled. BootROM Customer BSL region...
Page 311 MOTIX™ TLE985xQX Memory Control Unit from accepting any program or erase command. This prevents inadvertent destruction of stored data while protection is set. When NVM Data Linear read protection is enabled, the following accesses shall be restricted: • Data reading instructions executed from BootROM, RAM, Data Mapped NVM RAMtargeting the NVM Data Linear region •...
Page 312 MOTIX™ TLE985xQX Memory Control Unit 11.6.2.2.4 BootROMProtection Mode The NVM Data Mapped protection can be controlled via proper dedicated Password or via the NVMPROT_STS register as described in the Chapter 11.6.2.2.5. When its write protection is enabled, any operation capable to change the NVM values stored in this region shall be blocked.
Page 313 MOTIX™ TLE985xQX Memory Control Unit • Data reading instructions executed from Data Mapped NVM can target itself or RAM • Data reading instructions executed from the BootROM can target itself or RAM • Data reading instructions executed from the BootROM can target itself, Code Linear NVM, Data Linear NVM, Data Mapped NVM or RAM •...
Page 314: Firmware Protection Mode
MOTIX™ TLE985xQX Memory Control Unit Temporary Protection The hardware memory protection mechanism is controlled by the values of the NVM_ PROT_STS register bits. When user set a protection via password, the BootROM startup sequence enables proper protection modes by writing the related bit of the NVM_PROT_STS register. Even if user enables write protection on a defined region at startup using the dedicated password, during the application code execution there might be the need to temporarily disable the write protection to store some new code/data.
Page 315 MOTIX™ TLE985xQX Memory Control Unit • In case read protection is enabled on selected protection region (Customer BSL, Code Linear NVM, Data Linear NVM or Data Mapped NVM), all provided feature to download code into the selected region shall be blocked (for example all BSL modes available to download code into the selected regiom).
Page 316: Core Protection Mode
MOTIX™ TLE985xQX Memory Control Unit 11.7 Core Protection Mode Chapter 11.6.2 Chapter 11.6.3 describe the protection against accidental write or malicious read memory access implemented in hardware and firmware. The hardware implements a check of all direct access to the each memory region (even from debugger) granting access only when the target region is not protected.
Page 317: Interrupt System
MOTIX™ TLE985xQX Interrupt System Interrupt System 12.1 Features • 23 interrupt nodes for on-chip peripherals • 8 NMI nodes for critical system events • Maximum flexibility (resp. priority and node grouping) for all interrupt nodes 12.2 Introduction 12.2.1 Overview The TLE985xQX supports 24 interrupt vectors with 4 priority levels. 21 of these interrupt vectors are assigned to the on-chip peripherals: GPT12, SSC1, SSC2, CCU6, High-Side Switch, WAKEUP, Bridge Driver, Charge Pump, Differential Unit, Math Divider, GPIOs, MONs, CSA and A/D Converter are each assigned to one dedicated interrupt vector;...
Page 318: Functional Description
MOTIX™ TLE985xQX Interrupt System Table 157 Interrupt Vector Table (cont’d) Service Request Node ID Description SSC2 SSC2 interrupt (receive, transmit, error) UART1 UART1 interrupt (receive, transmit), Timer2, LIN sync, LIN UART2 UART2 interrupt (receive, transmit), Timer21, External Interrupt (EINT2) EXINT0 External interrupt (EINT0), wake-up EXINT1 External interrupt (EINT1)
Page 319: Interrupt Node 2 - Measurement Unit
MOTIX™ TLE985xQX Interrupt System GPT1_T2 GPT1T2 SCU_GPT12IRC.0 T2IE SCU_GPT12IEN ≥1 GPT1_T3 GPT1T3 INTISR[0] SCU_GPT12IRC.1 T3IE SCU_GPT12IEN GPT1_T4 GPT1T4 SCU_GPT12IRC.2 T4IE SCU_GPT12IEN GPT2_T5 GPT1T5 SCU_GPT12IRC.3 T5IE SCU_GPT12IEN ≥1 GPT2_T6 GPT1T6 INTISR[1] SCU_GPT12IRC.4 T6IE SCU_GPT12IEN GPT2_CR GPT2CR SCU_GPT12IRC.5 CRIE IEN0.31 SCU_GPT12IEN Figure 55 Interrupt Request Sources 0 and 1 (GPT12) 12.3.1.2 Interrupt Node 2 - Measurement Unit User Manual...
Page 320: Interrupt Node 3 - Adc10
MOTIX™ TLE985xQX Interrupt System VREF1V2_UV SCUPM_SYS_IS.VREF1V2_UV_IS SCUPM_SYS_IRQ_CTRL.VREF1V2_UV_IE ≥1 INTISR[2] VREF1V2_OV SCUPM_SYS_IS.VREF1V2_OV_IS SCUPM_SYS_IRQ_CTRL.VREF1V2_OV_IE IEN0.31 Figure 56 Interrupt Request Sources 2 (MU) 12.3.1.3 Interrupt Node 3 - ADC10 User Manual Rev. 2.0 2023-08-09...
Page 321: Interrupt Node 4, 5, 6, 7 - Ccu6
MOTIX™ TLE985xQX Interrupt System ADC1_IRQEN_1.IIR_CH0_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH0_IS Control ADC1_IRQEN_1.VS_IEN ADC1 Interrupt ADC1_IRQS_1.VS_IS Control ADC1_IRQCLR_1.VS_ISC ADC1_IRQEN_1.IIR_CH2_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH2_IS Control ADC1_IRQCLR_1.IIR_CH2_ISC ADC1_IRQEN_1.IIR_CH3_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH3_IS Control ADC1_IRQCLR_1.IIR_CH3_ISC ADC1_IRQEN_1.IIR_CH4_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH4_IS Control ADC1_IRQCLR_1.IIR_CH4_ISC ADC1_IRQEN_1.IIR_CH5_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH5_IS Control ADC1_IRQCLR_1.IIR_CH5_ISC ADC1_IRQEN_1.IIR_CH6_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH6_IS Control...
Page 322: Interrupt Node 8 And 9 - Ssc
MOTIX™ TLE985xQX Interrupt System Interrupt select and enable Registers CCU6_IEN CCU6_INP CCU6 Node 0 CCU6SR0 INTISR[4] SCU_IRCON4.0 CCU6 Node 1 CCU6SR1 INTISR[5] SCU_IRCON4.4 CCU6 Node 2 CCU6SR2 INTISR[6] SCU_IRCON4.16 CCU6 Node 3 CCU6SRC3 INTISR[7] SCU_IRCON4.20 IEN0.31 Figure 58 Interrupt Request Sources 4, 5, 6, 7 (CCU6) 12.3.1.5 Interrupt Node 8 and 9 - SSC User Manual Rev.
Page 323: Interrupt Node 10 - Uart1
MOTIX™ TLE985xQX Interrupt System SSC1 SSC_EIR1 EIR1 SCU_IRCON2.0 EIREN1 SCU_MODIEN1.0 SSC_TIR1 TIR1 INTISR[8] ≥1 SCU_IRCON2.1 TIREN1 SCU_MODIEN1.1 SSC_RIR1 RIR1 SCU_IRCON2.2 RIREN1 SCU_MODIEN1.2 SSC2 SSC_EIR2 EIR2 SCU_IRCON3.0 EIREN2 SCU_MODIEN1.8 SSC_TIR2 TIR2 INTISR[9] ≥1 SCU_IRCON3.1 TIREN2 SCU_MODIEN1.9 SSC_RIR2 RIR2 SCU_IRCON3.2 RIREN2 IEN0.31 SCU_MODIEN1.10 Figure 59 Interrupt Request Sources 8 and 9 (SSC)
Page 324: Interrupt Node 11 - Uart2
MOTIX™ TLE985xQX Interrupt System UART1 Receive UART1_SCON.0 RIEN1 SCU_MODIEN2.0 UART1 Transmit UART1_SCON.1 TIEN1 SCU_MODIEN2.1 Timer 2 Overflow T2_T2_CON.7 TF2EN ≥1 T2_T2_CON1.1 EXF2 T2EX T2_T2_CON.6 EXEN 2 EXF2EN INTISR[10] ≥1 T2_T2_CON.3 T2_T2_CON1.0 EDGESEL T2_T2_MOD.5 SM_ERR M_SM_ERR_IS LIN_IRQS.3 LIN_IRQEN.3 OT_IS LIN_IRQS.4 LIN_IRQEN.4 ≥1 OC_IS LIN_IRQS.5...
Page 325: Interrupt Node 12 And 13 - Interrupt
MOTIX™ TLE985xQX Interrupt System UART2 Receive UART2_SCON.0 RIEN2 SCU_MODIEN2.6 UART2 Transmit UART2_SCON.1 TIEN2 SCU_IRCON0 0 .5 / 0.4 SCU_MODIEN2.7 SCU_EXICON0.4/5 2 out of >=1 EINT2 INTISR[11] 3 Filter ≥1 EXINT 2_EN SCU_MODIEN2.5 Timer 21 Overflow T21_T2_CON.7 TF2EN T21_T2_CON1.1 ≥1 EXF2 T21EX T21_T2_CON.6 IEN 0.31...
Page 326: Interrupt Node 14
MOTIX™ TLE985xQX Interrupt System 12.3.1.9 Interrupt Node 14 SCU_WAKECON.WAKEUPEN WAKEUP SCU_IRCON5.WAKEUP INTISR[14] IEN0.31 Figure 63 Interrupt Request Sources 14(Wakeup) 12.3.1.10 Interrupt Node 15 MATH_EVIER.DIVEOCIEN Divider end of MATH_EVFR.DIVEOC conversion INTISR[15] >=1 MATH_EVIER.DIVERRIEN Divider error MATH_EVFR.DIVERR IEN0.31 Figure 64 Interrupt Request Sources 15 (Divider Unit) 12.3.1.11 Interrupt Node 17 and 18 - Bridge Driver / Charge Pump User Manual Rev.
Page 327: Interrupt Node 19 - Hs
MOTIX™ TLE985xQX Interrupt System DRV_IRQS.LS1_OC_IS LS1_OC DRV_IRQEN.LS1_OC_IEN HS1_OC DRV_IRQS.HS1_OC_IS DRV_IRQEN.HS1_OC_IEN LS2_OC DRV_IRQS.LS2_OC_IS DRV_IRQEN.LS2_OC_IEN HS2_OC DRV_IRQS.HS2_OC_IS DRV_IRQEN.HS2_OC_IEN LS1_DS DRV_IRQS.LS1_DS_IS ≥1 INTISR[18] DRV_IRQEN.LS1_DS_IEN HS1_DS DRV_IRQS.HS1_DS_IS DRV_IRQEN.HS1_DS_IEN LS2_DS DRV_IRQS.LS2_DS_IS DRV_IRQEN.LS2_DS_IEN HS2_DS DRV_IRQS.HS1_DS_IS DRV_IRQEN.HS2_DS_IEN SEQ_ERR DRV_IRQS.SEQ_ERR_IS DRV_IRQEN.SEQ_ERR_IEN IEN0.31 DRV_CP_IRQS.VSD_UPTH_IS VSD_UPTH DRV_CP_IRQEN.VSD_UPTH_IEN VSD_LOTH DRV_CP_IRQS.VSD_LOTH_IS DRV_CP_IRQEN.VSD_LOTH_IEN VCP_UPTH DRV_CP_IRQS.VCP_UPTH_IS DRV_CP_IRQEN.VCP_UPTH_IEN...
Page 328: Interrupt Node 21 - Dpp1 Differential Unit
MOTIX™ TLE985xQX Interrupt System CSA_LOTH ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQEN_2.PP_CHx_LO_IEN INTISR[20] ≥1 CSA_UPTH ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQEN_2.PP_CHx_UP_IEN IEN0.31 Which ADC 1 Post processing channel is linked to interupt node is depending on Post processing assignment in ADC 1 Figure 67 Interrupt Request Sources 20 (Current Sense Amplifier) 12.3.1.14 Interrupt Node 21 - DPP1 Differential Unit ADC1_IRQEN_1.DU1UP_IEN ADC1 Interrupt...
Page 329: Interrupt Node 23 - Port2.X
MOTIX™ TLE985xQX Interrupt System SCU_IRCON1 0.1 / 0.0 2 out >=1 of 3 MON1 MON1IE Filter SCU_MONIEN.0 SCU_EXICON1.1/0 SCU_IRCON1 0.3 / 0.2 2 out >=1 MON2 of 3 MON2IE Filter SCU_MONIEN.1 SCU_EXICON1.3/2 SCU_IRCON1 0.5 / 0.4 2 out >=1 MON3 of 3 MON3IE Filter...
Page 330 MOTIX™ TLE985xQX Interrupt System ADC1_IRQEN_2.PP_CHx_UP_IEN P20_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN P20_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P21_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN P21_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P22_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN ≥1 INTISR[23] P22_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P23_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN P23_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P27_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN...
Page 331: Non-Maskable Interrupt Request Source (Nmi)
MOTIX™ TLE985xQX Interrupt System ADC1_IRQEN_2.PP_CHx_UP_IEN P20_UP_STS / ADC1_IRQS_2.PP_CHx_UP_IS P28_UP_STS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN ADC1_IRQEN_2.PP_CHx_LO_IEN P20_LO_STS / ADC1_IRQS_2.PP_CHx_LO_IS P28_LO_STS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P21_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN P21_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P22_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN P22_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC ADC1_IRQEN_2.PP_CHx_UP_IEN P23_UP_STS ADC1_IRQS_2.PP_CHx_UP_IS ADC1_IRQCLR_2.PP_CHx_UP_ISC ADC1_IRQEN_2.PP_CHx_LO_IEN ≥1 INTISR[23] P23_LO_STS ADC1_IRQS_2.PP_CHx_LO_IS ADC1_IRQCLR_2.PP_CHx_LO_ISC...
Page 332: Interrupt Flags Overview
MOTIX™ TLE985xQX Interrupt System Watchdog Timer FNMIWDT Overflow SCU_NMISR.0 NMIWDT SCU_NMICON.0 System FNMIOT Overtemperature SCU_NMISR.3 NMIOCDS SCU_NMICON.3 MI_CLK/TFILT_CLK Watchdog FNMIOWD >=1 Oscillator SCU_NMISR.4 NMIOWD Watchdog SCU_NMICON.4 NVM Map Error FNMIMAP Maskable Interrupt >=1 SCU_NMISR.5 NMIMAP SCU_NMICON.5 Uncorrectable RDBE ECC Error SCU_EDCSTAT.0 SCU_EDCCON.0 FNMIECC...
Page 333 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive None Maskable Interrupts Watchdog NMI - FNMIWDT Watchdog Timer NMI edge set until SCU_WDTCON.WDTPR SCU_WDTCON.WDTEN cleared by software OT NMI - FNMIOT SYS_OTWARN edge...
Page 334 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive PREWARN_SUP edge set until SCUPM_SYS_SUPPLY_IR SCUPM_SYS_SUPPLY_IR VDD1V5_UV cleared by Q_STS.VDD1V5_UV_IS Q_CTRL.VDD1V5_UV_IE software PREWARN_SUP edge set until SCUPM_SYS_SUPPLY_IR SCUPM_SYS_SUPPLY_IR VDDEXT_UV cleared by...
Page 335 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive VDDEXT_UNDER level set until PMU_VDDEXT_CTRL.VDD PMU_VDDEXT_CTRL.VDD VOLT cleared by EXT_UV_IS EXT_FAIL_EN software Stack NMI - FNMISTOF Stack Overflow edge set until SCU_STACK_OVF_STS.S...
Page 336 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive ADC10-CH4 edge set until ADC1_Interrupt_Control: ADC1_IRQEN_1.IIR_CH4_ cleared by ADC1_IRQS_1.IIR_CH4_IS software ADC10-CH5 edge set until ADC1_Interrupt_Control: ADC1_IRQEN_1.IIR_CH5_ cleared by ADC1_IRQS_1.IIR_CH5_IS software ADC10-CH6...
Page 337 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive CCU2 level 2 per_clk CCU6 Node 2: CCU6_IEN/CCU6_INP cycles SCU_IRCON4.CCU6SR2 CCU3 level 2 per_clk CCU6 Node 3: CCU6_IEN/CCU6_INP cycles SCU_IRCON4.CCU6SR3...
Page 338 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive LIN OT edge set until LIN: LIN_IRQS.OT_IS LIN_IRQEN.OT_IEN cleared by SCUPM_SYS_IS.LIN_FAIL software LIN OC level set until LIN: LIN_IRQS.OC_IS LIN_IRQEN.OC_IEN cleared by...
Page 339 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive INTISR<15> → Math Divider DIVERR 15_0 Math Div: MATH_EVIER.DIVERRIEN MATH_EVFR.DIVERR DIVEOC 15_1 Math Div: MATH_EVIER.DIVEOCIEN MATH_EVFR.DIVEOC INTISR<17> → Charge Pump VSD_UPTH 17_0 edge...
Page 340 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive LS1_DS 18_5 edge set until BDRV_IRQS.LS1_DS_IS BDRV_IRQEN.LS1_DS_IE cleared by software HS2_DS 18_6 edge set until BDRV_IRQS.HS2_DS_IS BDRV_IRQEN.HS2_DS_IE cleared by software LS2_DS...
Page 341 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive WAKEUP 22_1 edge set until SCU_IRCON1.MON2R/F SCU_MONIEN.MON2IE cleared by software WAKEUP 22_2 edge set until SCU_IRCON1.MON3R/F SCU_MONIEN.MON3IE cleared by software WAKEUP...
Page 342 MOTIX™ TLE985xQX Interrupt System Table 159 All Interrupt Flags and Enable (cont’d) Service Request Node ID Level/Edge Duration SFR Flag Interrupt Enable Sensitive P21_LOTH 23_3 edge set until ADC1_IRQS_2.PP_CHx_L ADC1_IRQEN_2.PP_CHx_ cleared by O_IS LO_IEN software P22_UPTH 23_4 edge set until ADC1_IRQS_2.PP_CHx_U ADC1_IRQEN_2.PP_CHx_ cleared by...
Page 343: Interrupt Structure
MOTIX™ TLE985xQX Interrupt System 12.4 Interrupt Structure An interrupt event source may be generated from the on-chip peripherals or from external. Detection of interrupt events is controlled by the respective on-chip peripherals. Interrupt status flags are available for determining which interrupt event has occurred, especially useful for an interrupt node which is shared by several event sources.
Page 344: Interrupt Source And Vector
MOTIX™ TLE985xQX Interrupt System 12.5 Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt node can be individually enabled or disabled via an enable bit.
Page 345 MOTIX™ TLE985xQX Interrupt System Table 160 Interrupt Vector Address (cont’d) Interrupt Node Assignment for TLE985xQX Enable Bit INTISR[11] UART2 Receive RIEN MODIEN2.0 UART2 Transmit TIEN MODIEN2.1 Timer 21 Overflow TF2EN/ T21T2CON1.1 T21EX EXF2EN T21T2CON1.0 INTISR[12] EINT0 MODIEN3 INTISR[13] EINT1 MODIEN4 INTISR[14] Wake WAKECON...
Page 346 MOTIX™ TLE985xQX Interrupt System Table 160 Interrupt Vector Address (cont’d) Interrupt Node Assignment for TLE985xQX Enable Bit INTISR[23] Port2.1 P2_1_UP_IEN / ADC1_IRQEN_2 P2_1_LO_IEN Port2.2 P2_2_UP_IEN / ADC1_IRQEN_2 P2_2_LO_IEN Port2.3 P2_3_UP_IEN / ADC1_IRQEN_2 P2_3_LO_IEN Port2.7 P2_7_UP_IEN / ADC1_IRQEN_2 P2_7_LO_IEN User Manual Rev.
Page 347: Interrupt Priority
MOTIX™ TLE985xQX Interrupt System 12.6 Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request.
Page 348: Interrupt Handling
MOTIX™ TLE985xQX Interrupt System Table 162 Register Short Register Long Name Offset Address Reset Value name CPU_NVIC_IPR0 Interrupt Priority Register 0 0000 0000 CPU_NVIC_IPR1 Interrupt Priority Register 1 0000 0000 CPU_NVIC_IPR2 Interrupt Priority Register 2 0000 0000 CPU_NVIC_IPR3 Interrupt Priority Register 3 0000 0000 CPU_NVIC_IPR4 Interrupt Priority Register 4...
Page 349: Interrupt Registers
MOTIX™ TLE985xQX Interrupt System 12.8 Interrupt Registers Interrupt registers are used for interrupt node enable, external interrupt control, interrupt flags and interrupt priority setting. Table 164 Register Address Space Module Base Address End Address Note 50005000 50005FFF Table 165 Register Overview Register Short Name Register Long Name Offset Address...
Page 350: Interrupt Node Enable Registers
MOTIX™ TLE985xQX Interrupt System 12.8.1 Interrupt Node Enable Registers Register IEN0 contains the global interrupt masking bit (EA), which can be cleared to block all pending interrupt requests at once. The NMI interrupt vector is shared by a number of sources, each of which can be enabled or disabled individually via register NMICON.
Page 351 MOTIX™ TLE985xQX Interrupt System NMI Control Register SCU_NMICON Offset Reset Value NMI Control Register Table 167 NMIS NMIS NMIE NMIM NMIO NMIO NMIW Field Bits Type Description 31:9 Reserved Returns 0 if read; should be written with 0. NMISTOF Stack Overflow NMI Enable disable, Stack overflow NMI is disabled.
Page 352: External Interrupt Control Registers
MOTIX™ TLE985xQX Interrupt System 12.8.2 External Interrupt Control Registers The external interrupts, EXT_INT[1:0], are driven into the XC8_EPOWER from the ports. External interrupts can be positive, negative or double edge triggered. Register EXICON0 specifies the active edge for the external interrupt.
Page 353 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description EXINT0 External Interrupt 0 Trigger Select Disable, Interrupt disabled. Rising Edge, Interrupt on rising edge. Falling Edge, Interrupt on falling edge. Both Edges, Interrupt on both rising and falling edge. Table 168 RESET of SCU_EXICON0 Register Reset Type...
Page 354 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description MON2 MON2 Input Trigger Select Disable, external interrupt MON is disabled. Rising Edge, Interrupt on rising edge. Falling Edge, Interrupt on falling edge. Both Edges, Interrupt on both rising and falling edge. MON1 MON1 Input Trigger Select Disable, external interrupt MON is disabled.
Page 355: Interrupt Flag Registers
MOTIX™ TLE985xQX Interrupt System 12.8.3 Interrupt Flag Registers The interrupt flags for the different interrupt sources are located in several special function registers. This section describes the interrupt flags located in system registers or external interrupts belonging to system. Other interrupt flags located in respective module registers are described in the specific module chapter. For a complete listing of the interrupt flags and their assignment to SFRs, refer to Table 159.
Page 356 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description EXINT1R Interrupt Flag for External Interrupt 1x on rising edge This bit is set by hardware and can only be cleared by software. No Int, Interrupt on rising edge event has not occurred.
Page 357 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description EXINT2RC Interrupt Flag for External Interrupt 2x on rising edge No Clear, Interrupt event is not cleared. Clear, Interrupt event is cleared EXINT1FC Interrupt Flag for External Interrupt 1x on falling edge No Clear, Interrupt event is not cleared.
Page 358 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description MON4F Interrupt Flag for MON4x on falling edge This bit is set by hardware and can only be cleared by software. No Int, Interrupt on falling edge event has not occurred. Int, Interrupt on falling edge event has occurred. MON4R Interrupt Flag for MON4x on rising edge This bit is set by hardware and can only be cleared by...
Page 359 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description MON1R Interrupt Flag for MON1x on rising edge This bit is set by hardware and can only be cleared by software. No Int, Interrupt on rising edge event has not occurred. Int, Interrupt on rising edge event has occurred. Table 173 RESET of SCU_IRCON1...
Page 360 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description MON2FC Interrupt Flag for MON2x on falling edge No Clear, Interrupt event is not cleared. Clear, Interrupt event is cleared MON2RC Interrupt Flag for MON2x on rising edge No Clear, Interrupt event is not cleared. Clear, Interrupt event is cleared MON1FC Interrupt Flag for MON1x on falling edge...
Page 361 MOTIX™ TLE985xQX Interrupt System Interrupt Request Register 2 SCU_IRCON2 Offset Reset Value Interrupt Request Register 2 Table 175 RIR1 TIR1 EIR1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. RIR1 Receive Interrupt Flag for SSC1 This bit is set by hardware and can only be cleared by...
Page 362 MOTIX™ TLE985xQX Interrupt System Interrupt Request 2 Clear Register SCU_IRCON2CLR Offset Reset Value Interrupt Request 2 Clear Register Table 176 RIR1 TIR1 EIR1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. RIR1C Receive Interrupt Flag for SSC1 No Clear, Interrupt event is not cleared.
Page 363 MOTIX™ TLE985xQX Interrupt System Interrupt Request Register 3 SCU_IRCON3 Offset Reset Value Interrupt Request Register 3 Table 177 RIR2 TIR2 EIR2 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. RIR2 Receive Interrupt Flag for SSC2 This bit is set by hardware and can only be cleared by...
Page 364 MOTIX™ TLE985xQX Interrupt System Interrupt Request 3 Clear Register SCU_IRCON3CLR Offset Reset Value Interrupt Request 3 Clear Register Table 178 RIR2 TIR2 EIR2 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. RIR2C Receive Interrupt Flag for SSC2 No Clear, Interrupt event is not cleared.
Page 365 MOTIX™ TLE985xQX Interrupt System Interrupt Request Register 4 SCU_IRCON4 Offset Reset Value Interrupt Request Register 4 Table 179 CCU6 CCU6 CCU6 CCU6 Field Bits Type Description 31:21 Reserved Returns 0 if read; should be written with 0. CCU6SR3 Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software.
Page 366 MOTIX™ TLE985xQX Interrupt System Table 179 RESET of SCU_IRCON4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 367 MOTIX™ TLE985xQX Interrupt System Interrupt Request 4 Clear Register SCU_IRCON4CLR Offset Reset Value Interrupt Request 4 Clear Register Table 180 CCU6 CCU6 SR3C SR2C CCU6 CCU6 SR1C SR0C Field Bits Type Description 31:21 Reserved Returns 0 if read; should be written with 0. CCU6SR3C Interrupt Flag 1 for CCU6 No Clear, Interrupt event is not cleared...
Page 368 MOTIX™ TLE985xQX Interrupt System Interrupt Request Register 5 SCU_IRCON5 Offset Reset Value Interrupt Request Register 5 Table 181 WAKE Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. WAKEUP Interrupt Flag for Wake-Up This bit is set by hardware and can only be cleared by software.
Page 369 MOTIX™ TLE985xQX Interrupt System Interrupt Request 5 Clear Register SCU_IRCON5CLR Offset Reset Value Interrupt Request 5 Clear Register Table 182 WAKE Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. WAKEUPC Clear Flag for Wake-Up Interrupt No Clear, Interrupt event is not cleared Clear, Interrupt event is cleared Table 182...
Page 370 MOTIX™ TLE985xQX Interrupt System Timer and Counter Control/Status Register SCU_GPT12IRC Offset Reset Value Timer and Counter Control/Status Register Table 183 GPT1 GPT2 GPT2 GPT1 GPT1 GPT1 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 371 MOTIX™ TLE985xQX Interrupt System Table 183 RESET of SCU_GPT12IRC Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 372 MOTIX™ TLE985xQX Interrupt System Timer and Counter Control/Status Register SCU_GPT12ICLR Offset Reset Value Timer and Counter Control/Status Clear Table 184 Register GPT1 GPT2 GPT2 GPT1 GPT1 GPT1 2CRC Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read;...
Page 373 MOTIX™ TLE985xQX Interrupt System Table 184 RESET of SCU_GPT12ICLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 374 MOTIX™ TLE985xQX Interrupt System UART1 Control/Status Register Refer to Register UART_SCON Chapter SCU_SCON1 Offset Reset Value UART1 Control/Status Register Table 185 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission.
Page 375 MOTIX™ TLE985xQX Interrupt System UART2 Control/Status Register Refer to Register UART_SCON Chapter SCU_SCON2 Offset Reset Value UART2 Control/Status Register Table 186 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Reserved Returns 0 if read; should be written with 0. Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission.
Page 376 MOTIX™ TLE985xQX Interrupt System NMI Status Register Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. These include all the flags of NMISR register: FNMIWDT, FNMIOT, FNMIOWD, FNMIMAP, and indirectly, FNMIECC and FNMISUP. In the case of NMIs with shared source i.e.
Page 377 MOTIX™ TLE985xQX Interrupt System Field Bits Type Description FNMIOWD Oscillator Watchdog NMI Flag This bit is set by hardware and can only be cleared by software. no Int, No oscillator watchdog NMI has occurred. Int, Oscillator watchdog event has occurred. FNMIOT Overtemperature NMI Flag This bit is set by hardware and can only be cleared by...
Page 378 MOTIX™ TLE985xQX Interrupt System NMI Status Register Each NMI event and status flag is retained across these resets: 1) WDT reset, 2) soft reset. These include all the flags of NMISR register: FNMIWDT, FNMIOT, FNMIOWD, FNMIMAP, and indirectly, FNMIECC and FNMISUP. In the case of NMIs with shared source i.e.
Page 379: Interrupt Priority Registers
MOTIX™ TLE985xQX Interrupt System Field Bits Type Description FNMIWDTC Watchdog Timer NMI Flag As this is a shared NMI source, this flag should be cleared after checking and clearing the corresponding event flags. Not Cleared, Interrupt event is not cleared. Cleared, Interrupt event is cleared Table 188 RESET of...
Page 380: Math Divider Module
MOTIX™ TLE985xQX Math Divider Module Math Divider Module 13.1 Features The MATH Coprocessor includes the following features: • Divide function with operand pre-processing and result post-processing • AHB-Interface supports Byte/half word/ word Register access • Supports fast execution kernel clock faster than interface clock 13.2 Introduction The MATH Coprocessor (MATH) module supports the CPU in math-intensive computations with a Divider Unit...
Page 381: Divider Unit (Div)
MOTIX™ TLE985xQX Math Divider Module 13.4 Divider Unit (DIV) 13.4.1 Features The DIV supports the following features: • Signed/unsigned 32-bit division operation in 35 kernel clock cycles • Three division modes: – 32-bit divide by 32-bit – 32-bit divide by 16-bit –...
Page 382: Start Mode Selection
MOTIX™ TLE985xQX Math Divider Module Kernel Clock DIVCON.ST DIVST.BSY EVFR.DIVEOC QUOT Figure 75 Timing Diagram for a Division Operation Note: Reading the QUOT and RMD registers while BSY=1 will cause the DIV to insert wait states onto the bus until the active calculation is completed (BSY=0). This ensures that any read access on the result registers QUOT or RMD returns a valid result.
Page 383 MOTIX™ TLE985xQX Math Divider Module The division operation will still proceed as normal and complete in 35 kernel clock cycles. The error flag becomes set at the same clock cycle as DIVEOC. Divide by Zero Error A divide by zero error occurs when a division operation is started with the divisor value in DVS register equal to 0.
Page 384: Operand/Result Pre-/Post-Processing
MOTIX™ TLE985xQX Math Divider Module Table 189 QUOT/RMD Result Register content in divide by zero or overflow condition (cont’d) Operating Mode DVD positive DVD negative DVD positive DVD negative QUOT (Hex) RMD (Hex) 32/16 bit signed 7FFF’FFFF 8000’0000 0000’0000 32/16 bit unsigned FFFF’FFFF n.a.
Page 385 MOTIX™ TLE985xQX Math Divider Module The number of shifts is determined by the respective 5-bit shift count bit fields in DIVCON register. Additionally for the quotient, the shift direction is defined by the bit DIVCON.QSDIR. All shifts are arithmetic shifts. This means if shift left, zeros will be inserted at LSB, while if shift right, zeros (in unsigned mode) or the signed bit (in signed mode) will be inserted at MSB.
Page 386: Global Functions
MOTIX™ TLE985xQX Math Divider Module 13.5 Global Functions 13.5.1 Result Chaining The MATH Coprocessor supports result chaining between the result and the oparand registers of the DIV Unit. For the DIV, this means that each of the operand registers, DVD and DVS, can be updated with the value from any one of the result registers (QUOT and RMD).
Page 387: Service Request Generation
MOTIX™ TLE985xQX Math Divider Module 13.6 Service Request Generation If enabled by the respective interrupt enable bits in EVIER register, the DIV error and end of calculation events will trigger the interrupt service request to NVIC. The event is indicated by the event flag in EVFR register. The event flag can be cleared only by writing a 1 to the event flag clear bit in EVFCR register.
Page 388 MOTIX™ TLE985xQX Math Divider Module The MATH Coprocessor requires two input clock signals, one for the kernel clock and one for the interface clock. The GLBCON.MATH_EN will globaly enable the DIV_UNIT. In case the Math module is not enable (GLBCON.MATH_EN = 0) the kernel clock will be gated off. The interface clock is untouched by this setting. User Manual Rev.
Page 389: Register Description
MOTIX™ TLE985xQX Math Divider Module 13.10 Register Description Table 193 Register Address Space Module Base Address End Address Note MATH 4801 3000 4801 3FFF Math Table 194 Register Overview Register Short Name Register Long Name Offset Address Reset Value Math Module Registers, Global Registers MATH_GLBCON Global Control Register...
Page 390 MOTIX™ TLE985xQX Math Divider Module Global Control Register MATH_GLBCON Offset Reset Value Global Control Register Table 195 MATH SUSCFG DVSRC DVDRC Field Bits Type Description MATH_EN Enable Math Module Note: This bit is RESET_TYPE_3 Enable, Math module is enabled Disable, Math module is disabled 30:18 Reserved Returns 0 if read;...
Page 391 MOTIX™ TLE985xQX Math Divider Module Field Bits Type Description DVSRC Divisor Register Result Chaining The DVS register in DIV will be updated with the selected result register value when the result chaining trigger event occurs. Note: This field is RESET_TYPE_3 disabled, No result chaining is selected QUOT, QUOT register is the selected source RMD, RMD register is the selected source...
Page 392 MOTIX™ TLE985xQX Math Divider Module Module Identification Register MATH_MATH_ID Offset Reset Value Module Identification Register Table 196 MOD_NUMBER MOD_TYPE MOD_REV Field Bits Type Description MOD_NUMBER 31:16 Module Number Value This bit field defines the module identification number. MOD_TYPE 15:8 Module Type This bit field is C0 .
Page 393 MOTIX™ TLE985xQX Math Divider Module Event Interupt EnableRegister MATH_EVIER Offset Reset Value Event Interupt Enable Register Table 197 DIVE DIVE RRI* OCI* Field Bits Type Description 31:2 Reserved Returns 0 if read; should be written with 0. DIVERRIEN Divider Error Interrupt Enable Disable, Divider error interrupt generation is disabled Enable, Divider error interrupt generation is enabled...
Page 394 MOTIX™ TLE985xQX Math Divider Module Event Flag Register MATH_EVFR Offset Reset Value Event Flag Register Table 198 DIVE DIVE Field Bits Type Description 31:2 Reserved Returns 0 if read; should be written with 0. DIVERR Divider Error Event Flag no Error, Divider error event has not been detected Error, Divider error event has been detected DIVEOC Divider End of Calculation Event Flag...
Page 395 MOTIX™ TLE985xQX Math Divider Module Event Flag Set Register MATH_EVSFR Offset Reset Value Event Flag Set Register Table 199 DIVE DIVE Field Bits Type Description 31:2 Reserved Returns 0 if read; should be written with 0. DIVERRS Divider Error Event Flag Set no effect, No effect.
Page 396 MOTIX™ TLE985xQX Math Divider Module Event Flag Clear Register MATH_EVFCR Offset Reset Value Event Flag Clear Register Table 200 DIVE DIVE Field Bits Type Description 31:2 Reserved Returns 0 if read; should be written with 0. DIVERRC Divider Error Event Flag Clear no effect, No effect.
Page 397 MOTIX™ TLE985xQX Math Divider Module Dividend Register MATH_DVD Offset Reset Value Dividend Register Table 201 Field Bits Type Description 31:0 Dividend Value Table 201 Reset of MATH_DVD Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 User Manual Rev.
Page 398 MOTIX™ TLE985xQX Math Divider Module Divisor Register MATH_DVS Offset Reset Value Divisor Register Table 202 Field Bits Type Description 31:0 Divisor Value Table 202 Reset of MATH_DVS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 User Manual Rev.
Page 399 MOTIX™ TLE985xQX Math Divider Module Quotient Register MATH_QUOT Offset Reset Value Quotient Register Table 203 Field Bits Type Description 31:0 Quotient Value Table 203 Reset of MATH_QUOT Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 User Manual Rev.
Page 400 MOTIX™ TLE985xQX Math Divider Module Remainder Register MATH_RMD Offset Reset Value Remainder Register Table 204 Field Bits Type Description 31:0 Remainder Value Table 204 Reset of MATH_RMD Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 User Manual Rev.
Page 401 MOTIX™ TLE985xQX Math Divider Module Divider Status Register MATH_DIVST Offset Reset Value Divider Status Register Table 205 Field Bits Type Description 31:1 Reserved Returns 0 if read; should be written with 0. Busy Indication finish, Divider is not running any division operation. busy, Divider is still running a division operation.
Page 402 MOTIX™ TLE985xQX Math Divider Module Divider Control Register MATH_DIVCON Offset Reset Value Divider Control Register Table 206 DVSSRC DVDSLC QSDI USIG STMO QSCNT DIVMODE Field Bits Type Description 31:29 Reserved Returns 0 if read; should be written with 0. DVSSRC 28:24 Divisor Shift Right Count If DVSSRC is not equal to 0, it indicates the number of bits...
Page 403 MOTIX™ TLE985xQX Math Divider Module Field Bits Type Description USIGN Unsigned Division Enable signed, Signed division is selected unsigned, Unsigned division is selected STMODE Start Mode Selects the start mode for the division operation: Auto, Calculation is automatically started with a write to DVS register Manual, Calculation is started by setting the ST bit to 1...
Page 404: Watchdog Timer (Wdt1)
MOTIX™ TLE985xQX Watchdog Timer (WDT1) Watchdog Timer (WDT1) 14.1 Features There are two watchdog timers in the system. The Watchdog Timer (WDT) within the microcontroller and the Watchdog Timer (WDT1), which is described in this section. In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to recover from software or hardware failures.
Page 405: Introduction
MOTIX™ TLE985xQX Watchdog Timer (WDT1) 14.2 Introduction The behavior of the Watchdog Timer in Active Mode is depicted in Figure Power-up Reset RESET always Timeout Timeout RESET Trigger SOW Maximum number of count_SOW Timeout RESET Long Open Window Trigger in closed window Trigger &...
Page 406: Normal Operation
MOTIX™ TLE985xQX Watchdog Timer (WDT1) 14.3.2 Normal Operation The software has to trigger the watchdog by writing to the WDT1_TRIG register. By triggering the watchdog also the length of the next watchdog period is selected inherently. The next period starts immediately with the trigger.
Page 407 MOTIX™ TLE985xQX Watchdog Timer (WDT1) 50% of Watchdog Period 50% of Watchdog Period Nominal Watchdog Period closed window open window Minimum Watchdog Period closed window open window Maximum Watchdog Period closed window open window Safe Trigger Area closed window open window (Effective Open Window) OWmin OWmax...
Page 408: Watchdog Register Overview
MOTIX™ TLE985xQX Watchdog Timer (WDT1) Example: WDT_TRIG.SOWCONF = 10 „two successive Short Open Windows allowed“ Watchdog operation: Short Open Short Open Short Open closed window open window closed window closed window open window closed window window window window Trigger in normal open window will reset SOW counter Software tasks:...
Page 409 MOTIX™ TLE985xQX Watchdog Timer (WDT1) 14.3.2.1.1 Watchdog Register WDT1 Watchdog Control SCUPM_WDT1_TRIG Offset Reset Value WDT1 Watchdog Control Table 209 SOWCONF WDP_SEL Field Bits Type Description 31:8 Reserved Always read as 0 SOWCONF Short Open Window Configuration DIS, Short Open Windows disabled SOW1, one successive Short Open Window allowed SOW2, two successive Short Open Windows allowed SOW3, three successive Short Open Windows allowed...
Page 410: Gpio Ports And Peripheral I/O
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O GPIO Ports and Peripheral I/O This chapter describes the GPIO Ports of the TLE985xQX. It contains the following sections: • Introduction to the GPIO Ports (see Section 15.2) • GPIO Port functional descriptions (see Section 15.3) This section also describes the mapping of the alternate pin functions...
Page 411: Introduction
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.2 Introduction 15.2.1 Port 0 and Port 1 Figure 83 shows the block diagram of an TLE985xQX bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output.
Page 412: Port 2
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O PUDSEL Pull - up / Pull-down Select Register Pull - up / Pull-down Control Logic PUDEN Pull - up / Pull-down Enable Register TCCR Temperature Compensation Control Register Px_POCONy Port Output Driver Control Registers Open Drain Control Register Direction Register...
Page 413: Functional Description
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O PUDSEL Pull - up / Pull-down Select Register Pull - up / Pull-down Control Logic PUDEN Pull - up / Pull-down Enable Register Pull Device Input Driver Data Data Register Schmitt Trigger AltDataIn AnalogIn Port_Input _Diagram.vsd Figure 84...
Page 414: Data Registers - Pxdata
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Control Registers Data Registers Px_DIR Px_DATA Px_OD Px_PUDSEL Px_PUDEN Px_ALTSEL0 Px_ALTSEL1 Portx_Regs Figure 85 Port Registers Note: Not all the registers are implemented for each port. 15.3.1.1 Data Registers - PxDATA If a port pin is used as general purpose output, output data is written into register Px_DATA (Px_PPy_DAT bits) of port x.
Page 415: Alternate Functions Control - Pxaltsel0/1
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O • open drain with internal pull-up • open drain with external pull-up The pull-up/pull-down device can be fixed or controlled via the registers Px_PUDSEL and Px_PUDEN. Register Px_PUDSEL selects the type of pull-up/pull-down device, while register Px_PUDEN enables or disables it. The pull-up/pull-down device can be selected pinwise.
Page 416: Alternate Functions
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.3.2 Alternate Functions The following chapters describe the Portx.y mapping to their alternate functions. 15.3.2.1 Port 0 Functions Port 0 alternate function mapping according Table 210 Table 210 Port 0 Input/Output Functions Port Pin Input/Output Select Connected Signal(s)
Page 417 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 210 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.2 Input P0_DATA.P2 INP1 T2EUDA GPT12 INP2 CTRAP_0 CCU6 INP3 SSC12_M_MRST_0 SSC1/2 INP4 T21EX_0 Timer 21 INP5 EXINT1_3 Output P0_DATA.P2 ALT1...
Page 418 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 210 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.5 Input P0_DATA.P5 INP1 SSC1_M_MRST SSC1 INP2 EXINT0_0 INP3 T21EX_2 Timer 21 INP4 T5INA GPT12 INP5 CCPOS2_1 CCU6 Output P0_DATA.P5 ALT1...
Page 419: Port 1 Functions
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.3.2.2 Port 1 Functions Port 1 alternate function mapping according Table 211 Table 211 Port 1 Input / Output Functions Port Pin Input/Output Select Connected Signal(s) From/to Module P1.0 Input P1_DATA.P0 INP1 T3INC GPT12 INP2 CC61_0...
Page 420 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 211 Port 1 Input / Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.4 Input P1_DATA.P4 INP1 EXINT2_1 INP2 T21EX_1 Timer 21 INP3 T2INB GPT12 INP4 T5EUDA GPT12 INP5 SSC12_S_MTSR_0 SSC1/2 INP6...
Page 421: Port 2 Functions
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.3.2.3 Port 2 Functions Port 2 alternate function mapping according Table 212 Table 212 Port 2 Input Functions Port Pin Input/Output Select Connected Signal(s) From/to Module P2.0 Input P2_DATA.P0 INP1 EXINT1_1 INP2 CCPOS0_2 CCU6 INP3 T5EUDB...
Page 422 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 212 Port 2 Input Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P2.7 Input P2_DATA.P7 INP1 CCPOS2_0 CCU6 INP2 EXINT2_0 INP3 T13HR_1 CCU6 INP4 CC62_1 CCU6 INP5 T3EUDB GPT12 INP6 T4EUDC GPT12 INP7...
Page 423: Register Description
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.4 Register Description 15.4.1 Port 0 Register Description Table 213 Register Address Space Module Base Address End Address Note PORT 48028000 48029FFF Ports 5000 5000 5000 5FFF System Control Unit - Digital Modules Table 214 Register Overview Register Short Name...
Page 424 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description 31:22 Reserved Always read as 0 PP5_STS Port 0 Pin 5 Data Value (read back of Port Data when IO is configured as output) 0, Port 0 pin 5 data value = 0 1, Port 0 pin 5 data value = 1 PP4_STS Port 0 Pin 4 Data Value (read back of Port Data when IO...
Page 425 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Port 0 Pin 0 Data Value 0, Port 0 pin 0 data value = 0 1, Port 0 pin 0 data value = 1 Table 215 RESET of P0_DATA Register Reset Type Reset Values Reset Short Name...
Page 426 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description PP1_INEN Port 0 Pin 1 Input Schmitt Trigger enable (only valid if IO is configured as output) 0, Schmitt Trigger is disabled 1, Schmitt Trigger is enabled PP0_INEN Port 0 Pin 0 Input Schmitt Trigger enable (only valid if IO is configured as output) 0, Schmitt Trigger is disabled 1, Schmitt Trigger is enabled...
Page 427 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description 31:6 Reserved Returns 0 if read. Port 0 Pin 5 Open Drain Mode Normal Mode, Output is actively driven for 0 and 1 state Open Drain Mode, Output is actively driven only for 0 state Port 0 Pin 4 Open Drain Mode Normal Mode, Output is actively driven for 0 and 1...
Page 428 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 217 RESET of P0_OD Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 Port 0 Pull-Up/Pull-Down Select Register P0_PUDSEL Offset Reset Value Port 0 Pull-Up/Pull-Down Select Register Table 218 Field Bits...
Page 429 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Port 0 Pull-Up/Pull-Down Enable Register P0_PUDEN Offset Reset Value Port 0 Pull-Up/Pull-Down Enable Register Table 219 Field Bits Type Description 31:6 Reserved Returns 0 if read. Pull-Up/Pull-Down Enable at Port 0 Bit 5 Disabled, Pull-up or Pull-down device is disabled Enabled, Pull-up or Pull-down device is enabled Pull-Up/Pull-Down Enable at Port 0 Bit 4...
Page 430 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Alternate Output Select Register P0_ALTSEL0 Offset Reset Value Port 0 Alternate Select Register 0 Table 220 Field Bits Type Description 31:6 Reserved Returns 0 if read. Table 223 Table 223 Table 223 Table 223 Table 223 Table 223 Table 220...
Page 431 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Alternate Output Select Register P0_ALTSEL1 Offset Reset Value Port 0 Alternate Select Register 1 Table 222 Field Bits Type Description 31:6 Reserved Returns 0 if read. Table 223 Table 223 Table 223 Table 223 Table 223 Table 223 Table 222...
Page 432 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O P0_PDM5 P0_PDM4 P0_PDM3 P0_PDM2 P0_PDM1 P0_PDM0 Field Bits Type Description 31:23 Reserved Returns 0 if read; should be written with 0. P0_PDM5 22:20 P0.5 Port Driver Mode Code Driver Strength and Edge Shape Strong driver and sharp edge mode, Strong driver and medium edge mode, Strong driver and soft edge mode,...
Page 433 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Reserved Returns 0 if read; should be written with 0. P0_PDM2 10:8 P0.2 Port Driver Mode Code Driver Strength and Edge Shape Strong driver and sharp edge mode, Strong driver and medium edge mode, Strong driver and soft edge mode, Weak Driver, Medium Driver,...
Page 434: Port 1 Register Description
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.4.2 Port 1 Register Description Table 225 Register Overview Register Short Name Register Long Name Offset Address Reset Value Port 1 Register Description, P1_DATA Port 1 Data Register 000000XX P1_DIR Port 1 Direction Register 00000000 P1_OD Port 1 Open Drain Control Register...
Page 435 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description PP2_STS Port 1 Pin 2 Data Value (read back of Port Data when IO is configured as output) 0, Port 0 pin 2 data value = 0 1, Port 0 pin 2 data value = 1 PP1_STS Port 1 Pin 1 Data Value (read back of Port Data when IO is configured as output)
Page 436 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O PP4_ PP2_ PP1_ PP0_ INEN INEN INEN INEN Field Bits Type Description 31:21 Reserved Returns 0 if read. PP4_INEN Port 1 Pin 4 Input Schmitt Trigger enable (only valid if IO is configured as output) 0, Schmitt Trigger is disabled 1, Schmitt Trigger is enabled Reserved...
Page 437 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Port 1 Pin 0 Direction Control Input, Direction is set to input Output, Direction is set to output Table 227 RESET of P1_DIR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 438 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Port 1 Pin 0 Open Drain Mode Normal Mode, Output is actively driven for 0 and 1 state Open Drain Mode, Output is actively driven only for 0 state Table 228 RESET of P1_OD...
Page 439 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Table 229 RESET of P1_PUDSEL Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000017 RESET_TYPE_3 Port 1 Pull-Up/Pull-Down Enable Register P1_PUDEN Offset Reset Value Port 1 Pull-Up/Pull-Down Enable Register Table 230 Field Bits...
Page 440 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Alternate Output Select Register P1_ALTSEL0 Offset Reset Value Port 1 Alternate Select Register 0 Table 231 Field Bits Type Description 31:5 Reserved Returns 0 if read. Table 234 Reserved Returns 0 if read. Table 234 Table 234 Table 234...
Page 441 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Alternate Output Select Register P1_ALTSEL1 Offset Reset Value Port 1 Alternate Select Register 1 Table 233 Field Bits Type Description 31:5 Reserved Returns 0 if read. Table 234 Reserved Returns 0 if read. Table 234 Table 234 Table 234...
Page 442 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Port Output Control Register SCU_P1_POCON0 Offset Reset Value Port Output Control Register Table 235 P1_PDM4 P1_PDM2 P1_PDM1 P1_PDM0 Field Bits Type Description 31:19 Reserved Returns 0 if read; should be written with 0. P1_PDM4 18:16 P1.4 Port Driver Mode...
Page 443 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description P1_PDM1 P1.1 Port Driver Mode Code Driver Strength and Edge Shape Strong driver and sharp edge mode, Strong driver and medium edge mode, Strong driver and soft edge mode, Weak Driver, Medium Driver, Medium Driver,...
Page 444: Port 2 Register Description
MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O 15.4.3 Port 2 Register Description Table 236 Register Overview Register Short Name Register Long Name Offset Address Reset Value Port 2 Register Description, P2_DATA Port 2 Data Register 000000XX P2_DIR Port 2 Direction Register 00000000 P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register...
Page 445 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Reserved Always read as 0 Reserved Always read as 0 Port 2 Pin 3 Data Value 0, Port 2 pin 3 data value = 0 1, Port 2 pin 3 data value = 1 Port 2 Pin 2 Data Value 0, Port 2 pin 2 data value = 0 1, Port 2 pin 2 data value = 1...
Page 446 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Port 2 Pin 7 Driver Control Enabled, Input driver is enabled Disabled, Input driver is disabled Reserved Always read as 0 Reserved Always read as 0 Reserved Always read as 0 Port 2 Pin 3 Driver Control Enabled, Input driver is enabled Disabled, Input driver is disabled...
Page 447 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description Reserved Always read as 0 Reserved Always read as 0 Pull-Up/Pull-Down Select Port 2 Bit 7 Pull-down, Pull-down device is selected Pull-up, Pull-up device is selected Reserved Always read as 0 Reserved Always read as 0 Reserved...
Page 448 MOTIX™ TLE985xQX GPIO Ports and Peripheral I/O Field Bits Type Description 31:10 Reserved Always read as 0 Reserved Always read as 0 Reserved Always read as 0 Pull-Up/Pull-Down Enable at Port 2 Bit 7 Disabled, Pull-up or Pull-down device is disabled Enabled, Pull-up or Pull-down device is enabled Reserved Always read as 0...
Page 449: General Purpose Timer Units (Gpt12)
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) General Purpose Timer Units (GPT12) 16.1 Features 16.1.1 Features Block GPT1 The following list summarizes the supported features: • /4 maximum resolution • 3 independent timers/counters • Timers/counters can be concatenated • 4 operating modes: –...
Page 450: Block Diagram Gpt1
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.2.1 Block Diagram GPT1 Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is f /4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer.
Page 451: Block Diagram Gpt2
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.2.2 Block Diagram GPT2 Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is f /2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended functionality.
Page 452: Timer Block Gpt1
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3 Timer Block GPT1 From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded. Data Registers Control Registers Interrupt Control...
Page 453: Gpt1 Core Timer T3 Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.1 GPT1 Core Timer T3 Control The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T3 is configured and controlled via its control register T3CON.
Page 454 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T3 Output Toggle Latch The overflow/underflow signal of timer T3 is connected to a block named ‘Toggle Latch’, shown in the Timer Mode diagrams. Figure 89 illustrates the details of this block. An overflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL in control register T3CON.
Page 455: Gpt1 Core Timer T3 Operating Modes
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.2 GPT1 Core Timer T3 Operating Modes Timer T3 can operate in one of several modes. Timer T3 in Timer Mode Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 000 .
Page 456 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T3 in Gated Timer Mode Gated Timer Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 010 or 011 Bit T3M.0 (T3CON.3) selects the active level of the gate input. The same options for the input frequency are available in Gated Timer Mode as in Timer Mode (see Section 16.3.5).
Page 457 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T3 in Counter Mode Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001 . In Counter Mode, timer T3 is clocked by a transition at the external input pin T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line.
Page 458 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T3 in Incremental Interface Mode Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 110 or 111 . In Incremental Interface Mode, the two inputs associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder.
Page 459 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Signal Conditioning Encoder Controller T3Input T3Input Interrupt or T4IN MC_GPT1_ENCODER Figure 94 Connection of the Encoder to the TLE985xQX For incremental interface operation, the following conditions must be met: • Bitfield T3M must be 110 or 111 •...
Page 460 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Forward Jitter Backward Jitter Forward T3IN T3EUD Contents of T3 Down Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input, i.e. T3I = '011 MCT04373 Figure 95 Evaluation of Incremental Encoder Signals, 2 Count Inputs Forward Jitter...
Page 461: Gpt1 Auxiliary Timers T2/T4 Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.3 GPT1 Auxiliary Timers T2/T4 Control Auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for Timer Mode, Gated Timer Mode, Counter Mode, or Incremental Interface Mode with the same options for the timer frequencies and the count signal as the core timer T3.
Page 462: Gpt1 Auxiliary Timers T2/T4 Operating Modes
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.4 GPT1 Auxiliary Timers T2/T4 Operating Modes The operation of the auxiliary timers in the basic operating modes is almost identical with the core timer’s operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timers T2 and T4 in Timer Mode Timer mode for an auxiliary timer Tx is selected by setting its bitfield TxM in register TxCON to 000 Count...
Page 463 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timers T2 and T4 in Gated Timer Mode Gated Timer Mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 010 or 011 Bit TxM.0 (TxCON.3) selects the active level of the gate input. Note: A transition of the gate signal at line TxIN does not cause an interrupt request.
Page 464 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timers T2 and T4 in Counter Mode Counter Mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 001 . In Counter Mode, an auxiliary timer can be clocked either by a transition at its external input line TxIN, or by a transition of timer T3’s toggle latch T3OTL.
Page 465 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in Counter Mode concatenates the core timer T3 with the respective auxiliary timer. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL is selected to clock the auxiliary timer.
Page 466 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timers T2 and T4 in Capture Mode Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to . In capture mode, the contents of the core timer T3 are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer’s external input pin TxIN.
Page 467 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timers T2 and T4 in Incremental Interface Mode Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 110 or 111 . In Incremental Interface Mode, the two inputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to an incremental encoder.
Page 468 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timers T2 and T4 in Reload Mode Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to . In reload mode, the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals.
Page 469: Gpt1 Clock Signal Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Figure 104 shows an example for the generation of a PWM signal using the “single-transition” reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions).
Page 470 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) For both ways, the basic clock determines the maximum count frequency and the timer’s resolution: Table 242 Basic Clock Selection for Block GPT1 Block Prescaler BPS1 = 01 BPS1 = 00 BPS1 = 11 BPS1 = 10 Prescaling Factor for GPT1: F(BPS1)
Page 471: Interrupt Control For Gpt1 Timers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 243 GPT1 Timer Parameters (cont’d) Module Clock f = 10 MHz Overall Module Clock f = 40 MHz Prescaler Frequency Resolution Period Frequency Resolution Period Factor 19.53 kHz 51.2 µs 3.355 s 78.125 kHz 12.8 µs 838.9 ms...
Page 472: Gpt12 Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.7 GPT12 Registers Table 245 Register Address Space Module Base Address End Address Note GPT12E 40010000 40013FFF Table 246 Register Overview Register Short Name Register Long Name Offset Address Reset Value GPT1 Registers, GPT1 Timer Registers GPT12E_T2 Timer T2 Count Register...
Page 473 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T2 Count Register GPT12E_T2 Offset Reset Value Timer T2 Count Register Table 247 Field Bits Type Description 31:16 Reserved 15:0 Timer T2 Current Value Contains the current value of the timer T2 Table 247 RESET of GPT12E_T2...
Page 474: Gpt1 Core Timer T3 Control Register
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description 31:16 Reserved 15:0 Timer T4 Current Value Contains the current value of the timer T4 Table 249 RESET of GPT12E_T4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000...
Page 475 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description T3EDGE Timer T3 Edge Detection Flag The bit is set each time a count edge is detected. T3EDGE must be cleared by software. No count, No count edge was detected Count, A count edge was detected BPS1 12:11...
Page 476 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 250 RESET of GPT12E_T3CON Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 477: Gpt1 Auxiliary Timers T2/T4 Control Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.8.3 GPT1 Auxiliary Timers T2/T4 Control Registers Timer T2 Control Register GPT12E_T2CON Offset Reset Value Timer T2 Control Register Table 251 T2DI T2CH T2ED T2IR T2UD T2RC T2UD IDIS Field Bits Type Description 31:16 Reserved Read as 0;...
Page 478 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description T2UDE Timer T2 External Up/Down Enable T2UD, Count direction is controlled by bit T2UD; input T2EUD is disconnected T2EUD, Count direction is controlled by input T2EUD T2UD Timer T2 Up/Down Control Up, Timer T2 counts up Down, Timer T2 counts down Timer T2 Input Run Bit...
Page 479 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description 31:16 Reserved Read as 0; should be written with 0. T4RDIR Timer T4 Rotation Direction Up, Timer T4 counts up Down, Timer T4 counts down T4CHDIR Timer T4 Count Direction Change The bit is set each time a count direction of timer T4 changes.
Page 480: Encoding
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description Timer T4 Mode Control (Basic Operating Mode) Timer Mode, Counter Mode, Gated low, Gated Timer Mode with gate active low Gated high, Gated Timer Mode with gate active high Reload Mode, Capture Mode, Incremental Interface Mode, (Rotation Detection Mode)
Page 481 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 254 GPT1 Overall Prescaler Factors for Internal Count Clock (Timer Mode and Gated Timer Mode) (cont’d) Individual Prescaler Common Prescaler for Module Clock for Tx BPS1 = 01 BPS1 = 00 BPS1 = 11 BPS1 = 10 TxI = 010 TxI = 011...
Page 482: Gpt1 Timer Interrupt Control Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.3.8.5 GPT1 Timer Interrupt Control Registers The Interrupt Control and Status register are located in the SCU. User Manual Rev. 2.0 2023-08-09...
Page 483: Timer Block Gpt2
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.4 Timer Block GPT2 From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded.
Page 484: Gpt2 Core Timer T6 Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Note: The timing requirements for external input signals can be found in Section 16.4.6, Section 16.6.1 summarizes the module interface signals, including pins. 16.4.1 GPT2 Core Timer T6 Control The current contents of the core timer T6 are reflected by its count register T6. This register can also be written to by the CPU, for example, to set the initial start value.
Page 485: Gpt2 Core Timer T6 Operating Modes
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Set/Clear (SW) TxOE TxOUT Overflow/ To Port Logic Underflow Shadow Core Timer TxOTL Latch To Aux. Timer Toggle Latch Logic Input Logic mc_gpt0106_otl.vsd Figure 106 Block Diagram of the Toggle Latch Logic of Core Timer T6 (x = 6) Note: T6 is also used to clock the timers in the CAPCOM units.
Page 486 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T6 in Gated Timer Mode Gated Timer Mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 010 or 011 Bit T6M.0 (T6CON.3) selects the active level of the gate input. The same options for the input frequency are available in Gated Timer Mode as in Timer Mode (see Section 16.4.6).
Page 487 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Timer T6 in Counter Mode Counter Mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 001 . In Counter Mode, timer T6 is clocked by a transition at the external input pin T6IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line.
Page 488: Gpt2 Auxiliary Timer T5 Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.4.3 GPT2 Auxiliary Timer T5 Control Auxiliary timer T5 can be configured for Timer Mode, Gated Timer Mode, or Counter Mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer.
Page 489: Gpt2 Auxiliary Timer T5 Operating Modes
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.4.4 GPT2 Auxiliary Timer T5 Operating Modes The operation of the auxiliary timer in the basic operating modes is almost identical with the core timer’s operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timer T5 in Timer Mode Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in register T5CON to 000 Count...
Page 490 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Prescaler Count Gate Auxiliary T5IRQ Ctrl. Timer T5 BPS2 T5IN Clear T5RC T5UD Up/Down T5EUD T5UDE MCB05407_X4 Figure 111 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode Note: There is no output toggle latch for T5. Start/stop of the auxiliary timer can be controlled locally or remotely.
Page 491 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of For counter operation, pin T5IN must be configured as input.
Page 492: Gpt2 Register Caprel Operating Modes
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.4.5 GPT2 Register CAPREL Operating Modes The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication.
Page 493 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Count Auxiliary T5IRQ Clock Timer T5 Clear Up/Down Edge CAPIN T5CLR Select Capture T3IN Signal T5SC Select CAPREL T3EUD Register CRIRQ Clear T6CLR MCA 05410X11 Figure 114 Capture/Reload Register CAPREL in Capture Mode When a selected trigger is detected, the contents of the auxiliary timer T5 are latched into register CAPREL and the interrupt request line CRIRQ is activated.
Page 494 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Capture/Reload Register CAPREL in Reload Mode Reload mode for register CAPREL is selected by setting bit T6SR in control register T6CON. In reload mode, the core timer T6 is reloaded with the contents of register CAPREL, triggered by an overflow or underflow of T6. This will not activate the interrupt request line CRIRQ associated with the CAPREL register.
Page 495 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency.
Page 496 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Note: The underflow signal of Timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events.
Page 497: Gpt2 Clock Signal Control
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.4.6 GPT2 Clock Signal Control All actions within the timer block GPT2 are triggered by transitions of its basic clock. This basic clock is derived from the module clock f by a basic block prescaler, controlled by bitfield BPS2 in register T6CON (see Figure 87).
Page 498: Interrupt Control For Gpt2 Timers And Caprel
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 260 GPT2 Timer Parameters System Clock = 10 MHz Overall System Clock = 40 MHz Divider Frequency Resolution Period Frequency Resolution Period Factor 5.0 MHz 200 ns 13.11 ms 20.0 MHz 50 ns 3.28 ms 2.5 MHz 400 ns...
Page 499: Gpt2 Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag in register GPT12_CR is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector, if the respective interrupt enable bit is set.
Page 500: Gpt2 Timer Control Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description 15:0 Timer T6 Current Value Contains the current value of the timer T6 Table 263 RESET of GPT12E_T6 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3...
Page 501 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) T6CL T6OT T6UD T6SR BPS2 T6OE T6UD Field Bits Type Description 31:16 Reserved T6SR Timer T6 Reload Mode Enable Disabled, Reload from register CAPREL disabled Enabled, Reload from register CAPREL enabled T6CLR Timer T6 Clear Enable Bit Not cleared, Timer T6 is not cleared on a capture event Cleared, Timer T6 is cleared on a capture event Reserved...
Page 502 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description Timer T6 Mode Control Timer Mode, Counter Mode, Gated low, Gated Timer Mode with gate active low Gated high, Gated Timer Mode with gate active high Reserved, Do not use this combination Reserved, Do not use this combination Reserved, Do not use this combination Reserved, Do not use this combination...
Page 503 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description 13:12 Register CAPREL Capture Trigger Selection Disabled, Capture disabled Positive, Positive transition (rising edge) on CAPIN or any transition on T3IN Negative, Negative transition (falling edge) on CAPIN or any transition on T3EUD Any, Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD...
Page 504: Encoding
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 266 RESET of GPT12E_T5CON Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000 RESET_TYPE_3 16.4.8.3 Encoding Encoding of Timer Count Direction Control Table 267 GPT2 Timer Count Direction Control Pin TxEUD Bit TxUDE Bit TxUD...
Page 505: Gpt2 Timer And Caprel Interrupt Control Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 269 GPT2 Auxiliary Timer T5 Input Edge Selection (Counter Mode) (cont’d) Triggering Edge for Counter Increment/Decrement Positive transition (rising edge) of T6 toggle latch T6OTL Negative transition (falling edge) of T6 toggle latch T6OTL Any transition (rising or falling edge) of T6 toggle latch T6OTL Table 270 GPT2 Core Timer T6 Input Edge Selection (Counter Mode)
Page 506: Miscellaneous Gpt12 Registers
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.5 Miscellaneous GPT12 Registers The following registers are not assigned to a specific timer block. They control general functions and/or give general information. Port Input Select Register Register PISEL selects timer input signal from several sources under software control. GPT12E_PISEL Offset Reset Value...
Page 507 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description IST4IN Input Select for T4IN T4INA, Signal T4INA is selected T4INB, Signal T4INB is selected T4INC, Signal T4INC is selected T4IND, Signal T4IND is selected IST3EUD Input Select for T3EUD T3EUDA, Signal T3EUDA is selected T3EUDB, Signal T3EUDB is selected T3EUDC, Signal T3EUDC is selected...
Page 508 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Field Bits Type Description MOD_TYPE 15:8 Module Identification Number This bitfield defines the module identification number (58 GPT12E) MOD_REV Module Revision Number MOD:_REV defines the revision number. The value of a module revision starts with 01 (first revision) Table 272 RESET of...
Page 509: Implementation Of The Gpt12 Module
MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) 16.6 Implementation of the GPT12 Module This chapter describes the implementation of the GPT12 module in the TLE985xQX device. 16.6.1 Module Connections Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2 are connected to their environment in two basic ways: •...
Page 510 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 273 GPT12 Digital Connections in TLE985xQX (cont’d) Signal from/to Module I/O to Can be used to/as T3INA CC60 count input signals for timer T3 T3INB GPT12PISEL T3INC P1.0 T3IND P2.3 T3EUDA P0.4 direction input signals for timer T3 T3EUDB P2.7...
Page 511 MOTIX™ TLE985xQX General Purpose Timer Units (GPT12) Table 273 GPT12 Digital Connections in TLE985xQX (cont’d) Signal from/to Module I/O to Can be used to/as CAPIND read trigger from T2 or T3 or T4 I CRIRQ ICU/SCU interrupt request from capture control Port Control Port pins to be used for timer input signals must be switched to input (bitfield PC in the respective port control register must be 0xxx...
Page 512: Timer2 And Timer21
MOTIX™ TLE985xQX Timer2 and Timer21 Timer2 and Timer21 This chapter describes the Timer2 and Timer21. Each timer is a 16-bit timer which additionally can function as a counter. Each Timer 2 module also provides a single channel 16-bit capture. 17.1 Features •...
Page 513: Timer2 And Timer21 Modes Overview
MOTIX™ TLE985xQX Timer2 and Timer21 17.2.1 Timer2 and Timer21 Modes Overview Table 274 Port Registers Mode Description Auto-reload Up/Down Count Disabled • Count up only • Start counting from 16-Bit reload value, overflow at FFFF • Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well •...
Page 514: Up/Down Count Disabled
MOTIX™ TLE985xQX Timer2 and Timer21 counting sequence. The overflow condition is indicated by setting bit TF2 in the T2CON register. This will then generate an interrupt request to the core. The overflow flag TF2 must be cleared by software. The auto-reload mode is further classified into two categories depending upon the DCEN control bit. 17.3.1.1 Up/Down Count Disabled If DCEN = 0, the up-down count selection is disabled.
Page 515: Up/Down Count Enabled
MOTIX™ TLE985xQX Timer2 and Timer21 T2PRE C/T2=0 THL2 C/T2=1 Overflow Timer 2 Interrupt EXF2 EXEN2 T2EX Figure 118 Auto-Reload Mode (DCEN = 0) 17.3.1.2 Up/Down Count Enabled If DCEN = 1, the up-down count selection is enabled. The direction of count is determined by the level at input pin T2EX.
Page 516 MOTIX™ TLE985xQX Timer2 and Timer21 FFFF E X F2 (Down count reload ) Underflow PREN Timer 2 ÷ THL2 prescaler Interrupt 16-bit Comparator Overflow T2EX Figure 119 Auto-Reload Mode (DCEN = 1) User Manual Rev. 2.0 2023-08-09...
Page 517: Capture Mode
MOTIX™ TLE985xQX Timer2 and Timer21 17.3.2 Capture Mode In order to enter the 16-bit capture mode, bits CP_RL2 and EXEN2 in register T2CON must be set. In this mode, the down count function must remain disabled. The timer functions as a 16-bit timer or counter and always counts up to FFFF and overflows.
Page 518: Interrupt Generation
MOTIX™ TLE985xQX Timer2 and Timer21 If bit T2RHEN is set, Timer 2 can be started by the falling edge/rising edge on pin T2EX, which is defined by bit T2REGS. Note: If pin T2 is not connected, counting clock function on pin T2 cannot be used. 17.3.4 Interrupt Generation When an interrupt event happened, the corresponding interrupt flag bit EXF2/TF2 is set.
Page 519: Mode Register
MOTIX™ TLE985xQX Timer2 and Timer21 17.4.1 Mode Register The T2MOD is used to configure Timer 2 for various modes of operation. Timer 2 Mode Register T2_MOD Offset Reset Value Timer 2 Mode Register Table 277 T2RE T2RH EDGE PREN T2PRE DCEN Field Bits...
Page 520 MOTIX™ TLE985xQX Timer2 and Timer21 Field Bits Type Description DCEN Up/Down Counter Enable DISABLED, Up/Down Counter function is disabled ENABLED, Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0) Table 277 Reset of T2_MOD Register Reset Type Reset Values...
Page 521: Control Register
MOTIX™ TLE985xQX Timer2 and Timer21 17.4.2 Control Register Control register is used to control the operating modes and interrupt of Timer 2. Timer 2 Control Register T2_CON Offset Reset Value Timer 2 Control Register Table 278 EXEN CP_R EXF2 C_T2 rwhis Field Bits...
Page 522 MOTIX™ TLE985xQX Timer2 and Timer21 Field Bits Type Description CP_RL2 Capture/Reload Select Reload, upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1). Capture, Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1.The negative or positive transition at Pin T2EX is selected by bit EDGESEL.
Page 523 MOTIX™ TLE985xQX Timer2 and Timer21 Timer 2 Control Register 1 T2_CON1 Offset Reset Value Timer 2 Control Register 1 Table 280 TF2E EXF2 Field Bits Type Description 31:2 Reserved Always read as 0 TF2EN Overflow/Underflow Interrupt Enable DISABLE, Overflow/underflow interrupt. ENABLE, Overflow/underflow interrupt.
Page 524: Timer 2 Reload/Capture Register
MOTIX™ TLE985xQX Timer2 and Timer21 17.4.3 Timer 2 Reload/Capture Register The RC2 register is used for a 16-bit reload of the timer count upon an overflow or a capture of the current timer count depending on the mode selected. Timer 2 Reload/Capture Register, Low Byte T2_RC Offset Reset Value...
Page 525: Timer 2 Count Register
MOTIX™ TLE985xQX Timer2 and Timer21 17.4.4 Timer 2 Count Register The T2_CNT register holds the current 16-bit value of the Timer 2 count. Timer 2 Register T2_CNT Offset Reset Value Timer 2 Count Register Table 282 Field Bits Type Description 31:16 Reserved Always read as 0...
Page 526: Timer2 And Timer21 Implementation Details
MOTIX™ TLE985xQX Timer2 and Timer21 17.5 Timer2 and Timer21 Implementation Details This section describes: • the TLE985xQX module related interfaces such as port connections and interrupt control • all TLE985xQX module related registers with their addresses 17.5.1 Interfaces of the Timer2 and Timer21 Overviews of the Timer2 and Timer21 kernel I/O interfaces and interrupt signals are shown in Figure 121 Figure...
Page 527 MOTIX™ TLE985xQX Timer2 and Timer21 t21_adc _trigger t21_ext_trigger T21_0 T21_SUSPEND T21_1 T21_2 Interrupt P0.x/Pin assignment T21_IRQ Control see GPIO chapter SCU_DM Module T21EX_0 TIMER21 (Kernel) T2EX P1.x/Pin assignment Module Port Control T21EX_1 see GPIO chapter (Kernel) Clock T21EX_2 Control P2.x/Pin assignment T21EX_3 see GPIO chapter Address...
Page 528: Capture/Compare Unit 6 (Ccu6)
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Capture/Compare Unit 6 (CCU6) The CCU6 is a high-resolution 16-bit capture and compare unit with application specific modes, mainly for AC drive control. Special operating modes support the control of Brushless DC-motors using Hall sensors or Back- EMF detection.
Page 529: Introduction
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) • Can be synchronized to T12 • Interrupt generation at period-match and compare-match • Single-shot mode supported • Start can be controlled by external events • Capability of counting external events Additional Specific Functions •...
Page 530: Block Diagram
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.2.1 Block Diagram The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The Timer T13 can work in compare mode only.
Page 531: Operating Timer T12
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3 Operating Timer T12 The timer T12 block is the main unit to generate the 3-phase PWM signals. A 16-bit counter is connected to 3 channel registers via comparators, which generate a signal when the counter contents match one of the channel register contents.
Page 532: T12 Overview
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.1 T12 Overview Figure 125 shows a detailed block diagram of Timer T12. The functions of the timer T12 block are controlled by bits in registers TCTR0, TCTR2, and PISEL0. Timer T12 receives its input clock (f ) from the module clock f via a programmable prescaler and an optional 1/256 divider or from an input signal T12HR.
Page 533 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) transfer enable bit STE12. Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal allows a concurrent update by software for all relevant parameters. Two further signals indicate whether the counter contents are equal to 0000 (T12_ZM = zero match) or 0001 (T12_OM = one match).
Page 534: T12 Counting Scheme
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.2 T12 Counting Scheme This section describes the clocking and counting capabilities of T12. 18.3.2.1 Clock Selection In Timer Mode (PISEL2.ISCNT12 = 00 ), the input clock f of Timer T12 is derived from the internal module clock f through a programmable prescaler and an optional 1/256 divider.
Page 535: Edge-Aligned / Center-Aligned Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.2.2 Edge-Aligned / Center-Aligned Mode In Edge-Aligned Mode (CTM = 0), timer T12 is always counting upwards (CDIR = 0). When reaching the value given by the period register (period-match T12_PM), the value of T12 is cleared with the next counting step (saw tooth shape).
Page 536 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) <Period Value> + 1 Period Value Zero Period Period T12 Count Match Match Match Zero Down Down CDIR CC6x Value n Value n+1 Value n+1 Value n+2 Shadow Transfer Shadow Transfer CCU6_MCT05510 Figure 127 T12 Operation in Center-Aligned Mode Note: Bit CDIR changes with the next timer clock event after the one-match or the period-match.
Page 537: Single-Shot Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.2.3 Single-Shot Mode In Single-Shot Mode, the timer run bit T12R is cleared by hardware. If bit T12SSC = 1, the timer T12 will stop when the current timer period is finished. In Edge-Aligned mode, T12R is cleared when the timer becomes zero after having reached the period value (see Figure 128).
Page 538: T12 Compare Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.3 T12 Compare Mode Associated with Timer T12 are three individual capture/compare channels, that can perform compare or capture operations with regard to the contents of the T12 counter. The capture functions are explained in Section 18.3.5.
Page 539 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) CC60_R To Interrupt CCPOS0 CC60_F Control Switching Rule Compare Logic CM_60 State Bit To Dead_Time Channel CC60ST Counter 0 CC60 MSEL60 MCC60S/R CC61_R To Interrupt CCPOS1 CC61_F Control Switching Rule Compare Logic CM_61 State Bit To Dead_Time Channel CC61ST...
Page 540 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) • with the next T12 clock (f ) after a compare-match when T12 is counting up (i.e., when the counter is incremented above the compare value); • with the next T12 clock (f ) after a zero-match AND a parallel compare-match when T12 is counting up. A State Bit CC6xST is cleared to 0: •...
Page 541 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Period Value = 5 T12 Count Zero Down Down CDIR Value n Value n+1 Value n+2 Value n+3 CC6x CC6x = 2 CC6x = 2 CC6x = 1 CC6x = 1 CC6x = 1 CC6x = 0 CC6x = 0 CC6x = 0...
Page 542 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Period Value CC61R CC62R T12 Count CC60R Zero Down Down Down CDIR Shadow Transfer CC60ST CC61ST CC62ST CCU6_MCT05518 Figure 135 Three-Channel Compare Waveforms User Manual Rev. 2.0 2023-08-09...
Page 543: Hysteresis-Like Control Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.3.3 Hysteresis-Like Control Mode The hysteresis-like control mode (T12MSEL.MSEL6x = 1001 ) offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by clearing the State Bit CC6xST. This can be used as a simple motor control feature by using a comparator indicating, e.g., overcurrent.
Page 544: Compare Mode Output Path
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.4 Compare Mode Output Path Figure 136 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form. As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit, CC6xST.
Page 545 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Dead-Time Value DTRES Dead-Time Dead-Time Dead-Time Counter 0 Counter 1 Counter 2 DTE0 CC60ST DTE1 CC61ST DTE2 CC62ST Dead-Time 0 Dead-Time 1 Dead-Time 2 active / passive active / passive active / passive CC60ST CC60ST CC61ST CC61ST...
Page 546: State Selection
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) T12 Counter Value Compare Value active State Bit passive CC6xST active active Dead- passive passive Time CC6xST active with Dead- passive Time CC6xST active with Dead- passive Time CCU6_MCT05521 Figure 138 Dead-Time Generation Waveforms 18.3.4.2 State Selection To support a wide range of power switches and drivers, the state selection offers the flexibility to define when an output can be active and can be modulated, especially useful for complementary or multi-phase PWM...
Page 547: Output Modulation And Level Selection
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.4.3 Output Modulation and Level Selection The last block of the data path is the Output Modulation block. Here, all the modulation sources and the trap functionality are combined and control the actual level of the output pins (controlled by the modulation enable bits T1xMODENy and MCMEN in register MODCTR).
Page 548 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) TRPS Trap Handling Block TRPEN0 CC63_O T13 Block Output active Level T13MODEN0 Modulation passive Selection CC60 CC60 CC60_O T12 Block + PSL0 COUT60_O Dead-Time T12MODEN0 MCMP0 Multi-Channel MCMP1 Mode MCMEN TRPEN1 Output active Level T13MODEN1 Modulation passive...
Page 549: T12 Capture Modes
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.5 T12 Capture Modes Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an external signal CC6xIN. In capture mode, the interrupt event CC6x_R is detected when a rising edge is detected at the input CC6xIN, whereas the interrupt event CC6x_F is detected when a falling edge is detected.
Page 550 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Counter Register MSEL6x CC6xIN Edge Capture Shadow Register Mode CC6xSR Selection Detect State Bit CC6xST Register CC6xR CC6x_R To Interrupt Logic CC6x_F CCU6_MCB05523 Figure 141 Capture Modes 2, 3 and 4 Block Diagram User Manual Rev.
Page 551 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Five further capture modes are called Multi-Input Capture Modes, as they use two different external inputs, signal CC6xIN and signal CCPOSx. Counter Register MSEL6x CC6xIN Edge Capture Mode Selection Detect State Bit Shadow Register Register CC6xR CC6xST CC6xSR...
Page 552 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 285 Multi-Input Capture Modes Overview (cont’d) MSEL6x Mode Signal Active Edge T12 Stored in 1101 CC6xIN Falling CC6xR CCPOSx Falling CC6xSR 1110 CC6xIN CC6xR CCPOSx CC6xSR 1111 – reserved (no capture or compare action) User Manual Rev.
Page 553: T12 Shadow Register Transfer
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.3.6 T12 Shadow Register Transfer A special shadow transfer signal (T12_ST) can be generated to facilitate updating the period and compare values of the compare channels CC60, CC61, and CC62 synchronously to the operation of T12. Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters.
Page 554: Timer T12 Operating Mode Selection
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) A T12 shadow register transfer takes place (T12_ST active): • while timer T12 is not running (T12R = 0), or • STE12 = 1 and a Period-Match is detected while counting up, or • STE12 = 1 and a One-Match is detected while counting down When signal T12_ST is active, a shadow register transfer is triggered with the next cycle of the T12 clock.
Page 555: T13 Overview
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) State Bit Timer T13 Capture/Compare To Output CC63ST Logic Channel CC63 Modulation Input and Control/Status Logic T13HR Synchronization to T12 CCU6_MCA05526 Figure 144 Overview Diagram of the Timer T13 Block 18.4.1 T13 Overview Figure 145 shows a detailed block diagram of Timer T13.
Page 556 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Sync. to T12 T13RSEL T13RS T13RR T13R edge detection ISCNT13 T13STR T13STD STE13 T13SSC Control T13HR edge & Status detection Counter Register T13RES T13CNT Clock Selection = 0000 T13_ZM Comp. T13_PM T13CLK T13PRE Read from Period Register T13PR T13_ST...
Page 557: T13 Counting Scheme
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.4.2 T13 Counting Scheme This section describes the clocking and the counting capabilities of T13. 18.4.2.1 Clock Selection In Timer Mode (PISEL2. ISCNT13 = 00 ), the input clock f of Timer T13 is derived from the internal module clock f through a programmable prescaler and an optional 1/256 divider.
Page 558: T13 Counting
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.4.2.2 T13 Counting The period of the timer is determined by the value in the period Register T13PR according to the following formula: = <Period-Value> + 1; in T13 clocks (f (18.3) Timer T13 can only count up, comparable to the Edge-Aligned mode of T12. This leads to very simple ‘counting rule’...
Page 559: Synchronization To T12
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.4.2.4 Synchronization to T12 Timer T13 can be synchronized to a T12 event. Bit fields T13TEC and T13TED select the event that is used to start Timer T13. The selected event sets bit T13R via HW, and T13 starts counting. Combined with the Single- Shot mode, this feature can be used to generate a programmable delay after a T12 event.
Page 560 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 289 T12 Trigger Event Additional Specifier T13TED Selected Event Specifier Reserved, no action Selected event is active while T12 is counting up (CDIR = 0) Selected event is active while T12 is counting down (CDIR = 1) Selected event is active independently of the count direction of T12 User Manual Rev.
Page 561: T13 Compare Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.4.3 T13 Compare Mode Associated with Timer T13 is one compare channel, that can perform compare operations with regard to the contents of the T13 counter. Figure 144 gives an overview on the T13 channel in Compare Mode. The channel is connected to the T13 counter register via an equal-to comparator, generating a compare match signal when the contents of the counter matches the contents of the compare register.
Page 562 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) • with the next T13 clock (f ) after a zero-match AND NO parallel compare-match. Compare-Match Compare-Match Period Value Compare T13 Count Value Zero CC63ST CCU6_MCT05533 Figure 150 T13 Compare Operation User Manual Rev. 2.0 2023-08-09...
Page 563: Compare Mode Output Path
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.4.4 Compare Mode Output Path Figure 151 gives an overview on the signal path from the channel State Bit CC63ST to its output pin COUT63. As illustrated, a user can determine the desired output behavior in relation to the current state of CC63ST. Please refer to Section 18.3.4.3 for detailed information on the output modulation for T12 signals.
Page 564: T13 Shadow Register Transfer
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) TRPS Trap Handling Block TRPEN13 Output active Level Modulation passive Selection COUT63 COUT63_O COUT63 T13 Block ECT13O PSL63 CCU6_MCA05545 Figure 152 T13 Output Modulation 18.4.5 T13 Shadow Register Transfer A special shadow transfer signal (T13_ST) can be generated to facilitate updating the period and compare values of the compare channel CC63 synchronously to the operation of T13.
Page 565 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Read Read Read Read Period Register PSL63 CC63PS T13IM T13PR Period Shadow PSL63 CC63PS T13IM Register T13PR Shadow Shadow Shadow Write Write Write Write Read Compare Register CC63R T13_ST Compare Shadow Register CC63SR Write Read CCU6_MCA05547 Figure 153 T13 Shadow Register Overview...
Page 566: Trap Handling
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.5 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input signal CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. to perform an emergency stop).
Page 567 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) T12 Count T13 Count TRPF CTRAP active TRPS Sync. to T12 TRPS Sync. to T13 TRPS No sync. CCU6_MCT05542 Figure 155 Trap State Synchronization (with TRM2 = 0) User Manual Rev. 2.0 2023-08-09...
Page 568: Multi-Channel Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.6 Multi-Channel Mode The Multi-Channel mode offers the possibility to modulate all six T12-related output signals with one instruction. The bits in bit field MCMOUT.MCMP are used to specify the outputs that may become active. If Multi-Channel mode is enabled (bit MODCTR.MCMEN = 1), only those outputs may become active, that have a 1 at the corresponding bit position in bit field MCMP.
Page 569 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) field MCMPS with the shadow transfer request bit STRMCM = 1. The option to trigger an update by SW is possible for all settings of SWSEL. By using the direct mode and bit STRMCM = 1, the update takes place completely under software control. Table 290 Multi-Channel Mode Switching Event Selection SWSEL...
Page 570: Hall Sensor Mode
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.7 Hall Sensor Mode For Brushless DC-Motors in block commutation mode, the Multi-Channel Mode has been introduced to provide efficient means for switching pattern generation. These patterns need to be output in relation to the angular position of the motor.
Page 571: Hall Pattern Evaluation
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.7.1 Hall Pattern Evaluation The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection block (with the module clock f ). In order to suppress spikes on the Hall inputs due to noise in rugged inverter environment, two optional noise filtering methods are supported by the Hall logic (both methods can be combined).
Page 572 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 292 Hall Sensor Mode Trigger Event Selection (cont’d) HSYNC Selected Event (see register T12MSEL) A T12 Period-Match while counting up (T12_PM and CDIR = 0). A T12 One-Match while counting down (T12_OM and CDIR = 1). A T12 Compare-Match of compare channel CC61 while counting up (CM_61 and CDIR = 0).
Page 573: Hall Pattern Compare Logic
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.7.2 Hall Pattern Compare Logic Figure 158 gives an overview on the double-register structure and the pattern compare logic. Software writes the next modulation pattern (MCMPS) and the corresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadow register MCMOUTS.
Page 574 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Flag IS.CHE (Correct Hall Event) is set by signal CM_CHE when the sampled Hall pattern matches the expected one (EXPH). This flag can also be set by SW by setting bit ISS.SCHE = 1. If enabled by bit IEN.ENCHE = 1, the set signal for CHE can also generate an interrupt request to the CPU.
Page 575: Hall Mode For Brushless Dc-Motor Control
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.7.4 Hall Mode for Brushless DC-Motor Control The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient control of block commutation patterns for Brushless DC-Motors. This mode is selected by setting all T12MSEL.MSEL6x bit fields of the three T12 Channels to 1000 In this mode, illustrated in Figure...
Page 576 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) CC62 Compare Hall Event captures for Time-Out and resets T12 CC62 Comp. T12 Count CC61 Compare for Phase Delay CC61 Comp. 0000 CCPOS0 CCPOS1 CCPOS2 = 101 = 001 = 011 = 010 = 110 CURH = 001 = 011...
Page 577: Interrupt Handling
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.8 Interrupt Handling This section describes the interrupt handling of the CCU6 module. 18.8.1 Interrupt Structure The HW interrupt event or the SW setting of the corresponding interrupt set bit (in register ISS) sets the event indication flags (in register IS) and can trigger the interrupt generation.
Page 578 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) T12_PM Interrupt Request T12 Counter Reg. CC6x_0IC T12_OM Interrupt Request CDIR Reg. CC6x_1IC CC6x_R T12 Capture Interrupt Request Compare Reg. CC6x_2IC CC6x_F Channels CC6x Interrupt Request Reg. CC6x_3IC T13_PM T13 Counter Interrupt Interrupt Set Control Logic Register ISS CM_63...
Page 579: General Module Operation
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.9 General Module Operation This section provides information about the: • Input selection (see Section 18.9.1) 18.9.1 Input Selection Each CCU6 input signal can be selected from a vector of four or eight possible inputs by programming the port input select registers PISEL0 and PISEL2.
Page 580: Ccu6 Register Description
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.10 CCU6 Register Description All CCU6 kernel register names described in this section will be referenced in other parts of this specification with the module name prefix “CCU6_”. Table 294 lists the CCU6 registers. Note: If a hardware and a software request to modify a bit occur simultaneously, the software wins.
Page 581: System Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 294 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value CCU6_CMPSTAT Compare State Register 0000 CCU6 Register Description, Global Modulation Control Registers CCU6_PSLR Passive State Level Register 0000 CCU6_MODCTR Modulation Control Register 0000 CCU6_TRPCTR...
Page 582 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description IST12HR 15:14 Input Select for T12HR This bit field defines the input signal used as T12HR input. T12HRA, Either signal T12HRA (if T12EXT = 0) or T12HRE (if T12EXT = 1) is selected. T12HRB, Either signal T12HRB (if T12EXT = 0) or T12HRF (if T12EXT = 1) is selected.
Page 583 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ISCC61 Input Select for CC61 This bit field defines the port pin that is used for the CC61 capture input signal. CC61_0, The input pin for CC61_0. CC61_1, The input pin for CC61_1. Reserved, Reserved Reserved, Reserved ISCC60...
Page 584: Timer 12 - Related Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ISCNT13 Input Select for T13 Counting Input This bit field defines the input event leading to a counting action of T13. T13 prescaler, The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account. TCTR4.T13CNT, Bit TCTR4.T13CNT written with 1 is a counting event.
Page 585 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 297 Double-Register Capture Modes Description 0100 The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n. 0101 The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR.
Page 586 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) T12 Capture/Compare Mode Select Register CCU6_T12MSEL Offset Reset Value T12 Capture/Compare Mode Select Register Table 300 DBYP HSYNC MSEL62 MSEL61 MSEL60 Field Bits Type Description DBYP Delay Bypass Bit DBYP defines if the source signal for the sampling of the Hall input pattern (selected by HSYNC) uses the dead-time counter DTC0 of timer T12 as additional delay or if the delay is bypassed.
Page 587 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description MSEL62 11:8 Capture/Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, Compare outputs disabled, pins...
Page 588 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description MSEL60 Capture/Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, Compare outputs disabled, pins...
Page 589 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 301 RESET of CCU6_T12 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 RESET_TYPE_3 Timer T12 Period Register Register T12PR contains the period value for timer T12. The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules.
Page 590 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description 15:0 Channel 0 Capture/Compare Value In compare mode, the bit fields CCV contain the values that are compared to the T12 counter value. In capture mode, the captured value of T12 can be read from these registers. Table 303 RESET of CCU6_CC60R...
Page 591 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description 15:0 Channel 2 Capture/Compare Value In compare mode, the bit fields CCV contain the values that are compared to the T12 counter value. In capture mode, the captured value of T12 can be read from these registers. Table 305 RESET of CCU6_CC62R...
Page 592 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Capture/Compare Shadow Register for Channel CC61 The registers CC61R can only be read by software, the modification of the value is done by a shadow register transfer from register CC61SR. The corresponding shadow registers CC61SR can be read and written by software.
Page 593 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description 15:0 Shadow Register for Channel 2 Capture/Compare Value In compare mode, the contents of bit field CCS are transferred to the bit field CCV for the corresponding channel during a shadow transfer.
Page 594 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description DTR1 Dead-Time Run Indication Bit 1 Bit DTR1 indicates the status of the dead-time generation for compare channel 1 of timer T12. Zero, The value of the corresponding dead-time counter channel is 0.
Page 595 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description DTE0 Dead-Time Enable Bit 0 Bit DTE0 enables and disables the dead-time generation for compare channel 0 of timer T12. Disabled, Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay.
Page 596: Timer 13 - Related Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.10.3 Timer 13 – Related Registers The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal.
Page 597 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13PV 15:0 T13 Period Value The value T13PV defines the counter value for T13, which leads to a period-match. On reaching this value, the timer T13 is set to zero. Table 311 RESET of CCU6_T13PR...
Page 598 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Capture/Compare Register for Channel CC63 Register CC63R is the actual compare register for T13. The value stored in CC63R is compared to the counter value of T13. The State Bit CC63ST is located in register CMPSTAT. CCU6_CC63R Offset Reset Value...
Page 599: Capture/Compare Control Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.10.4 Capture/Compare Control Registers Compare State Register The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state, and control bits defining the active/passive state of the compare channels. CCU6_CMPSTAT Offset Reset Value Compare State Register...
Page 600 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description COUT62PS Passive State Select for Compare Outputs COUT6xPS select the state of the corresponding compare channel, which is considered to be the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin.
Page 601 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description CC61PS Passive State Select for Compare Outputs Bits CC6xPS select the state of the corresponding compare channel, which is considered to be the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin.
Page 602 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description CC63ST Capture/Compare State Bits Bit CC63ST is related to T13. These bits are set and reset according to the T12 and T13 switching rules. Less, In compare mode, the timer count is less than the compare value.
Page 603 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description CC61ST Capture/Compare State Bits Bits CC6xST monitor the state of the capture/compare channels. Bits CC6xST are related to T12; bit CC63ST is related to T13. These bits are set and reset according to the T12 and T13 switching rules.
Page 604 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description Reserved MCC63R Capture/Compare Status Modification Bits (Reset) These bits are used to reset the corresponding CC63ST bits by software. This feature allows the user to individually change the status of the output lines by software, e.g.
Page 605 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description MCC62S Capture/Compare Status Modification Bit 2 (Set) This bit is used to set the corresponding CC62ST bits by software. This feature allows the user to individually change the status of the output lines by software, e.g.
Page 606 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Timer Control Register 0 Register TCTR0 controls the basic functionality of both timers T12 and T13. Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running (T12R = 0).
Page 607 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13CLK 10:8 Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the <T13CLK> peripheral clock according to the equationf 1, f 2, f 4, f 8, f 16, f...
Page 608 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T12CLK Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the <T12CLK> peripheral clock according to the equation f 1, f 2, f 4, f 8, f 16, f...
Page 609 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Timer Control Register 2 Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. Both timers can run in single-shot mode. In this mode, they stop their counting sequence automatically after one counting period with a count value of zero.
Page 610 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13TED Timer T13 Trigger Event Direction Bit field T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected. No action, Up, while T12 is counting up Down, while T12 is counting down...
Page 611 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Example If the timer T13 is intended to start at any compare event on T12 (T13TEC = 100 ), the trigger event direction can be programmed to: • counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up •...
Page 612 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13RS Timer T13 Run Set Setting this bit sets the T13R bit. No influence, T13R is not influenced. T13R set, T13R is set, T13 counts. T13RR Timer T13 Run Reset Setting this bit resets the T13R bit.
Page 613: Global Modulation Control Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.10.5 Global Modulation Control Registers Modulation Control Register Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals.
Page 614 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description MCMEN Multi-Channel Mode Enable Disabled, The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled. Enabled, The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled.
Page 615 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) TRPPEN TRPEN13 TRPEN TRPM2 TRPM10 Field Bits Type Description TRPPEN Trap Pin Enable Disabled, The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF.
Page 616 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description TRPM2 Trap Mode Control Bit 2 Hardware reset, The trap state can be left (return to normal operation = bit TRPS = 0) as soon as the input CTRAP becomes inactive.
Page 617 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 322 Trap Mode Control Bits 1, 0 Field Bits Description TRPM0, TRPM1 A synchronization to the timer driving the PWM pattern permits to avoid unintended short pulses when leaving the trap state. The combination (TRPM1, TRPM0) leads to: , The trap state is left (return to normal operation according to TRPM2) when a zero-match of T12 (while counting up) is detected...
Page 618 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Passive State Level Register Register PSLR defines the passive state level driven by the output pins of the module. The passive state level is the value that is driven by the port pin during the passive state of the output. During the active state, the corresponding output pin drives the active state level, which is the inverted passive state level.
Page 619: Multi-Channel Modulation Control Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Table 323 RESET of CCU6_PSLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 RESET_TYPE_3 Notes 1. Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines. The bits are updated with the T12 shadow transfer.
Page 620 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description Reserved Returns 0 if read. CURHS 13:11 Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH. The bit field is transferred to bit field CURH if an edge on the hall input pins CCPOSx (x = 0, 1, 2) is detected.
Page 621 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) CURH EXPH MCMP Field Bits Type Description 15:14 Reserved Returns 0 if read. CURH 13:11 Current Hall Pattern Bit field CURH is written by a shadow transfer from bit field CURHS.The contents are compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired (= expected) hall pattern or a wrong pattern.
Page 622 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description MCMP Multi-Channel PWM Pattern Bit field MCMP is written by a shadow transfer from bit field MCMPS. It contains the output pattern for the multi-channel mode. If this mode is enabled by bit MCMEN in register MODCTR, the output state of the following output signal can be modified: Bit 0: multi-channel state for output CC60 Bit 1: multi-channel state for output COUT60...
Page 623 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description STE13U Shadow Transfer Enable for T13 Upcounting This bit enables the shadow transfer T13_ST if flag MCMOUT.R is set or becomes set while a T13 period match is detected. No action, Enabled, The T13_ST shadow transfer mechanism is enabled if MCMEN = 1.
Page 624 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description SWSEL Switching Selection Bit field SWSEL selects one of the following trigger request sources (next multi-channel event) for the shadow transfer from MCMPS to MCMP. The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer.
Page 625: Interrupt Control Registers
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.10.7 Interrupt Control Registers Capture/Compare Interrupt Status Register Register IS contains the individual interrupt request bits. This register can only be read; write actions have no impact on the contents of this register. The software can set or reset the bits individually by writing to the registers ISS (to set the bits) or to register ISR (to reset the bits).
Page 626 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description Wrong Hall Event On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx. If both comparisons (CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set. Not detected, A transition to a wrong hall event (not the expected one) has not yet been detected since this bit has been reset for the last time.
Page 627 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description T12PM Timer T12 Period-Match Flag Not detected, A timer T12 period-match (while counting up) has not yet been detected since this bit has been reset for the last time. Detected, A timer T12 period-match (while counting up) has been detected.
Page 628 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ICC60R Capture, Compare-Match Rising Edge Flag In compare mode, a compare-match has been detected while T12 was counting up. In capture mode, a rising edge has been detected at the input CC60. Not occurred, The event has not yet occurred since this bit has been reset for the last time.
Page 629 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description SWHC Software Hall Compare No action, Set, The Hall compare action is triggered. STRPF Set Trap Flag No action, Set, Bits TRPF and TRPS in register IS will be set. ST13PM Set Timer T13 Period-Match Flag No action,...
Page 630 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) CCU6_ISR Offset Reset Value Capture/Compare Interrupt Status Reset Table 329 Register RSTR RIDLE RWHE RCHE RTRPF RT13PM RT13CM RT12PM RT12OM RCC62F RCC62R RCC61F RCC61R RCC60F RCC60R Field Bits Type Description RSTR Reset STR Flag No action, Reset, Bit STR in register IS will be reset.
Page 631 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description RCC62F Reset Capture, Compare-Match Falling Edge Flag No action, Reset, Bit CC62F in register IS will be reset. RCC62R Reset Capture, Compare-Match Rising Edge Flag No action, Reset, Bit CC62R in register IS will be reset. RCC61F Reset Capture, Compare-Match Falling Edge Flag No action,...
Page 632 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ENSTR Enable Multi-Channel Mode Shadow Transfer Interrupt No interrupt, No interrupt will be generated if the set condition for bit STR in register IS occurs. Interrupt, An interrupt will be generated if the set condition for bit STR in register IS occurs.
Page 633 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ENT13CM Enable Interrupt for T13 Compare-Match No interrupt, No interrupt will be generated if the set condition for bit T13CM in register IS occurs. Interrupt, An interrupt will be generated if the set condition for bit T13CM in register IS occurs.
Page 634 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description ENCC60F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0 No interrupt, No interrupt will be generated if the set condition for bit CC60F in register IS occurs. Interrupt, An interrupt will be generated if the set condition for bit CC60F in register IS occurs.
Page 635 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description INPT13 13:12 Interrupt Node Pointer for Timer T13 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit T13CM (if enabled by bit ENT13CM) or for bit T13PM (if enabled by bit ENT13PM).
Page 636 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) Field Bits Type Description INPCC61 Interrupt Node Pointer for Channel 1 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit CC61R (if enabled by bit ENCC61R) or for bit CC61F (if enabled by bit ENCC61F).
Page 637: Tle985Xqx Module Implementation Details
MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) 18.11 TLE985xQX Module Implementation Details This section describes the CCU6 module interfaces with the clock control, port connections, interrupt control, and address decoding. 18.11.1 Interfaces of the CCU6 Module An overview of the Mod_Name kernel I/O interface is shown in Figure 164.
Page 638 MOTIX™ TLE985xQX Capture/Compare Unit 6 (CCU6) CC60 CC61 /CTRAP P0.2/P2.3/P2.2 SRC0 Interrupt SRC1 CCPOS0 P2.1/P0.3/P2.0 Controller SRC2 CCPOS1 SRC3 P2.3/P0.4/P1.4 CCPOS2 P2.7/P0.5/P1.2 CC60 P0.4/P2.3 T12_SUSPEND COUT60 T13_SUSPEND P0.5 CC61 CCU6 Port P1.0/P2.1 Module Control COUT61 (Kernel) P1.1 Clock CC62 Control P0.1/P2.7 COUT62 P1.4...
Page 639: Uart1/2
MOTIX™ TLE985xQX UART1/2 UART1/2 19.1 Features • Full-duplex asynchronous modes – 8-Bit or 9-Bit data frames, LSB first – fixed or variable baud rate • Receive buffered (1 Byte) • Multiprocessor communication • Interrupt generation on the completion of a data transmission or reception •...
Page 640: Block Diagram
MOTIX™ TLE985xQX UART1/2 19.2.1 Block Diagram UART disreq from SCU _DM SCU_D Interrupt RXD_0 URIOS Control RXD_1 SCU_DM P0.x UART Port Control Module P1.x (Kernel ) Clock UART2 Baud Rate f BR P2.x Control Generator Address RXDO_2 Decoder SCU_DM AHB Interface SSC Module GPIOs Figure 165 UART Block Diagram...
Page 641: Mode 1, 8-Bit Uart, Variable Baud Rate
MOTIX™ TLE985xQX UART1/2 output position, it has a 1 and a sequence of zeros to its left. The control block then executes one last shift before setting the TI bit. Reception is started by the condition REN = 1 and RI = 0. At the start of the reception cycle, 11111110 is written to the receive shift register.
Page 642 MOTIX™ TLE985xQX UART1/2 Clock txd_en lin_rx _rdy SEND Data Shift Start Stop Clock Start Stop Bit Detector Sample Times Shift _finish Figure 166 Serial Interface, Mode 1, Timing Diagram User Manual Rev. 2.0 2023-08-09...
Page 643: Mode 2, 9-Bit Uart, Fixed Baud Rate
MOTIX™ TLE985xQX UART1/2 19.3.3 Mode 2, 9-Bit UART, Fixed Baud Rate In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The 9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit received is placed in RB8 (SCON.2).
Page 644 MOTIX™ TLE985xQX UART1/2 Clock txd_en lin_rx _rdy SEND Data Shift Start Stop Clock Start Stop Bit Detector Sample Times Shift _finish Figure 167 Serial Interface, Modes 2 and 3, Timing Diagram User Manual Rev. 2.0 2023-08-09...
Page 645: Multiprocessor Communication
MOTIX™ TLE985xQX UART1/2 19.4 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes, 9 data bits are received. The 9th data bit goes into RB8 (SCON.2).
Page 646: Baud Rate Generation
MOTIX™ TLE985xQX UART1/2 19.6 Baud Rate Generation There are several ways to generate the baud rate clock for the serial port, depending on the mode in which they are operating. The baud rates in modes 0 and 2 are fixed to f /2 and f /64 respectively, while the variable baud rate in modes 1 and 3 is generated based on the setting of the baud-rate generator in SCU (see...
Page 647 MOTIX™ TLE985xQX UART1/2 The value of PRE (prescaler) is chosen by the bit field BCON.BRPRE. BR_VALUE represents the contents of the reload value, taken as unsigned 11-bit integer from the bit field BGL/BGH.BR_VALUE. n/32 is defined by the fractional divider selection in bit field BGL.FDSEL. The maximum baud rate that can be generated is limited to f /32.
Page 648: Lin Support In Uart
MOTIX™ TLE985xQX UART1/2 19.7 LIN Support in UART The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2.
Page 649: Lin Header Transmission
MOTIX™ TLE985xQX UART1/2 13 bits of dominant value, including the start bit, followed by a Sync Break Delimiter, as shown in Figure 171. The Sync Break Delimiter will be at least one nominal bit time long. A slave node will use a Sync Break detection threshold of 11 nominal bit times. Start Break delimit...
Page 650: Automatic Synchronization To The Host
MOTIX™ TLE985xQX UART1/2 19.7.3 Automatic Synchronization to the Host Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps that are to be included in the user software: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host...
Page 651: Initialization Of Break/Synch Field Detection Logic
MOTIX™ TLE985xQX UART1/2 19.7.4 Initialization of Break/Synch Field Detection Logic The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using Timer 2. Initialization consists of: • Setting of the serial port of the microcontroller to Mode 1 (8-bit UART, variable baud rate) for communication.
Page 652 MOTIX™ TLE985xQX UART1/2 The baud rate range defined by different SCU_LINST.BGSEL settings is shown in Table 336. Table 336 BGSEL Bit Field Definition for Different Input Frequencies BGSEL Baud Rate Select for Detection BGSEL BGSEL /(2184*2 ) to f /(72*2 40 MHz 18.3 kHz to 555.6 kHz 9.2 kHz to 277.8 kHz...
Page 653: Lin Baud Rate Detection
MOTIX™ TLE985xQX UART1/2 19.7.6 LIN Baud Rate Detection The baud rate detection for LIN is shown in Figure 173, the Header LIN frame consists of the: • Sync Break (13 bit times low) • Sync Byte (55 • Protected ID field 1st negative transition, T2 automatically Last captured value of T2...
Page 654: Register Description
MOTIX™ TLE985xQX UART1/2 19.8 Register Description Table 337 Register Address Space Module Base Address End Address Note UART1 4802 0000 4802 1FFF UART1 UART2 4802 2000 4802 3FFF UART2 Table 338 Register Overview Register Short Name Register Long Name Offset Address Reset Value UART Registers,...
Page 655 MOTIX™ TLE985xQX UART1/2 Serial Data Buffer UART_SBUF Offset Reset Value Serial Data Buffer Table 339 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Serial Interface Buffer Register Table 339 Reset of UART_SBUF Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 656 MOTIX™ TLE985xQX UART1/2 Serial Channel Control Register UART_SCON Offset Reset Value Serial Channel Control Register Table 340 Field Bits Type Description 31:8 Reserved Returns 0 if read; should be written with 0. Serial Port Operating Mode Selection Table 333 Serial Port Operating Mode Selection Table 333 Enable Serial Port Multiprocessor Communication in Modes 2 and 3...
Page 657 MOTIX™ TLE985xQX UART1/2 Field Bits Type Description Transmit Interrupt Flag This is set by hardware at the end of the 8th bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. Must be cleared by flag SCONCLR.TICLR. This flag can also be set by software.
Page 658: Baud-Rate Generator Control And Status Registers
MOTIX™ TLE985xQX UART1/2 Serial Channel Control Clear Register UART_SCONCLR Offset Reset Value Serial Channel Control Clear Register Table 341 RB8C TICL RICL Field Bits Type Description 31:3 Reserved Returns 0 if read; should be written with 0. RB8CLR SCON.RB8 Clear Flag No Clear, RB8 Flag is not cleared.
Page 659: Interfaces Of The Uart Module Mod_Name
MOTIX™ TLE985xQX UART1/2 19.9 Interfaces of the UART Module Mod_Name An overview of the Mod_Name I/O interface is shown in Figure 174. In mode 0 (the serial port behaves as a shift register) data is shifted in through RXD_1 and out through RXDO, while the TXD_1 line is used to provide a shift clock which can be used by external devices to clock data in and out.
Page 660: Lin Transceiver
MOTIX™ TLE985xQX LIN Transceiver LIN Transceiver 20.1 Features General Functional Features • Compliant to LIN2.2 Standard, backward compatible to LIN1.3, LIN2.0 and LIN 2.1 • Compliant to SAE J2602 (Slew Rate, Receiver hysteresis) Special Features • Measurement of LIN Master baudrate via Timer 2 •...
Page 661: Block Diagram
MOTIX™ TLE985xQX LIN Transceiver 20.2.1 Block Diagram LIN Transceiver 30 k LIN_CTRL_STS CTRL Driver + TxD_1 LIN-FSM Curr. Limit. + from UART STATUS GND_LIN Transmitter PMU_LIN_WAKE_EN.LIN_EN Filter RxD_1 to UART Filter Receiver LIN_Wake Sleep Comparator LIN_Block_Diagram_Customer.vsd GND_LIN Figure 175 LIN Transceiver Block Diagram 20.3 Functional Description The supported baud rates are:...
Page 662 MOTIX™ TLE985xQX LIN Transceiver LIN MODE CONTROL LIN Sleep-Mode (LSLM) LSLM→LHVIOM Transition LHVIOM→LSLM Transition LSLM→ LNM Transition LNM→LSLM Transition LIN Normal - Mode (LNM) LSLM→LROM Transition LROM→LSLM Transition LNM→LROM Transition LROM→LNM Transition High Voltage IO- Mode (LHVIO) LIN Recieve-Only- Mode (LROM) Figure 176 SFR controlled LIN Transceiver State machine LIN Normal Mode (LNM)
Page 663 MOTIX™ TLE985xQX LIN Transceiver The transitions between the described states can only be executed when corresponding conditions are fulfilled. The detailed description of the transitions can be found below. LIN Sleep Mode (LSLM) - LIN Receive-Only Mode (LROM) Transition Description •...
Page 664: Lin Transceiver Error Handling
MOTIX™ TLE985xQX LIN Transceiver – LIN_CTRL.MODE is configured to LIN Normal Mode after LIN_CTRL.HV_MODE flag was set and – Feedback Signals of Mode and Slope Mode are ok and – LIN Transceiver LIN_CTRL.OT_STS and LIN_CTRL.OC_STS are not set • LHVIO - LSLM transition is executed when: –...
Page 665: Slope Modes
MOTIX™ TLE985xQX LIN Transceiver 20.3.3 Slope Modes The LIN Module provides some additional slope mode features which can be used for EoL (End of Line) programming or to reduce emission in case of usage of lower baud rates. The configurable slope modes are: Normal Slope Mode This mode is usually used to transmit and receive messages on the bus.
Page 666: Lin Transceiver Slope Mode Status
MOTIX™ TLE985xQX LIN Transceiver A Mode Error indicates a problem in the LIN configuration. If that applies, check the LIN software configuration, and whenever this does not improve the feedback mode it is recommended to enter Sleep Mode. 20.3.5 LIN Transceiver Slope Mode Status The LIN transceiver provides the possibility to monitor the on chip status of the slope control through internally generated feedback signals.
Page 667: Register Definition
MOTIX™ TLE985xQX LIN Transceiver 20.4 Register Definition Register Functionality according Table 345 Reset value according Table 345 Table 344 shows the module base addresses. Table 344 Register Address Space Module Base Address End Address Note 4801E000 4801FFFF Table 345 Register Overview Register Short Name Register Long Name Offset Address...
Page 668 MOTIX™ TLE985xQX LIN Transceiver Field Bits Type Description 31:23 Reserved Always read as 0 Reserved Always read as 1 HV_MODE LIN Transceiver High Voltage Input - Output Mode Note: switching to HVIO-Mode (this configuration bit gets effective) is only possible when transceiver is in Sleep Mode. DISABLE, High Voltage Mode Entry is disabled ENABLE, High Voltage Mode Entry is enabled 20:19...
Page 669 MOTIX™ TLE985xQX LIN Transceiver Field Bits Type Description MODE LIN transceiver power mode control LIN Sleep Mode, LIN module switched to LIN Sleep Mode LIN Receive-Only Mode, LIN module switched to LIN Receive Only Mode n.u., not used LIN Normal Mode, LIN module switched to LIN Normal Mode LIN Transceiver enable DISABLE, LIN module disable ENABLE, LIN module enable...
Page 670 MOTIX™ TLE985xQX LIN Transceiver LIN Transceiver Interrupt Status LIN_IRQS Offset Reset Value LIN Transceiver Interrupt Status Table 347 TXD_ OT_S M_SM TXD_ OC_I OT_I M_SM TMOU _ERR TMOU _ERR T_S* _STS T_IS Field Bits Type Description 31:12 Reserved Always read as 0 TXD_TMOUT_ LIN TXD time-out Status NO_TIMEOUT, no time-out occurred...
Page 671 MOTIX™ TLE985xQX LIN Transceiver Field Bits Type Description Reserved Always read as 1 Table 347 RESET of LIN_IRQS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 672 MOTIX™ TLE985xQX LIN Transceiver LIN Transceiver Interrupt Status Register Clear LIN_IRQCLR Offset Reset Value LIN Transceiver Interrupt Status Register Table 348 Clear TXD_ OT_S M_SM TXD_ OC_I OT_I M_SM TMOU _ERR TMOU _ERR T_SC T_I* _ISC Field Bits Type Description 31:12 Reserved Always read as 0...
Page 673 MOTIX™ TLE985xQX LIN Transceiver Field Bits Type Description M_SM_ERR_I LIN Transceiver Mode Error - Slope Mode Error Interrupt Status Clear NO_Clear, overtemperature not cleared Clear, overtemperature cleared Reserved Always read as 1 Table 348 RESET of LIN_IRQCLR Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 674: Lin Transceiver Interrupts
MOTIX™ TLE985xQX LIN Transceiver Field Bits Type Description Reserved Always read as 1 Table 349 RESET of LIN_IRQEN Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 20.5 LIN Transceiver Interrupts The LIN Transceiver has four different interrupt sources: LIN-Interrupt Sources: •...
Page 675: High-Speed Synchronous Serial Interface Ssc1/2
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 High-Speed Synchronous Serial Interface SSC1/2 21.1 Features • Master and Slave Mode operation – Full-duplex or half-duplex operation • Transmit and receive double buffered • Flexible data format – Programmable number of data bits: 2 to 16 bits –...
Page 676: Block Diagram
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.2.1 Block Diagram Figure 178 shows all functional relevant interfaces associated with the SSC Kernel. MRSTA MRSTB MTSR SCU_DM Interrupt Control MTSRA P0.x MTSRB Port Module P1.x MRST Control (Kernel) Clock hw_clk P2.x Control SCLKA SCLKB...
Page 677: Operating Mode Selection
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 PCLK SS_CLK Baud-rate Clock Generator Control MS_CLK Shift Clock Receive Int. Request SSC Control Block Transmit Int. Request Register CON Error Int. Request Status Control TXD(Master) RXD(Slave) 16-Bit Shift Control TXD(Slave) Register RXD(Master) Transmit Buffer Receive Buffer Register TB...
Page 678: Full-Duplex Operation
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Note: Only one SSC (etc.) can be master at a given time. The transfer of serial data bits can be programmed in many respects: • The data width can be specified from 2 bits to 16 bits •...
Page 679 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 for master operation generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock, their pin SCLK must be switched to input mode. The output of the master’s shift register is connected to the external transmit line, which in turn is connected to the slaves’...
Page 680 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line actively to a low-level when transmitting a zero bit. The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave.
Page 681: Half-Duplex Operation
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.3.4 Half-Duplex Operation In a Half-Duplex Mode, only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both the MTSR and MRST pins of each device, the shift clock line is connected to the SCLK pin.
Page 682: Port Control
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Note: Of course, this can happen only in multiples of the selected basic data width, because it would require disabling/enabling of the SSC to reprogram the basic data width on-the-fly. 21.3.5.1 Port Control The SSC uses three lines to communicate with the external world.
Page 683: Baud Rate Generation
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.3.6 Baud Rate Generation The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability, allowing baud rate generation independent of the timers. Figure 179 shows the baud-rate generator. Figure 183 shows the baud-rate generator of the SSC in more detail.
Page 684: Error Detection Mechanisms
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Table 350 Typical Baud Rates of the SSC (f = 40 MHz) (cont’d) hw_clk Reload Value Baud Rate (= f Deviation MS_CLK/SS_CLK 00C7 100 kBaud 0.0% 07CF 10 kBaud 0.0% 4E1F 1 kBaud 0.0% FFFF 305.18 Baud...
Page 685 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST (Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK.
Page 686 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 The cause of an error interrupt request (receive, phase, baud rate, transmit error) can be identified by the error status flags in control register CON. Note: In contrast to the error interrupt request line EIR, the error status flags CON.TE, CON.RE, CON.PE, and CON.BE, are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software.
Page 687: Interrupts
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.4 Interrupts The three SSC interrupts can be separately enabled or disabled by setting or clearing their corresponding enable bits in SFR SCU_MODIEN. For a detailed description of the various interrupts see Section 21.3.
Page 688: Ssc Kernel Registers
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.5 SSC Kernel Registers There are two SSC kernels in the TLE985xQX, namely SSC1 and SSC2. Table 352 shows the SSC module base addresses. Table 352 Register Address Space Module Base Address End Address Note SSC1 48024000...
Page 689: Configuration Register
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 MIS_ MIS_ Field Bits Type Description 31:5 Reserved Always read as 0; should be written with 0. Global SSC12 Input Select Inputs SSC12_S_SCK_0, SSC12_S_MTSR_0, and SSC12_M_MRST_0 are selected if CIS, SIS or MIS_O is 1. Inputs SSC12_S_SCK_1, SSC12_S_MTSR_1, and SSC12_M_MRST_1 are selected if CIS, SIS or MIS_O is 1.
Page 690 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Control Register SSC_CON Offset Reset Value Control Register Table 355 AREN Field Bits Type Description 31:29 Reserved Always read as 0; should be written with 0. Busy Flag Can only be read when EN=1 (operating mode). Invalid data when EN=0 (programming mode).
Page 691 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Field Bits Type Description Receive Error Flag Can only be read when EN=1 (operating mode). Invalid data when EN=0 (programming mode). NO, error. ERROR, Reception completed before the receive buffer was read. Transmit Error Flag Can only be read when EN=1 (operating mode).
Page 692 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Field Bits Type Description Baud Rate Error Enable Can only be accessed when EN=0 (programming mode). Invalid data when EN=1 (operating mode). IGNORE, baud rate errors. CHECK, baud rate errors. Phase Error Enable Can only be accessed when EN=0 (programming mode).
Page 693 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Field Bits Type Description Data Width Selection Can only be accessed when EN=0 (programming mode). Invalid data when EN=1 (operating mode). 0000 Reserved, Do not use this combination. 0001 2, Transfer Data Width is 2 (BM+1). 1111 16, Transfer Data Width is 16 bits (BM+1).
Page 694: Baud Rate Timer Reload Register
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 Interrupt Status Register Clear SSC_ISRCLR Offset Reset Value Interrupt Status Register Clear Table 356 BECL PECL RECL TECL Field Bits Type Description 31:12 Reserved Returns 0 if read; should be written with 0. BECLR Baud Rate Error Flag Clear NO, No error clear.
Page 695 MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 BR_VALUE Field Bits Type Description 31:16 Reserved Returns 0 if read; should be written with 0. BR_VALUE 15:0 Baud Rate Timer/Reload Register Value Reading BR returns the 16-bit contents of the baud rate timer.
Page 696: Transmitter Buffer Register
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 21.5.4 Transmitter Buffer Register Transmitter Buffer Register The SSC transmitter buffer register TB contains the transmit data value. SSC_TB Offset Reset Value Transmitter Buffer Register Table 358 TB_VALUE Field Bits Type Description 31:16 Reserved Returns 0 if read;...
Page 697: Output Multiplexing
MOTIX™ TLE985xQX High-Speed Synchronous Serial Interface SSC1/2 RB_VALUE Field Bits Type Description 31:16 Reserved Returns 0 if read; should be written with 0. RB_VALUE 15:0 Receive Data Register Value RB contains the received data value RB_VALUE. Unselected bits of RB will be not valid and should be ignored.
Page 698: Measurement Unit
MOTIX™ TLE985xQX Measurement Unit Measurement Unit 22.1 Features • 1 x 10-bit ADC with 12 inputs • Supply Voltage Attenuators with attenuation of VBAT_SENSE, VS, MONx, P2.x, CSA. • 1 x 8-bit ADC with 9 inputs • Supply Voltage Attenuators with attenuation of VS, VDDEXT, VSD, VCP, VDDP, VBG, VDDC, T_SENSE1 (Central Temperature Sensor), T_SENSE2 (Bridge Driver Charge Pump Temperature Sensor).
Page 699: Block Diagram
MOTIX™ TLE985xQX Measurement Unit 22.2.1 Block Diagram The Structure of the Measurement Functions Module is shown in the following figure. VDDC VBAT_SENSE VBAT_SENSE MON1 VMONx MON2 VMONx MON3 VMONx MON4 VMONx P2.0 DPP1 VREF P2.1 P2.2 P2.3 ADC 1 CH10 CH11 CH12 P2.7...
Page 700: Measurement Unit Register Overview
MOTIX™ TLE985xQX Measurement Unit 22.2.2 Measurement Unit Register Overview Table 361 Register Address SpaceAddress Space for Measurement Unit Registers Module Base Address End Address Note 48018000 4801BFFF Measurement Unit Table 362 Register Overview Register Short Name Register Long Name Offset Address Reset Value Supplement Modules Control and Status Register,...
Page 701: 8-Bit - 10 Channel Adc Core
MOTIX™ TLE985xQX Measurement Unit 22.3 8-bit - 10 Channel ADC Core The 8-bit ADC Core operates at the VDDC Supply Voltage. This enables the user to operate the measurement system down to reset threshold. The ADC can also be operated independently from the DPP unit. This enables the user to build up a software controlled measurement cycle.
Page 702: 10-Bit - 14 Channel Adc Core
MOTIX™ TLE985xQX Measurement Unit 22.4 10-bit - 14 Channel ADC Core The 10-bit ADC is using Port 2.x, MON’s, CSA, VS and Vbat_sense as inputs. The configuration possibilities of the input channels are described in Analog Digital Converter ADC10B (ADC1) 22.4.1 Transfer Characteristics of ADC1 The transfer function of ADC1 can be expressed by the equation below:...
Page 703: Central And Charge Pump Temperature Sensor
MOTIX™ TLE985xQX Measurement Unit 22.5 Central and Charge Pump Temperature Sensor This module is a quasi combination of a main on-chip temperature sensor and a charge pump temperature sensor. Module Features • 2 operation modes with Mode 1 - temperature range corresponds to differential output voltage range 0 …1.2V (output voltage shift enabled), resolution approximately 10°C.
Page 704: Supplement Modules
MOTIX™ TLE985xQX Measurement Unit 22.6 Supplement Modules The purpose of the supplement modules is to enable a certain infrastructure on the device to guarantee a fail safe operation: Module Features • Bandgap Reference Voltage with accuracy ± 1.5%. • Bandgap is monitored by an independent reference voltage. •...
Page 705: Supplement Modules Control And Status Register
MOTIX™ TLE985xQX Measurement Unit 22.6.2 Supplement Modules Control and Status Register The next chapter lists the diagnosis and configuration possibilities of the supplement modules. Table 363 Register Overview Register Short Name Register Long Name Offset Address Reset Value Supplement Modules Control and Status Register, MF_REF1_STS Reference 1 Status Register...
Page 706 MOTIX™ TLE985xQX Measurement Unit Field Bits Type Description Reserved Always read as 0 Reserved Always read as 0 Table 364 RESET of MF_REF1_STS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 000000C1 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 707: Measurement Core Module (Incl. Adc2)
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Measurement Core Module (incl. ADC2) 23.1 Features • 9 individually programmable channels split into two groups of user configurable and non user configurable • Individually programmable channel prioritization scheme for measurement unit • Two independent filter stages with programmable low-pass and time filter characteristics for each channel •...
Page 708: Block Diagram
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.2.1 Block Diagram MUX_SEL<3:0> Channel Controller (Sequencer) ADC2 - SFR 1st Order IIR 8 Bit ADC VREF UP_X_STS + / - Calibration Unit: THy_z_UPPER. VDDEXT VDDP y= a + (1+b)*x THy_z_LOWER. PMU-VBG + / - LOW_X_STS VDDC BDrv CP Temp.
Page 709: Adc2 - Core (8-Bit Adc)
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.3 ADC2 - Core (8-bit ADC) 23.3.1 Functional Description The different sequencer modes are controlled by SFR Register: • “Normal Sequencer Mode” described in the Chapter Channel Controller. • “Exceptional Interrupt Measurement” (EIM), upon hardware event, the channel programmed in ADC2_CHx_EIM is inserted after the current measurement is finished.
Page 710: Adc2 Control Registers
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.3.2 ADC2 Control Registers The ADC2 is fully controllable by the below listed sfr Registers. The control must be enabled by setting all sequencer bits to zero. . To enable the sequencer again this corresponding bits in the sequencer register must be set to one again.
Page 711 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC2 Control Register ADC2_CTRL_STS Offset Reset Value ADC2 Control and Status Register Table 367 IN_MUX_SEL rwh1 Field Bits Type Description 31:25 Reserved Always read as 0 Reserved Always read as 0 23:12 Reserved Always read as 0 IN_MUX_SEL 11:8...
Page 712 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description rwh1 ADC2 Start of Sampling/Conversion (software mode) Note: Bit is set by software to start sampling and conversion and it is cleared by hardware once the conversion is finished ADC2_SOC can be only written if the DPP is in software mode.
Page 713 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC2 HV Status Register ADC2_STATUS Offset Reset Value ADC2 HV Status Register Table 368 READ Field Bits Type Description 31:2 Reserved Always read as 0 READY HVADC Ready bit Not ready, Module in power down or in init phase Ready, set automatically 5 ADC clock cycles after module is enabled Reserved...
Page 714: Channel Controller
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.4 Channel Controller 23.4.1 Functional Description The task of each channel controller is a prioritization of the individual measurement channels. The sequencing scheme is illustrated in the example of following table and can be programmed individually for measurement unit.
Page 715 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2)        meas, n meas (23.2) The timing of the analog MUX and the digital DEMUX is controlled by the channel controller accordingly. The analog MUX with sample and hold stage needs one clock cycle for channel switching and the ADC consumes, as default setting, 12 clock cycles for the sampling of the input voltage.
Page 716: Channel Controller Control Registers
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.4.2 Channel Controller Control Registers The Channel Controller can be configured by the SFR Register listed in Table 370. The registers which cannot be written by the user have the attribute rwpt. Table 370 Register Overview Register Short Name Register Long Name...
Page 717 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) CALIB_EN_8_0 rwpt Field Bits Type Description 31:9 Reserved Always read as 0 CALIB_EN_8_0 rwpt Calibration Enable for Channels 8 to 0 The following values can be ored: 0 0000 0001 CH0_EN, Channel 0 calibration enable 0 0000 0010 CH1_EN, Channel 1 calibration enable 0 0000 0100...
Page 718 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) SAMPLE_TIME_i MCM_ MCM_ PD_N rwpt Field Bits Type Description 31:16 Reserved Always read as 0 15:12 Reserved Always read as 0 SAMPLE_TIME_int 11:8 Sample time of ADC2 MICLK4, 4 MI_CLK clock periods MICLK6, 6 MI_CLK clock periods MICLK8, 8 MI_CLK clock periods MICLK10, 10 MI_CLK clock periods MICLK12, 12 MI_CLK clock periods (default)
Page 719 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 1) MCM = Measurement Core Module Table 372 RESET of ADC2_CTRL2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000401 RESET_TYPE_4 TRIM_2 00000401 RESET Measurement Unit Control Register 4 ADC2_CTRL4 Offset Reset Value...
Page 720 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description FILT_OUT_SEL_8_0 Output Filter Selection for Channels 0 to 8 Each bit enables the IIR filter for the corresponding channel. 0 0000 0000 ADC2 Unfiltered Data can be monitored in the corresponding ADC2_FILT_OUTx Registers, .
Page 721 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:25 Reserved Always read as 0 24:16 rwpt Sequence 1 channel enable The following values can be ored: 0 0000 0001 CH0_EN, Channel 0 enable 0 0000 0010 CH1_EN, Channel 1 enable 0 0000 0100 CH2_EN, Channel 2 enable 0 0000 1000...
Page 722 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) rwpt rwpt Field Bits Type Description 31:25 Reserved Always read as 0 24:16 rwpt Sequence 3 channel enable The following values can be ored: 0 0000 0001 CH0_EN, Channel 0 enable 0 0000 0010 CH1_EN, Channel 1 enable 0 0000 0100 CH2_EN, Channel 2 enable...
Page 723 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Measurement Channel Enable Bits for Sequence 4-5 ADC2_SQ4_5 Offset Reset Value Measurement Channel Enable Bits for Table 376 Sequence 4 - 5 rwpt rwpt Field Bits Type Description 31:25 Reserved Always read as 0 24:16 rwpt Sequence 5 channel enable...
Page 724 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Table 376 RESET of ADC2_SQ4_5 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 012600DE RESET_TYPE_4 TRIM_2 012600DE RESET User Manual Rev. 2.0 2023-08-09...
Page 725 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Measurement Channel Enable Bits for Sequence 6-7 ADC2_SQ6_7 Offset Reset Value Measurement Channel Enable Bits for Table 377 Sequence 6 - 7 rwpt rwpt Field Bits Type Description 31:25 Reserved Always read as 0 24:16 rwpt Sequence 7 channel enable...
Page 726 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Table 377 RESET of ADC2_SQ6_7 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 012600DF RESET_TYPE_4 TRIM_2 012600DF RESET User Manual Rev. 2.0 2023-08-09...
Page 727 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Measurement Channel Enable Bits for Sequence 8 ADC2_SQ8_9 Offset Reset Value Measurement Channel Enable Bits for Table 378 Sequence 8 rwpt Field Bits Type Description 31:9 Reserved Always read as 0 rwpt Sequence 8 channel enable The following values can be ored: 0 0000 0001 CH0_EN, Channel 0 enable...
Page 728 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Sequencer Feedback Register ADC2_SQ_FB Offset Reset Value Sequencer Feedback Register Table 379 EIM_ SQ_S SQ_FB ACT* Field Bits Type Description 31:20 Reserved Always read as 0 19:16 Current active ADC2 Channel (in normal mode) Other bit combinations are reserved, do not use.
Page 729 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description EIM_ACTIVE ADC2 EIM active not active , EIM not active active, EIM active SQ_STOP ADC2 Sequencer Stop Signal for DPP DPP Running, Postprocessing Sequencer in running mode DPP Stopped, Postprocessing Sequencer stopped / Software Mode entered Reserved Always read as 0...
Page 730 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Channel Setting for Exceptional Interrupt Measurement ADC2_CHx_EIM Offset Reset Value Channel Settings Bits for Exceptional Table 380 Interrupt Measurement CHx_SEL Field Bits Type Description 31:13 Reserved Always read as 0 Exceptional interrupt measurement (EIM) Trigger select GPT12PISEL.T3_GPT12_SEL, Signal according to SCU_GPT12PISEL.T3_GPT12SEL setting CP_clk, Charge-pump clock...
Page 731 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description CHx_SEL Channel set for exceptional interrupt measurement (EIM) Other bit combinations are n.u., not used. 0000 CH0_EN, Channel 0 enable 0001 CH1_EN, Channel 1 enable 0010 CH2_EN, Channel 2 enable 0011 CH3_EN, Channel 3 enable 0100...
Page 732 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Maximum Time for Software Mode ADC2_MAX_TIME Offset Reset Value Maximum Time for Software Mode Table 381 MAX_TIME Field Bits Type Description 31:8 Reserved Always read as 0 MAX_TIME Maximum Time in Software Mode Maximum time in Software Mode with the unit of 1 clock cycle (typ.
Page 733: Calibration Unit
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.5 Calibration Unit 23.5.1 Functional Description The calibration unit of the Measurement Core module is dedicated to cancel offset and gain errors out of the signal chain. The upcoming two chapters describe usage and setup of the calibration unit. 23.5.1.1 Method for determining the Calibration Parameters As mentioned in the introduction of the calibration unit, the module can be used to correct gain and offset errors caused by non-idealities in the measurement chain.
Page 734 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Calibration Unit ALU - 16 Bit signed : y = a + (1+b)*x ADC Raw Data à x CALIB_EN ADC - SFR ADC_CALOFFS ADC_CALGAIN ADC_CALIB_ENx Figure 189 Structure of Calibration Unit User Manual Rev.
Page 735: Calibration Unit Control Registers
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.5.2 Calibration Unit Control Registers The Calibration Unit can be configured by the SFR Registers shown below. The registers which cannot be written by the user have the attribute rwpt. Table 382 Register Overview Register Short Name Register Long Name Offset Address...
Page 736 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description OFFS_CH0 rwpt Offset Calibration for channel 0 For ADC output set CALIB_EN_0 = 0 Table 383 RESET of ADC2_CAL_CH0_1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000...
Page 737 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC2 Calibration Value Channel 4 & 5 ADC2_CAL_CH4_5 Offset Reset Value Calibration for Channel 4 & 5 Table 385 GAIN_CH5 OFFS_CH5 rwpt rwpt GAIN_CH4 OFFS_CH4 rwpt rwpt Field Bits Type Description GAIN_CH5 31:24 rwpt Gain Calibration for channel 5 For ADC output set CALIB_EN_5 = 0...
Page 738 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) GAIN_CH7 OFFS_CH7 rwpt rwpt GAIN_CH6 OFFS_CH6 rwpt rwpt Field Bits Type Description GAIN_CH7 31:24 rwpt Gain Calibration for channel 7 For ADC output set CALIB_EN_7 = 0 23:21 Reserved Always read as 0 OFFS_CH7 20:16 rwpt...
Page 739 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:16 Reserved Always read as 0 GAIN_CH8 15:8 rwpt Gain Calibration for channel 8 For ADC output set CALIB_EN_8 = 0 Reserved Always read as 0 OFFS_CH8 rwpt Offset Calibration for channel 8 For ADC output set CALIB_EN_8 = 0 Table 387 RESET of...
Page 740: Iir-Filter
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.6 IIR-Filter 23.6.1 Functional Description To cancel high frequency noise out of the measured signal, every channel of the digital signal includes a first order IIR Filter. The structure of the IIR Filter is shown in the picture below. IIR _Data Calib_Raw_Data IIR-Filter-Structure.vsd...
Page 741: Step Response
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Frequency response of 1st order IIR a = - 0.5 a = - 0.9375 Frequency (Hz) x 10 Phase response of 1st order IIR Frequency (Hz) x 10 Figure 191 IIR filter transfer function for different filter length fl (1MHz corresponds to 1/2*channel sampling frequency) 23.6.1.1 Step Response The IIR filter’s step response time is shown in the figure below:...
Page 742 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Table 388 IIR filter characteristics Filter coefficient Group delay at=ω0 τ[samples] User Manual Rev. 2.0 2023-08-09...
Page 743: Iir Filter Control Registers
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.6.2 IIR Filter Control Registers The IIR Filter can also be configured by the sfr Register shown below. The registers which cannot be written by the user have the attribute rwpt. ADC2_FILT_OUT0 ADC2_FILT_OUT8 registers are 10 bits wide, but the ADC delivers only a resolution of 8 bits.
Page 744 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Filter Coefficients ADC Channel 0-8 ADC2_FILTCOEFF0_8 Offset Reset Value Filter Coefficients ADC Channel 0-8 Table 391 A_CH8 rwpt A_CH7 A_CH6 A_CH5 A_CH4 A_CH3 A_CH2 A_CH1 A_CH0 rwpt rwpt rwpt rwpt rwpt rwpt rwpt rwpt Field Bits...
Page 745 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description A_CH3 rwpt Filter Coefficient A for ADC channel 3 1/2, weight of current sample 1/4, weight of current sample 1/8, weight of current sample 1/16, weight of current sample A_CH2 rwpt Filter Coefficient A for ADC channel 2...
Page 746 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC or Filter Output Channel 0 This register reflects the current value of channel 0 of the measurement chain, which is assigned to VBAT_SENSE measurement. ADC2_FILT_OUT0 Offset Reset Value ADC or Filter Output Channel 0 Table 392 OUT_CH0 Field...
Page 747 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH1 ADC or filter output value channel 1 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[1] = 1 For unfiltered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[1] = 0 Table 393 RESET of ADC2_FILT_OUT1 Register Reset Type...
Page 748 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC or Filter Output Channel 2 ADC2_FILT_OUT2 Offset Reset Value ADC or Filter Output Channel 2 Table 394 OUT_CH2 Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH2 ADC or filter output value channel 2 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[2] = 1 For unfiltered output set...
Page 749 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH3 ADC or filter output value channel 3 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[3] = 1 For unfiltered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[3] = 0 Table 395 RESET of ADC2_FILT_OUT3 Register Reset Type...
Page 750 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC or Filter Output Channel 4 ADC2_FILT_OUT4 Offset Reset Value ADC or Filter Output Channel 4 Table 396 OUT_CH4 Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH4 ADC or filter output value channel 4 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[4] = 1 For unfiltered output set...
Page 751 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH5 ADC or filter output value channel 5 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[5] = 1 For unfiltered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[5] = 0 Table 397 RESET of ADC2_FILT_OUT5 Register Reset Type...
Page 752 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) ADC or Filter Output Channel 7 ADC2_FILT_OUT7 Offset Reset Value ADC or Filter Output Channel 7 Table 399 OUT_CH7 Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH7 ADC or filter output value channel 7 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[7] = 1 For unfiltered output set...
Page 753 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description 31:10 Reserved Always read as 0 OUT_CH8 ADC or filter output value channel 8 For filtered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[8] = 1 For unfiltered output set ADC2_CTRL4.FILT_OUT_SEL_8_0[8] = 0 Table 400 RESET of ADC2_FILT_OUT8 Register Reset Type...
Page 754: Signal Processing
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.7 Signal Processing 23.7.1 Functional Description Upper Ch. X Up counter comparator comparator UPLOEN_ChX CNT_UP_ 3 to 8 TH_UP_CHX stop (1) UP_X_STS CNT_UP_ reset Calib_Raw_Data ADC2_MMODE0_8.MSEL_Chx[1], x=0~8 TH_UP_CHX HYST_UP_CHX UPLOEN_ChX CNT_LO_ 3 to 8 TH_LO_CHX ADC2_FILT_ stop (1)
Page 755 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) a) Range control: ADC2_MMODE0_8.MSEL_Chx=00 (MMODE0), x=0~8, filters/counter disabled overvoltage ADC_OUT undervoltage detection (VBAT) detection THUP_CHx HYST_UP_CHx > 0 HYST_LO_CHx > 0 THLO_CHx time ahb_lo_sts_o[x] time ahb_up_sts_o[x] time b) Overvoltage mode: ADC2_MMODE0_8.MSEL_Chx=10 (MMODEOV), x=0~8, filters/counter disabled ADC_OUT level 2...
Page 756 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Table 401 Register protection for some channels Measurement channel n protection on LOWER registers protection on UPPER registers 0 (VS) 4 (VDDC) 5 (VBG) 6 (VDDP) 7 and 8 (temp. sensors) User Manual Rev.
Page 757: Postprocessing Control Registers
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.7.2 Postprocessing Control Registers The Postprocessing Unit is fully controllable by the below listed sfr Registers. Table 402 Register Overview Register Short Name Register Long Name Offset Address Reset Value Postprocessing Control Registers, ADC2_FILT_UPLO_CTR Upper and Lower Threshold Filter Enable Table 403...
Page 758 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper and Lower Threshold Filter Enable ADC2_FILT_UPLO_CTRL Offset Reset Value Upper and Lower Threshold Filter Enable Table 403 UPLO UPLO UPLO UPLO UPLO UPLO UPLO UPLO UPLO EN_C EN_C EN_C EN_C EN_C EN_C EN_C EN_C EN_C...
Page 759 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description UPLOEN_Ch0 Upper and lower threshold IIR filter enable ch 0 Disable, Enable, Table 403 RESET of ADC2_FILT_UPLO_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 000001FF RESET_TYPE_4 TRIM_2...
Page 760 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description MSEL_Ch6 13:12 rwpt Measurement mode ch 6 MMODE0, upper and lower voltage/limit measurement MMODEUV, undervoltage/-limit measurement MMODEOV, overvoltage/-limit measurement RESERVED, reserved MSEL_Ch5 11:10 rwpt Measurement mode ch 5 MMODE0, upper and lower voltage/limit measurement MMODEUV, undervoltage/-limit measurement MMODEOV, overvoltage/-limit measurement...
Page 761 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Table 404 RESET of ADC2_MMODE0_8 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00028000 RESET_TYPE_4 TRIM_2 00028000 RESET User Manual Rev. 2.0 2023-08-09...
Page 762 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Comparator Trigger Level Channel 0 - 3 ADC2_TH0_3_UPPER Offset Reset Value Upper Comparator Trigger Level Channel 0- Table 405 THUP_CH3 THUP_CH2 THUP_CH1 THUP_CH0 Field Bits Type Description THUP_CH3 31:24 Channel 3 upper trigger level 0, min.
Page 763 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Comparator Trigger Level Channel 4 - 7 ADC2_TH4_7_UPPER Offset Reset Value Upper Comparator Trigger Level Channel 4 - Table 406 THUP_CH7 THUP_CH6 rwpt THUP_CH5 THUP_CH4 rwpt Field Bits Type Description THUP_CH7 31:24 rwpt Channel 7 upper trigger level 0, min.
Page 764 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Comparator Trigger Level Channel 8 ADC2_TH8_11_UPPER Offset Reset Value Upper Comparator Trigger Level Channel 8 Table 407 THUP_CH8 rwpt Field Bits Type Description 31:8 Reserved Always read as 0 THUP_CH8 rwpt Channel 8 upper trigger level 0, min.
Page 765 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Counter Trigger Level Channel 0 - 3 ADC2_CNT0_3_UPPER Offset Reset Value Upper Counter Trigger Level Channel 0 - 3 Table 408 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _CH3 _CH2 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _CH1 _CH0 Field Bits...
Page 766 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description HYST_UP_CH1 12:11 Channel 1 upper hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8 HYST16, hysteresis = 16 Reserved Always read as 0 CNT_UP_CH1 Upper timer trigger threshold channel 1 1 , 1 measurement 2 , 2 measurements 4 , 4 measurements...
Page 767 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Counter Trigger Level Channel 4 to 7 ADC2_CNT4_7_UPPER Offset Reset Value Upper Counter Trigger Level Channel 4 to 7 Table 409 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _CH7 _CH6 rwpt rwpt HYST_UP CNT_UP_ HYST_UP CNT_UP_ _CH5 _CH4...
Page 768 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description HYST_UP_CH5 12:11 rwpt Channel 5 upper hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8 HYST16, hysteresis = 16 Reserved Always read as 0 CNT_UP_CH5 rwpt Upper timer trigger threshold channel 5 1, 1 measurement...
Page 769 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Upper Counter Trigger Level Channel 8 ADC2_CNT8_11_UPPER Offset Reset Value Upper Counter Trigger Level Channel 8 Table 410 HYST_UP CNT_UP_ _CH8 rwpt rwpt Field Bits Type Description 31:5 Reserved Always read as 0 HYST_UP_CH8 rwpt Channel 8 upper hysteresis...
Page 770 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Comparator Trigger Level Channel 0 - 3 ADC2_TH0_3_LOWER Offset Reset Value Lower Comparator Trigger Level Channel 0 - Table 411 THLO_CH3 THLO_CH2 THLO_CH1 THLO_CH0 rwpt Field Bits Type Description THLO_CH3 31:24 Channel 3 lower trigger level 0, Min.
Page 771 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Comparator Trigger Level Channel 4 to 7 ADC2_TH4_7_LOWER Offset Reset Value Lower Comparator Trigger Level Channel 4 Table 412 to 7 THLO_CH7 THLO_CH6 rwpt THLO_CH5 THLO_CH4 rwpt rwpt Field Bits Type Description THLO_CH7 31:24 Channel 7 lower trigger level...
Page 772 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Comparator Trigger Level Channel 8 ADC2_TH8_11_LOWER Offset Reset Value Lower Comparator Trigger Level Channel 8 Table 413 THLO_CH8 Field Bits Type Description 31:8 Reserved Always read as 0 THLO_CH8 Channel 8 lower trigger level 0, Min.
Page 773 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Counter Trigger Level Channel 0 - 3 ADC2_CNT0_3_LOWER Offset Reset Value Lower Counter Trigger Level Channel 0 - 3 Table 414 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _CH3 _CH2 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _CH1 _CH0 rwpt rwpt...
Page 774 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description HYST_LO_CH1 12:11 Channel 1 lower hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8 HYST16, hysteresis = 16 Reserved Always read as 0 CNT_LO_CH1 Lower timer trigger threshold channel 1 1, 1 measurement 2, 2 measurements 4, 4 measurements...
Page 775 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Counter Trigger Level Channel 4 to 7 ADC2_CNT4_7_LOWER Offset Reset Value Lower Counter Trigger Level Channel 4 to 7 Table 415 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _CH7 _CH6 rwpt rwpt HYST_LO CNT_LO_ HYST_LO CNT_LO_ _CH5 _CH4...
Page 776 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Field Bits Type Description HYST_LO_CH5 12:11 rwpt Channel 5 lower hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8 HYST16, hysteresis = 16 Reserved Always read as 0 CNT_LO_CH5 rwpt Lower timer trigger threshold channel 5 1, 1 measurement...
Page 777 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) Lower Counter Trigger Level Channel 8 ADC2_CNT8_11_LOWER Offset Reset Value Lower Counter Trigger Level Channel 8 Table 416 HYST_LO CNT_LO_ _CH8 Field Bits Type Description 31:5 Reserved Always read as 0 HYST_LO_CH8 Channel 8 lower hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8...
Page 778: Start-Up Behavior After Reset
MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 23.8 Start-up Behavior after Reset After the end of a reset phase the measurement sources and the post-processing units need some time for settling. In order to avoid undesired triggering of interrupts until the measurement signal acquisition is in a steady state, the status signals are forced to zero during the start-up phase.
Page 779 MOTIX™ TLE985xQX Measurement Core Module (incl. ADC2) 3) register: HYST_LO_CHx / HYST_UP_CHx; selectable decimal values [0, 4, 8, 16] 4) register: ADC2_FILTCOEFF0_8; selectable decimal values [2, 4, 8, 16] 5) register: CNT_LO_CHx / CNT_UP_CHx; selectable decimal values [2 ...2 User Manual Rev.
Page 780: Analog Digital Converter Adc10B (Adc1)
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Analog Digital Converter ADC10B (ADC1) 24.1 Features The basic function of this block is the digital postprocessing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. The measurement postprocessing block is built of the same number of identical channel units attached to the outputs of the 10-bit ADC.
Page 781: Introduction
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.2 Introduction The basic function of this unit, is the digital signal processing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. The Measurement Core module processes all channels in a quasi parallel process.
Page 782 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) “Software Mode”, Sequencer and Exceptional Interrupt and Sequence Measurement is disabled, each measurement is triggered by software. The IIR filter can be bypassed via ADC1_FILT_UPLO_CTRL The threshold counter can be bypassed (counting only 1 measurement) via CNT_LO_PPx User Manual Rev.
Page 783: Adc1 - Core (10-Bit Adc)
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.3 ADC1 - Core (10-Bit ADC) 24.3.1 Functional Description The different sequencer modes are controlled by SFR Register: • “Normal Sequencer Mode” described in the Chapter Channel Controller. • “Exceptional Interrupt Measurement” (EIM), upon a hardware event , the channel programmed in ADC1_CHx_EIM is inserted after the current measurement is finished.
Page 784: Adc1 Control And Status Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Debug Suspend Mode: During Debug Suspend Mode the Sequencer is stopped once the current measurement is finished (after the next EOC event) and Software Mode is entered. As long as the Debug Suspend Mode is active no measurements are performed by the Sequencer.
Page 785 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Control and Status Register ADC1_CTRL_STS Offset Reset Value ADC1 Control and Status Register Table 420 STRT UP_* CAL_ READ SW_CH_SEL SOOC PD_N SIGN rwh1 rwh1 Field Bits Type Description 31:19 Reserved Always read as 0 STRTUP_DIS DPP1 Startup Disable Startup Enable, DPP1 Startup enabled...
Page 786 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description Reserved Always read as 0 CAL_SIGN Output of Comparator to Steer Gain / Offset calibration READY HVADC Ready bit Not ready, Module in power down or in init phase Ready, set automatically 5 ADC clock cycles after module is enabled Reserved...
Page 787 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Offset Calibration Register ADC1_OFFSETCALIB Offset Reset Value ADC1 Offset Calibration Register Table 421 OFFSET_SHI OFFSET_DAC Field Bits Type Description 31:13 Reserved Always read as 0 OFFSET_DAC 12:8 Set the Value of the Offset Calibration DAC Reserved Always read as 0 OFFSET_SHIFT...
Page 788 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Status Register ADC1_STATUS Offset Reset Value ADC1 Status Register Table 422 SD_F SOC_JIT EED* DAC_IN Field Bits Type Description SD_FEEDB_ON Sigma Delta Feedback Loop Disable, Enable, 30:18 Reserved Always read as 0 SOC_JITTER 17:16 Programs Soc Clock Jitter...
Page 789: Adc - Trigger Unit
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.4 ADC - Trigger Unit The DPP Unit provides also a trigger block. This trigger block provides the following functionality: • “Exceptional Interrupt Measurement” (EIM), upon hardware event , the channel programmed in ADC1_CHx_EIM is inserted after the current measurement is finished.
Page 790: Channel Controller
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.5 Channel Controller 24.5.1 Functional Description The task of each channel controller is a prioritization of the individual measurement channels. The sequencing scheme is illustrated in the example of following table and can be programmed individually for measurement unit.
Page 791 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1)       meas   (24.1) which results in 196 A/D conversion cycles. The average measurement periodicity of channel n in A/D conversion cycles is defined as   ...
Page 792 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Table 424 ADC1 channel mapping (cont’d) P2.0 P2.1 P2.2 P2.3 CH10 CH11 CH12 P2.7 CH13 User Manual Rev. 2.0 2023-08-09...
Page 793: Channel Controller Control Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.5.2 Channel Controller Control Registers The Channel Controller can fully be configured by the SFR Register listed in Table 425. Table 425 Register Overview Register Short Name Register Long Name Offset Address Reset Value Channel Controller Control Registers, ADC1_SQ_FB...
Page 794 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Control Register 2 This register is dedicated for controlling the calibration unit of the measurement core module. The respective channel calibration can be enabled or disabled by the bits listed below. ADC1_CTRL2 Offset Reset Value...
Page 795 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Control Register 3 ADC1_CTRL3 Offset Reset Value Measurement Unit 1 Control Register 3 Table 427 SAMPLE_TIME_L MCM_ EoC_ EoC_ SW_M MCM_ SAMPLE_TIME_HVCH FAIL FAI* PD_N rwhxr Field Bits Type Description 31:20 Reserved Always read as 0...
Page 796 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description SAMPLE_TIME_HVCH 12:8 Sample time of ADC1 Note: the absolute sampling time of a High Voltage Channel should not be choosen lower than 600 ns. Otherwise it is not ensured that the settling time of the input signal is long enough.
Page 797 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description EoC_FAIL rwhxr Fail of ADC End of Conversion Signal ADC EoC available, End of Conversion Signal was sent properly by ADC ADC EoC not available, End of Conversion Signal was not sent properly by ADC Reserved Always read as 0...
Page 798 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Control Register 5 ADC1_CTRL5 Offset Reset Value Measurement Unit 1 Control Register 5 Table 428 FILT_OUT_SEL_13_0 Field Bits Type Description 31:14 Reserved Always read as 0 FILT_OUT_SEL_13_0 13:0 Output Filter Selection for Channels 0 to 13 Each bit enables the IIR filter for the corresponding channel.
Page 799 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 0 - 1 ADC1_SQ0_1 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 429 Cycle 0-1 Field Bits Type Description 31:30 Reserved Always read as 0 29:16 Sequence 1 channel enable Each bit enables the corresponding channel in the sequence 1.
Page 800 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 2 - 3 ADC1_SQ2_3 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 430 Cycle 2-3 Field Bits Type Description 31:30 Reserved Always read as 0 29:16 Sequence 3 channel enable Each bit enables the corresponding channel in the sequence 3.
Page 801 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 4-5 ADC1_SQ4_5 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 431 Cycle 4-5 Field Bits Type Description 31:30 Reserved Always read as 0 29:16 Sequence 5 channel enable Each bit enables the corresponding channel in the sequence 5.
Page 802 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 6-7 ADC1_SQ6_7 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 432 Cycle 6-7 Field Bits Type Description 31:30 Reserved Always read as 0 29:16 Sequence 7 channel enable Each bit enables the corresponding channel in the sequence 7.
Page 803 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 8-9 ADC1_SQ8_9 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 433 Cycle 8-9 Field Bits Type Description 31:30 Reserved Always read as 0 29:16 Sequence 9 channel enable Each bit enables the corresponding channel in the sequence 9.
Page 804 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 10-11 ADC1_SQ10_11 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 434 Cycle 10-11 SQ11 SQ10 Field Bits Type Description 31:30 Reserved Always read as 0 SQ11 29:16 Sequence 11 channel enable...
Page 805 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Channel Enable Bits for Cycle 12-13 ADC1_SQ12_13 Offset Reset Value Measurement Unit 1 Channel Enable Bits for Table 435 Cycle 12-13 SQ13 SQ12 Field Bits Type Description 31:30 Reserved Always read as 0 SQ13 29:16 Sequence 13 channel enable...
Page 806 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Sequencer Feedback Register ADC1_SQ_FB Offset Reset Value Sequencer Feedback Register Table 436 ESM_ EIM_ SQ_S SQ_FB ACT* ACT* Field Bits Type Description 31:20 Reserved Always read as 0 19:16 Current ADC1 Channel Other bit combinations are reserved, do not use. 0000 CH0, Channel 0 enable 0001...
Page 807 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description 14:11 Current Active ADC1 Sequence Other bit combinations are reserved, do not use. 0000 SQ0, Sequence 0 enable 0001 SQ1, Sequence 1 enable 0010 SQ2, Sequence 2 enable 0011 SQ3, Sequence 3 enable 0100 SQ4, Sequence 4 enable...
Page 808 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description SQ_FB Current Sequence that caused software mode 0 0000 SQ0, Sequence 0 enable 0 0001 SQ1, Sequence 1 enable 0 0010 SQ2, Sequence 2 enable 0 0011 SQ3, Sequence 3 enable 0 0100 SQ4, Sequence 4 enable 0 0101...
Page 809 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Channel Setting Bits for Exceptional Interrupt Measurement ADC1_CHx_EIM Offset Reset Value Channel Setting Bits for Exceptional Table 437 Interrupt Measurement ADC1_EIM_T RIG_SEL EIM_ EIM_REP EIM_CHx Field Bits Type Description 31:19 Reserved Always read as 0 ADC1_EIM_T 18:16 Trigger selection for exceptional interrupt measurement (EIM)
Page 810 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description EIM_CHx Channel set for exceptional interrupt measurement (EIM) 0000 CH0_EN, Channel 0 enable 0001 CH1_EN, Channel 1 enable 0010 CH2_EN, Channel 2 enable 0011 CH3_EN, Channel 3 enable 0100 CH4_EN, Channel 4 enable 0101 CH5_EN, Channel 5 enable...
Page 811 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Channel Setting Bits for Exceptional Sequence Measurement ADC1_CHx_ESM Offset Reset Value Channel Setting Bits for Exceptional Table 438 Sequence Measurement ESM_ ESM_ ADC1_ESM_T RIG_SEL ESM_0 Field Bits Type Description ESM_STS Exceptional Sequence Measurement is finished not active, Exceptional Sequence Measurement not done done, Exceptional Sequence Measurement done ESM_EN...
Page 812 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description ESM_0 13:0 Channel Sequence for Exceptional Sequence Measurement (ESM) The following values can be ored: 0001 CH0_EN, Channel 0 enable 0002 CH1_EN, Channel 1 enable 0004 CH2_EN, Channel 2 enable 0008 CH3_EN, Channel 3 enable 0010...
Page 813 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Maximum Time for Software Mode ADC1_MAX_TIME Offset Reset Value Maximum Time for Software Mode Table 439 MAX_TIME Field Bits Type Description 31:8 Reserved Always read as 0 MAX_TIME Maximum Time in Software Mode Maximum time in Software Mode with the unit of 50 ns.
Page 814: Calibration Unit
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.6 Calibration Unit 24.6.1 Functional Description The calibration unit of the Measurement Core module is dedicated to cancel offset and gain errors out of the signal chain. The upcoming two chapter describe usage and setup of the calibration unit. 24.6.1.1 Method for determining the Calibration Parameters As mentioned in the introduction of the calibration unit, the module can be used to correct gain and offset errors caused by non-idealities in the measurement chain.
Page 815 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Calibration Unit ALU - 20 Bit signed : y = a + (1+b)*x ADC Raw Data à x CALIB_EN ADC - SFR ADC_CALOFFS ADC_CALGAIN Figure 197 Structure of Calibration Unit User Manual Rev. 2.0 2023-08-09...
Page 816: Calibration Unit Control Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.6.2 Calibration Unit Control Registers The Calibration Unit can be configured by the SFR Register shown below. All calibration registers can be written by the user. This allows an in-system recalibration of a dedicated measurement. Table 440 Register Overview Register Short Name...
Page 817 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description Reserved Always read as 0 CALOFFS_CH0 rwpw Offset Calibration for channel 0 For ADC output set CALIB_EN_0 = 0 Table 441 RESET of ADC1_CAL_CH0_1 Register Reset Type Reset Values Reset Short Name Reset Mode Note...
Page 818 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 2 & 3 ADC1_CAL_CH2_3 Offset Reset Value Calibration for Channel 2 & 3 Table 442 CALGAIN_CH3 CALOFFS_CH3 rwpw rwpw CALGAIN_CH2 CALOFFS_CH2 rwpw rwpw Field Bits Type Description CALGAIN_CH3 31:24 rwpw...
Page 819 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 4 & 5 ADC1_CAL_CH4_5 Offset Reset Value Calibration for Channel 4 & 5 Table 443 CALGAIN_CH5 CALOFFS_CH5 rwpw rwpw CALGAIN_CH4 CALOFFS_CH4 rwpw rwpw Field Bits Type Description CALGAIN_CH5 31:24 rwpw...
Page 820 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 6 & 7 ADC1_CAL_CH6_7 Offset Reset Value Calibration for Channel 6 & 7 Table 444 CALGAIN_CH7 CALOFFS_CH7 rwpw rwpw CALGAIN_CH6 CALOFFS_CH6 rwpw rwpw Field Bits Type Description CALGAIN_CH7 31:24 rwpw...
Page 821 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 8 & 9 ADC1_CAL_CH8_9 Offset Reset Value Calibration for Channel 8 & 9 Table 445 CALGAIN_CH9 CALOFFS_CH9 rwpw rwpw CALGAIN_CH8 CALOFFS_CH8 rwpw rwpw Field Bits Type Description CALGAIN_CH9 31:24 rwpw...
Page 822 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 10 & 11 ADC1_CAL_CH10_11 Offset Reset Value Calibration for Channel 10 & 11 Table 446 CALGAIN_CH11 CALOFFS_CH11 rwpw rwpw CALGAIN_CH10 CALOFFS_CH10 rwpw rwpw Field Bits Type Description CALGAIN_CH11 31:24 rwpw...
Page 823 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Calibration for Channel 12 & 13 ADC1_CAL_CH12_13 Offset Reset Value Calibration for Channel 12 & 13 Table 447 CALGAIN_CH13 CALOFFS_CH13 rwpw rwpw CALGAIN_CH12 CALOFFS_CH12 rwpw rwpw Field Bits Type Description CALGAIN_CH13 31:24 rwpw...
Page 824: Iir-Filter
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.7 IIR-Filter 24.7.1 Functional Description To cancel low frequency noise out of the measured signal, every channel of the digital signal includes a first order IIR Filter. The structure of the IIR Filter is shown in the picture below. IIR _Data Calib_Raw_Data IIR-Filter-Structure.vsd...
Page 825: Step Response
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 1 – a (1 – a (24.7) Frequency response of 1st order IIR a = - 0.5 a = - 0.9375 Frequency (Hz) x 10 Phase response of 1st order IIR Frequency (Hz) x 10 Figure 199 IIR filter transfer function for different filter length fl (1MHz corresponds to 1/2*channel sampling frequency)
Page 826 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Table 448 summarizes the main filter characteristics. Table 448 IIR filter characteristics Filter coefficient Group delay at=ω0 Normalized -3dB -3dB frequency frequency /2=250 kHz s_ch τ[samples] [Hz] -3dB s_ch -3dB 1) The filter’s - 3dB frequency is normalized to half the channel sampling frequency (Nyquist frequency) User Manual Rev.
Page 827: Iir Filter Control Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.7.2 IIR Filter Control Registers The IIR Filter can also be configured by the sfr Register shown below. ADC1_FILT_OUT0 ADC1_FILT_OUT13 registers are 12 bits wide, but the ADC delivers only a resolution of 10 bits. Bits 1:0 of ADC1_FILT_OUTx contain two bits fractional part (2 ) after calibration and filtering, increasing the resolution to 1/4 LSB.
Page 828 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Table 450 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value ADC1_FILT_OUTEIM ADC1 or Filter Output of EIM Table 467 ADC1_FILT_OUT13 ADC1 or Filter Output Channel 13 Table 465 The registers are addressed wordwise.
Page 829 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description CH10 21:20 Filter Coefficients ADC channel 10 1/2, weight of current sample 1/4, weight of current sample 1/8, weight of current sample 1/16, weight of current sample 19:18 Filter Coefficients ADC channel 9 1/2, weight of current sample 1/4, weight of current sample 1/8, weight of current sample...
Page 830 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description Filter Coefficients ADC channel 1 1/2, weight of current sample 1/4, weight of current sample 1/8, weight of current sample 1/16, weight of current sample Filter Coefficients ADC channel 0 1/2, weight of current sample 1/4, weight of current sample 1/8, weight of current sample...
Page 831 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 0 This registers reflects the current value of channel 0 of the measurement chain, which is assigned to Supply Voltage VS of the system. ADC1_FILT_OUT0 Offset Reset Value ADC1 or Filter Output Channel 0 Table 452 WFR0...
Page 832 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description 15:12 Reserved Always read as 0 FILT_OUT_CH0 11:0 ADC or filter output value channel 0 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH0_EN = 0 Table 452 RESET of ADC1_FILT_OUT0 Register Reset Type Reset Values Reset Short Name Reset Mode...
Page 833 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 1 ADC1_FILT_OUT1 Offset Reset Value ADC1 or Filter Output Channel 1 Table 453 WFR1 FILT_OUT_CH1 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 834 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH1 11:0 ADC or filter output value channel 1 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH1_EN = 0 Table 453 RESET of ADC1_FILT_OUT1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 835 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 2 ADC1_FILT_OUT2 Offset Reset Value ADC1 or Filter Output Channel 2 Table 454 WFR2 FILT_OUT_CH2 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 836 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH2 11:0 ADC or filter output value channel 2 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH2_EN = 0 Table 454 RESET of ADC1_FILT_OUT2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 837 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 3 ADC1_FILT_OUT3 Offset Reset Value ADC1 or Filter Output Channel 3 Table 455 WFR3 FILT_OUT_CH3 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 838 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH3 11:0 ADC or filter output value channel 3 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH3_EN = 0 Table 455 RESET of ADC1_FILT_OUT3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 839 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 4 ADC1_FILT_OUT4 Offset Reset Value ADC1 or Filter Output Channel 4 Table 456 WFR4 FILT_OUT_CH4 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 840 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH4 11:0 ADC or filter output value channel 4 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH4_EN = 0 Table 456 RESET of ADC1_FILT_OUT4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 841 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 5 ADC1_FILT_OUT5 Offset Reset Value ADC1 or Filter Output Channel 5 Table 457 WFR5 FILT_OUT_CH5 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 842 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH5 11:0 ADC or filter output value channel 5 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH5_EN = 0 Table 457 RESET of ADC1_FILT_OUT5 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 843 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 6 ADC1_FILT_OUT6 Offset Reset Value ADC1 or Filter Output Channel 6 Table 458 WFR6 FILT_OUT_CH6 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 844 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH6 11:0 ADC or filter output value channel 6 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH6_EN = 0 Table 458 RESET of ADC1_FILT_OUT6 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 845 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 7 ADC1_FILT_OUT7 Offset Reset Value ADC1 or Filter Output Channel 7 Table 459 WFR7 FILT_OUT_CH7 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 846 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH7 11:0 ADC or filter output value channel 7 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH7_EN = 0 Table 459 RESET of ADC1_FILT_OUT7 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 847 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 8 ADC1_FILT_OUT8 Offset Reset Value ADC1 or Filter Output Channel 8 Table 460 WFR8 FILT_OUT_CH8 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 848 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH8 11:0 ADC or filter output value channel 8 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH8_EN = 0 Table 460 RESET of ADC1_FILT_OUT8 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 849 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 9 ADC1_FILT_OUT9 Offset Reset Value ADC1 or Filter Output Channel 9 Table 461 WFR9 FILT_OUT_CH9 Field Bits Type Description 31:19 Reserved Always read as 0 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 850 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH9 11:0 ADC or filter output value channel 9 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH9_EN = 0 Table 461 RESET of ADC1_FILT_OUT9 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 851 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 10 ADC1_FILT_OUT10 Offset Reset Value ADC1 or Filter Output Channel 10 Table 462 WFR1 OF10 VF10 FILT_OUT_CH10 Field Bits Type Description 31:19 Reserved Always read as 0 OF10 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by...
Page 852 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH10 11:0 ADC or filter output value channel 10 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH10_EN = 0 Table 462 RESET of ADC1_FILT_OUT10 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 853 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 11 ADC1_FILT_OUT11 Offset Reset Value ADC1 or Filter Output Channel 11 Table 463 WFR1 OF11 VF11 FILT_OUT_CH11 Field Bits Type Description 31:19 Reserved Always read as 0 OF11 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by...
Page 854 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH11 11:0 ADC or filter output value channel 11 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH11_EN = 0 Table 463 RESET of ADC1_FILT_OUT11 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 855 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 12 ADC1_FILT_OUT12 Offset Reset Value ADC1 or Filter Output Channel 12 Table 464 WFR1 OF12 VF12 FILT_OUT_CH12 Field Bits Type Description 31:19 Reserved Always read as 0 OF12 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by...
Page 856 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH12 11:0 ADC or filter output value channel 12 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH12_EN = 0 Table 464 RESET of ADC1_FILT_OUT12 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 857 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output Channel 13 ADC1_FILT_OUT13 Offset Reset Value ADC1 or Filter Output Channel 13 Table 465 WFR1 OF13 VF13 FILT_OUT_CH13 Field Bits Type Description 31:19 Reserved Always read as 0 OF13 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by...
Page 858 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FILT_OUT_CH13 11:0 ADC or filter output value channel 13 For ADC output set ADC1_FILT_UPLO_CTRL.FUL_PP_CH13_EN = 0 Table 465 RESET of ADC1_FILT_OUT13 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...
Page 859 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Differential Channel Output 1 ADC1_DIFFCH_OUT1 Offset Reset Value ADC1 Differential Channel Output 1 Table 466 DWFR DOF1 DVF1 DCH1 Field Bits Type Description 31:19 Reserved Always read as 0 DOF1 Overrun Flag Indicates if the result register is overwritten with new content (bit is set if VFx = 1 and new result is updated by hardware.
Page 860 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description DCH1 11:0 ADC differential output value 1 Table 466 RESET of ADC1_DIFFCH_OUT1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0XXX RESET_TYPE_3 Exact reset value: 0000 0000 0000 0000 0000 XXXX XXXX XXXX(binary)
Page 861 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 or Filter Output for EIM Measurement Note: This Channel is not included in the sequencer. EIM Mode uses the postprocessing chain of the selected EIM channel. ADC1_FILT_OUTEIM Offset Reset Value ADC1 or Filter Output of EIM Table 467 OF_E VF_E...
Page 862 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description WFR_EIM Wait for Read Mode Enables wait for read mode for result register DISABLE, overwrite mode ENABLE, wait for read mode enabled 15:12 Reserved Always read as 0 FILT_OUT_EIM 11:0 ADC or filter output value for last EIM measurement Table 467...
Page 863: Signal Processing
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.8 Signal Processing 24.8.1 Functional Description Upper Ch. X up/down counter (integrator) comparator comparator FUL_PP_CHX_EN CNT_UP_ 3 to 8 TH_UP_CHX PP_CHX_UP_STS stop (+1) CNT_UP_ ±1 reset ADC1_MMODE0_11.MMODE_x[0], x=0~11 Calib_Raw_Data PP_CHX_UP HYST_UP_PPX FUL_PP_CHX_EN CNT_LO_ 3 to 8 TH_LO_CHX PP_CHX_LO_STS...
Page 864 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) a) ADC1_MMODE0_11.MMODE_x, x=0~11, [00B] filters/counter disabled overvoltage ADC_OUT undervoltage detection (VBAT) detection PP_CHx_UP HYST_UP_PPx > 0 HYST_LO_PPx > 0 PP_CHx_LOW time PP_CHx_LO_STS time PP_CHx_UP_STS time b) ADC1_MMODE0_11.MMODE_x[1], x=0~11, [10B] filters/counter disabled ADC_OUT level 2 (TEMP) detection level 1...
Page 865: Postprocessing Control Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.8.2 Postprocessing Control Registers The Postprocessing block is fully controllable by the below listed sfr Registers. Table 468 Register Overview Register Short Name Register Long Name Offset Address Reset Value Postprocessing Control Registers, ADC1_TH0_3_LOWER Lower Comparator Trigger Level Post- Table 477...
Page 866 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper And Lower Threshold Filter Enable ADC1_FILT_UPLO_CTRL Offset Reset Value Upper And Lower Threshold Filter Enable Table 469 FUL_ FUL_ FUL_ FUL_ FUL_ FUL_ FUL_ FUL_ PP_C PP_C PP_C PP_C PP_C PP_C PP_C PP_C H7_* H6_*...
Page 867 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description FUL_PP_CH1_EN Upper and lower threshold IIR filter enable Post- Processing-Channel 1 Disable, Enable, FUL_PP_CH0_EN Upper and lower threshold IIR filter enable Post- Processing-Channel 0 Disable, Enable, Table 469 RESET of ADC1_FILT_UPLO_CTRL Register Reset Type Reset Values...
Page 868 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description MMODE_7 15:14 Measurement mode Post-Processing-Channel 7 MMODE0, upper and lower voltage/limit measurement MMODEUV, undervoltage/-limit measurement MMODEOV, overvoltage/-limit measurement RESERVED, reserved MMODE_6 13:12 Measurement mode Post-Processing-Channel 6 MMODE0, upper and lower voltage/limit measurement MMODEUV, undervoltage/-limit measurement MMODEOV, overvoltage/-limit measurement...
Page 869 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description MMODE_0 Measurement mode Post-Processing-Channel 0 MMODE0, upper and lower voltage/limit measurement MMODEUV, undervoltage/-limit measurement MMODEOV, overvoltage/-limit measurement RESERVED, reserved Table 470 RESET of ADC1_MMODE0_7 Register Reset Type Reset Values Reset Short Name Reset Mode Note...
Page 870 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Comparator Trigger Level Post-Processing-Channel 0-3 ADC1_TH0_3_UPPER Offset Reset Value Upper Comparator Trigger Level Post- Table 471 Processing-Channel 0-3 PP_CH3_UP PP_CH2_UP PP_CH1_UP PP_CH0_UP Field Bits Type Description PP_CH3_UP 31:24 Post-Processing-Channel 3 upper trigger level 0, min.
Page 871 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Comparator Trigger Level Post-Processing-Channel 4-7 ADC1_TH4_7_UPPER Offset Reset Value Upper Comparator Trigger Level Post- Table 472 Processing-Channel 4-7 PP_CH7_UP PP_CH6_UP PP_CH5_UP PP_CH4_UP Field Bits Type Description PP_CH7_UP 31:24 Post-Processing-Channel 7 upper trigger level 0, min.
Page 872 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Comparator Trigger Level Differential Channel 1 ADC1_DCHTH1_4_UPPER Offset Reset Value Upper Comparator Trigger Level Differential Table 473 Channel 1 DCH1_UP Field Bits Type Description 31:8 Reserved Always read as 0 DCH1_UP Differential Channel 1 upper trigger level 0, min.
Page 873 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Counter Trigger Level Post-Processing-Channel 0-3 ADC1_CNT0_3_UPPER Offset Reset Value Upper Counter Trigger Level Post- Table 474 Processing-Channel 0-3 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _PP3 _PP2 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _PP1 _PP0 Field Bits Type Description 31:29...
Page 874 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description CNT_UP_PP2 17:16 Upper timer trigger threshold Post-Processing-Channel 1, 1 measurement 2, 2 measurements 4, 4 measurements 7, 7 measurements 15:13 Reserved Always read as 0 HYST_UP_PP1 12:11 Post-Processing-Channel 1 upper hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8...
Page 875 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Counter Trigger Level Post-Processing-Channel 4-7 ADC1_CNT4_7_UPPER Offset Reset Value Upper Counter Trigger Level Post- Table 475 Processing-Channel 4-7 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _PP7 _PP6 HYST_UP CNT_UP_ HYST_UP CNT_UP_ _PP5 _PP4 Field Bits Type Description 31:29...
Page 876 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description CNT_UP_PP6 17:16 Upper timer trigger threshold Post-Processing-Channel 1, 1 measurement 2, 2 measurements 4, 4 measurements 7, 7 measurements 15:13 Reserved Always read as 0 HYST_UP_PP5 12:11 Post-Processing-Channel 5 upper hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8...
Page 877 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Upper Counter Trigger Level Differential Channel 1 ADC1_DCHCNT1_4_UPPER Offset Reset Value Upper Counter Trigger Level Differential Table 476 Channel 1 HYST_UP CNT_UP_ _DCH1 DCH1 Field Bits Type Description 31:5 Reserved Always read as 0 HYST_UP_DCH1 Differential Channel 1 upper hysteresis HYSTOFF, hysteresis switched off...
Page 878 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Comparator Trigger Level Post-Processing-Channel 0-3 ADC1_TH0_3_LOWER Offset Reset Value Lower Comparator Trigger Level Post- Table 477 Processing-Channel 0-3 PP_CH3_LOW PP_CH2_LOW PP_CH1_LOW PP_CH0_LOW Field Bits Type Description PP_CH3_LOW 31:24 Post-Processing-Channel 3 lower trigger level 0, Min.
Page 879 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Comparator Trigger Level Post-Processing-Channel 4-7 ADC1_TH4_7_LOWER Offset Reset Value Lower Comparator Trigger Level Post- Table 478 Processing-Channel 4-7 PP_CH7_LOW PP_CH6_LOW PP_CH5_LOW PP_CH4_LOW Field Bits Type Description PP_CH7_LOW 31:24 Post-Processing-Channel 7 lower trigger level 0, Min.
Page 880 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Comparator Trigger Level Differential Channel 1 ADC1_DCHTH1_4_LOWER Offset Reset Value Lower Comparator Trigger Level Table 479 Differential Channel 1 DCH1_LOW Field Bits Type Description 31:8 Reserved Always read as 0 DCH1_LOW Differential Channel 1 lower trigger level 0, Min.
Page 881 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Counter Trigger Level Post-Processing-Channel 0-3 ADC1_CNT0_3_LOWER Offset Reset Value Lower Counter Trigger Level Post- Table 480 Processing-Channel 0-3 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _PP3 _PP2 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _PP1 _PP0 Field Bits Type Description 31:29...
Page 882 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description CNT_LO_PP2 17:16 Lower timer trigger threshold Post-Processing-Channel 1, 1 measurement 2, 2 measurements 4, 4 measurements 7, 7 measurements 15:13 Reserved Always read as 0 HYST_LO_PP1 12:11 Post-Processing-Channel 1 lower hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8...
Page 883 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Counter Trigger Level Post-Processing-Channel 4-7 ADC1_CNT4_7_LOWER Offset Reset Value Lower Counter Trigger Level Post- Table 481 Processing-Channel 4-7 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _PP7 _PP6 HYST_LO CNT_LO_ HYST_LO CNT_LO_ _PP5 _PP4 Field Bits Type Description 31:29...
Page 884 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description CNT_LO_PP6 17:16 Lower timer trigger threshold Post-Processing-Channel 1, 1 measurement 2, 2 measurements 4, 4 measurements 7, 7 measurements 15:13 Reserved Always read as 0 HYST_LO_PP5 12:11 Post-Processing-Channel 5 lower hysteresis HYSTOFF, hysteresis switched off HYST4, hysteresis = 4 HYST8, hysteresis = 8...
Page 885 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Lower Counter Trigger Level Differential Channel 1 ADC1_DCHCNT1_4_LOWER Offset Reset Value Lower Counter Trigger Level Differential Table 482 Channel 1 HYST_LO CNT_LO_ _DCH1 DCH1 Field Bits Type Description 31:5 Reserved Always read as 0 HYST_LO_DCH1 Differential Channel 1 lower hysteresis HYSTOFF, hysteresis switched off...
Page 886 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Post-Processing Mapping Channel 0-3 ADC1_PP_MAP0_3 Offset Reset Value Post-Processing Mapping Channel 0-3 Table 483 EN_P RESE EN_P RESE PP_MAP3 PP_MAP2 P_M* T_P* P_M* T_P* EN_P RESE EN_P RESE P_M* T_P* P_M* T_P* Field Bits Type Description...
Page 887 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_MAP2 19:16 Mapping of Entry Channel to Post-Processing-Channel 2 Ch0, Entry Channel 0 Ch13, Entry Channel 13 Reserved, Reserved, EN_PP_MAP1 Mapping Enable for Post-Processing-Channel 1 Enable/disable the triggering of the post processing channel 1 Disabled, Mapping Disabled Enabled, Mapping Enabled...
Page 888 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Post-Processing Mapping Channel 4-7 ADC1_PP_MAP4_7 Offset Reset Value Post-Processing Mapping Channel 4-7 Table 484 EN_P RESE EN_P RESE PP_MAP7 PP_MAP6 P_M* T_P* P_M* T_P* EN_P RESE EN_P RESE PP_MAP5 PP_MAP4 P_M* T_P* P_M* T_P* Field Bits...
Page 889 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_MAP6 19:16 Mapping of Entry Channel to Post-Processing-Channel 6 Ch0, Entry Channel 0 Ch13, Entry Channel 13 Reserved, Reserved, EN_PP_MAP5 Mapping Enable for Post-Processing-Channel 5 Enable/disable the triggering of the post processing channel 5 Disabled, Mapping Disabled Enabled, Mapping Enabled...
Page 890: Interrupt Handling
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.9 Interrupt Handling 24.9.1 Functional Description Figure 204 shows the interrupt generation of ADC1.The generated interrupts are assigned to several nodes. The exact mapping can be red in the corresponding interrupt chapter of this device. Note: all status flags and interrupt status flags are blanked within the startup procedure of the sequencer.
Page 891 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_PP_MAPx.PP_MAPx Decode VBAT_SENSE CH 0 ADC1_IRQEN_2.PP_CH0_UP/LO_IEN CH 1 mon_int p2x_int MON1 CH 2 PP_CH0_UP/LO csa_int MON2 CH 3 MON3 CH 4 ADC1_IRQEN_2.PP_CH1_UP/LO_IEN MON4 CH 5 mon_int p2x_int P2.0/P2.8 CH 6 PP_CH2_UP/LO csa_int P2.1 CH 7 .
Page 892 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_IRQEN_1.IIR_CH0_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH0_IS Control ADC1_IRQCLR_1.IIR_CH0_ISC ADC1_IRQEN_1.VS_IEN ADC1 Interrupt ADC1_IRQS_1.VS_IS Control ADC1_IRQCLR_1.VS_ISC ADC1_IRQEN_1.IIR_CH2_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH2_IS Control ADC1_IRQCLR_1.IIR_CH2_ISC ADC1_IRQEN_1.IIR_CH3_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH3_IS Control ADC1_IRQCLR_1.IIR_CH3_ISC ADC1_IRQEN_1.IIR_CH4_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH4_IS Control ADC1_IRQCLR_1.IIR_CH4_ISC ADC1_IRQEN_1.IIR_CH5_IEN ADC1 Interrupt ADC1_IRQS_1.IIR_CH5_IS Control ADC1_IRQCLR_1.IIR_CH5_ISC...
Page 893 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_PP_MAPx.PP_MAPx ADC1_IRQEN_2.PP_CH0_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_UP_IS Control ADC1_IRQCLR_2.PP_CH0_UP_ISC PP_CH0 assigned to MON ADC1_IRQEN_2.PP_CH0_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_LO_IS Control ADC1_IRQCLR_2.PP_CH0_LO_ISC PP_CH0 assigned to MON ADC1_IRQEN_2.PP_CH2_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_UP_IS Control ADC1_IRQCLR_2.PP_CH2_UP_ISC PP_CH2 assigned to MON ADC1_IRQEN_2.PP_CH2_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_LO_IS Control ADC1_IRQCLR_2.PP_CH2_LO_ISC...
Page 894 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_PP_MAPx.PP_MAPx ADC1_IRQEN_2.PP_CH0_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_UP_IS Control ADC1_IRQCLR_2.PP_CH0_UP_ISC PP_CH0 assigned to P2.x ADC1_IRQEN_2.PP_CH0_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_LO_IS Control ADC1_IRQCLR_2.PP_CH0_LO_ISC PP_CH0 assigned to P2.x ADC1_IRQEN_2.PP_CH2_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_UP_IS Control ADC1_IRQCLR_2.PP_CH2_UP_ISC PP_CH2 assigned to P2.x ADC1_IRQEN_2.PP_CH2_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_LO_IS Control ADC1_IRQCLR_2.PP_CH2_LO_ISC...
Page 895 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_PP_MAPx.PP_MAPx ADC1_IRQEN_2.PP_CH0_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_UP_IS Control ADC1_IRQCLR_2.PP_CH0_UP_ISC PP_CH0 assigned to CSA ADC1_IRQEN_2.PP_CH0_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH0_LO_IS Control ADC1_IRQCLR_2.PP_CH0_LO_ISC PP_CH0 assigned to CSA ADC1_IRQEN_2.PP_CH2_UP_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_UP_IS Control ADC1_IRQCLR_2.PP_CH2_UP_ISC PP_CH2 assigned to CSA ADC1_IRQEN_2.PP_CH2_LO_IEN ADC1 Interrupt ADC1_IRQS_2.PP_CH2_LO_IS Control ADC1_IRQCLR_2.PP_CH2_LO_ISC...
Page 896 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1_IRQEN_1.DU1_UP_IEN ADC1 Interrupt ADC1_IRQS_1.DU1_UP_IS Control ADC1_IRQCLR_1.DU1_UP_ISC adc10_dunit_int_o >=1 ADC1_IRQEN_1.DU1_LO_IEN ADC1 Interrupt ADC1_IRQS_1.DU1_LO_IS Control ADC1_IRQCLR_1.DU1_LO_ISC Figure 208 ADC1 Interrupt Generation for Differential Unit User Manual Rev. 2.0 2023-08-09...
Page 897: Interrupt Registers
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.9.2 Interrupt Registers Table 485 Register Overview Register Short Name Register Long Name Offset Address Reset Value Interrupt Registers, ADC1_IRQS_1 ADC1 Interrupt Status 1 Register Table 486 ADC1_IRQEN_1 ADC1 Interrupt Enable 1 Register Table 491 ADC1_IRQCLR_1 ADC1 Interrupt Status Clear 1 Register...
Page 898 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Interrupt Status 1 Register ADC1_IRQS_1 Offset Reset Value ADC1 Interrupt Status 1 Register Table 486 DU1U DU1L ESM_ EIM_ P_IS O_IS rwhxre rwhxre rwhxre rwhxre IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_...
Page 899 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description IIR_CH12_IS rwhxre ADC1 IIR-Filter-Channel 12 Interrupt Status Conversion of Channel has finished INACTIVE, No Channel 12 Interrupt has occurred ACTIVE, Channel 12 Interrupt has occurred IIR_CH11_IS rwhxre ADC1 IIR-Filter-Channel 11 Interrupt Status Conversion of Channel has finished INACTIVE, No Channel 11 Interrupt has occurred ACTIVE, Channel 11 Interrupt has occurred...
Page 900 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description VS_IS rwhxre ADC1 IIR-Filter-Channel 1 Interrupt Status Conversion of Channel has finished INACTIVE, No Channel 1 Interrupt has occurred ACTIVE, Channel 1 Interrupt has occurred IIR_CH0_IS rwhxre ADC1 IIR-Filter-Channel 0 Interrupt Status Conversion of Channel has finished INACTIVE, No Channel 0 Interrupt has occurred ACTIVE, Channel 0 Interrupt has occurred...
Page 901 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Status 2 Register ADC1_IRQS_2 Offset Reset Value ADC1 Interrupt Status 2 Register Table 487 PP_C PP_C PP_C PP_C PP_C PP_C VS_U PP_C H7_* H6_* H5_* H4_* H3_* H2_* P_IS H0_* rwhxre rwhxre rwhxre...
Page 902 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_CH0_UP_IS rwhxre ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status INACTIVE, no interrupt has occurred ACTIVE, interrupt has occurred 15:8 Reserved Always read as 0 PP_CH7_LO_IS rwhxre ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status INACTIVE, no interrupt has occurred ACTIVE, interrupt has occurred...
Page 903 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Status 2 Register ADC1_STS_2 Offset Reset Value ADC1 Status 2 Register Table 488 PP_C PP_C PP_C PP_C PP_C PP_C VS_U PP_C H7_* H6_* H5_* H4_* H3_* H2_* P_S* H0_* PP_C PP_C PP_C PP_C...
Page 904 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_CH0_UP_STS ADC1 Post-Processing-Channel 0 Upper Threshold Status Below limit, Status below upper threshold Above limit, Upper threshold exceeded 15:8 Reserved Always read as 0 PP_CH7_LO_STS ADC1 Post-Processing-Channel 7 Lower Threshold Status Below limit, Status below upper threshold Above limit, Upper threshold exceeded...
Page 905 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Interrupt Status Clear 1 Register ADC1_IRQCLR_1 Offset Reset Value ADC1 Interrupt Status Clear 1 Register Table 489 DU1U DU1L ESM_ EIM_ P_I* O_I* IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_...
Page 906 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description IIR_CH10_ISC ADC1 IIR-Filter-Channel 10 Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared ACTIVE, interrupt status is cleared IIR_CH9_ISC ADC1 IIR-Filter-Channel 9 Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared ACTIVE, interrupt status is cleared...
Page 907 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Table 489 RESET of ADC1_IRQCLR_1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000 RESET_TYPE_3 User Manual Rev. 2.0 2023-08-09...
Page 908 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Interrupt Status Clear 2 Register ADC1_IRQCLR_2 Offset Reset Value ADC1 Interrupt Status Clear 2 Register Table 490 PP_C PP_C PP_C PP_C PP_C PP_C VS_U PP_C H7_* H6_* H5_* H4_* H3_* H2_* P_I* H0_*...
Page 909 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_CH2_UP_ISC ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared ACTIVE, interrupt status is cleared VS_UP_ISC ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared...
Page 910 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_CH2_LO_ISC ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared ACTIVE, interrupt status is cleared VS_LO_ISC ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status Clear Interrupt status is cleared INACTIVE, interrupt status is not cleared...
Page 911 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Interrupt Enable 1 Register ADC1_IRQEN_1 Offset Reset Value ADC1 Interrupt Enable 1 Register Table 491 DU1U DU1L ESM_ EIM_ P_I* O_I* IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ IIR_ VS_I IIR_...
Page 912 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description IIR_CH10_IEN ADC1 IIR-Filter-Channel 10 Interrupt Enable DISABLED , Interrupt disabled ENABLED , Interrupt enabled IIR_CH9_IEN ADC1 IIR-Filter-Channel 9 Interrupt Enable DISABLED , Interrupt disabled ENABLED , Interrupt enabled IIR_CH8_IEN ADC1 IIR-Filter-Channel 8 Interrupt Enable DISABLED , Interrupt disabled ENABLED , Interrupt enabled...
Page 913 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) ADC1 Interrupt Enable 2 Register ADC1_IRQEN_2 Offset Reset Value ADC1 Interrupt Enable 2 Register Table 492 PP_C PP_C PP_C PP_C PP_C PP_C VS_U PP_C H7_* H6_* H5_* H4_* H3_* H2_* P_I* H0_* PP_C PP_C PP_C PP_C...
Page 914 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Field Bits Type Description PP_CH0_UP_IEN ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Enable DISABLED , Interrupt disabled ENABLED , Interrupt enabled 15:8 Reserved Always read as 0 PP_CH7_LO_IEN ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Enable DISABLED , Interrupt disabled ENABLED , Interrupt enabled PP_CH6_LO_IEN...
Page 915 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Status 1Register ADC1_STS_1 Offset Reset Value ADC1 Status 1Register Table 493 DU1U DU1L P_S* O_S* rwhxr rwhxr Field Bits Type Description 31:26 Reserved Always read as 0 DU1UP_STS rwhxr ADC1 Differential Unit 1 (DU1) upper Channel Status Conversion of Channel has finished INACTIVE, No DU upper Channel Status has occurred...
Page 916 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 Status Clear 1 Register ADC1_STSCLR_1 Offset Reset Value ADC1 Status Clear 1 Register Table 494 DU1U DU1L P_SC O_SC Field Bits Type Description 31:26 Reserved Always read as 0 DU1UP_SC ADC1 Differential Unit 1 (DU1) upper Channel Status Clear Conversion of Channel has finished...
Page 917: Differential Measurement Unit
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.10 Differential Measurement Unit 24.10.1 Motivation for Differential Measurement Unit Rev. Polarit y Protection PF ILT VBAT PF ILT1 PF ILT1 EMC Filter VDDP2 VDD P1 VDD C1 VDDC2 VDDP VDDC R P2 CP1H C PS1 CP1L...
Page 918 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) MUX_SEL<4:0> Channel Controller (Sequencer) ADC - SFR ADC1_CTRL_STS ADC1_CTRL_STS ADC1_FILTOUT... n.u. n.u. / 12 MON1 MON2 ADC_OUT_CHx ADC_OUT_CHx n.u. n.u. 10 Bit ADC VREF DU1_UP_STS + / - n.u. Calibration Unit : TH_UP_CHx n.u.
Page 919: Adc1 Differential Unit Input Selection Register
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.10.3 ADC1 Differential Unit Input Selection Register Table 495 Register Overview Register Short Name Register Long Name Offset Address Reset Value ADC1 Differential Unit Input Selection Register, ADC1_DUIN_SEL Measurement Unit 1 - Differential Unit Input Table 496 Selection Register The registers are addressed wordwise.
Page 920 MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) Measurement Unit 1 - Differential Unit Input Selection Register ADC1_DUIN_SEL Offset Reset Value Measurement Unit 1 - Differential Unit Input Table 496 Selection Register DU1R DU1_ ES_* Field Bits Type Description 31:5 Reserved Always read as 0 DU1RES_NEG Differential Unit 1 result negative...
Page 921: Start-Up Behavior After Reset
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.11 Start-up behavior after reset After the end of a reset phase the measurement sources and the post-processing units need some time for settling. In order to avoid undesired triggering of interrupts until the measurement signal acquisition is in a steady state, the status signals are forced to zero during the start-up phase.
Page 922: Postprocessing Default Values
MOTIX™ TLE985xQX Analog Digital Converter ADC10B (ADC1) 24.12 Postprocessing Default Values The following table shows the assigned measurements of the particular channels and the reset default values which are read by FW during power-up. Since all channels are configurable by the user, the reset values can be reconfigured by writting the corresponding sfrs.
Page 923: High-Voltage Monitor Input
MOTIX™ TLE985xQX High-Voltage Monitor Input High-Voltage Monitor Input 25.1 Features • Four High-voltage inputs with VS/2 threshold voltage • Wake capability for system stop mode and system sleep mode • Edge sensitive wake-up feature configurable for transitions from low to high, high to low or both directions •...
Page 924: Functional Description
MOTIX™ TLE985xQX High-Voltage Monitor Input 25.2.2 Functional Description For a wake-up on a positive voltage transition, the MONx_RISE bit has to be configured. For a wake-up on a negative voltage transition, the corresponding bit MONx_FALL has to be set. This configuration can also be used for an edge detection in active mode.
Page 925 MOTIX™ TLE985xQX High-Voltage Monitor Input The following tables provides an overview of the configuration possibilities on the MON_INs via XSFR. Table 498 includes all pull-up and pull-down setup scenarios which can be chosen for one MONx. Table 499 shows an overview of the available states of a MONx. Table 498 Pull-Up / Pull-Down Input Current MONx_PU...
Page 926: Register Definition
MOTIX™ TLE985xQX High-Voltage Monitor Input 25.3 Register Definition This chapter describes the configuration registers for MON1-MON4. Table 500 Register Address Space for PMU Registers Module Base Address End Address Note 50004000 50004FFF Power Management Unit Registers Table 501 Register Overview Register Short Name Register Long Name Offset Address...
Page 927 MOTIX™ TLE985xQX High-Voltage Monitor Input Field Bits Type Description MON4_STS MON4 Status Input Note: the MON4 Status Input Bit is also updated in active mode of the device, when the HV MON4 input status changes. The user has to clear this flag before entering power saving modes otherwise the device will stay in active.
Page 928 MOTIX™ TLE985xQX High-Voltage Monitor Input Field Bits Type Description MON4_FALL MON4 Wake-up on Falling Edge Enable Note: Can only be enabled if MON4_EN is set. During reconfiguration of this bit, wake-up events can be lost. Disable, Wake-up disabled Enable, Wake-up enabled MON4_EN MON4 Enable Disable, MON4 disabled...
Page 929 MOTIX™ TLE985xQX High-Voltage Monitor Input Field Bits Type Description MON3_RISE MON3 Wake-up on Rising Edge Enable Note: Can only be enabled if MON3_EN is set. During reconfiguration of this bit, wake-up events can be lost. Disable, Wake-up disabled Enable, Wake-up enabled MON3_FALL MON3 Wake-up on Falling Edge Enable Note:...
Page 930 MOTIX™ TLE985xQX High-Voltage Monitor Input Field Bits Type Description MON2_CYC MON2 for Cycle Sense Enable Note: Can only be enabled if MON2_EN is set. During reconfiguration of this bit, wake-up events can be lost. Disable, Cycle Sense disabled Enable, Cycle Sense enabled MON2_RISE MON2 Wake-up on Rising Edge Enable Note:...
Page 931 MOTIX™ TLE985xQX High-Voltage Monitor Input Field Bits Type Description MON1_PD Pull-Down Current Source for MON1 Input Enable Note: Can only be enabled if MON1_EN is set. Disable, Pull-down source disabled Enable, Pull-down source enabled MON1_CYC MON1 for Cycle Sense Enable Note: Can only be enabled if MON1_EN is set.
Page 932: High-Side Switch
MOTIX™ TLE985xQX High-Side Switch High-Side Switch 26.1 Features The high-side switch is optimized for driving resistive loads. Only small line inductances are allowed. Typical applications are single or multiple LEDs of a dashboard, switch illumination or other loads that require a high- side switch.
Page 933: Introduction
MOTIX™ TLE985xQX High-Side Switch 26.2 Introduction 26.2.1 Block Diagram 25 mA 50 mA OC_SEL OC-Detection 100 mA 150 mA Cyclic- Driver Driver OL-Detection High Side Figure 213 High-Side Module Block Diagram (incl. subblocks) 26.2.2 General The high-side switch can generally be controlled in three different ways: •...
Page 934: Slew Rate Configuration
MOTIX™ TLE985xQX High-Side Switch • selectable Slew Rate Control for improved EMI behavior. • Overcurrent Detection with four different thresholds (min.): 26 mA, 51 mA, 101 mA and 151 mA. • Overtemperature Protection, to protect the switch against overtemperature. • On-State Open Load Detection with threshold lower than 1.4 mA typ .
Page 935: Pwm Operation
MOTIX™ TLE985xQX High-Side Switch 26.3.2 PWM Operation In PWM mode the high-side switch has to be first enabled by the corresponding bit in the HSx_CTRL register. The related bit is described below. SCU_PM HS_ON & ≥1 HS_PWM & PWM_CHx CCU6 Figure 214 Combinatorial Control of High-Side Switch in PWM Mode To avoid any output glitches on the HSx output, the HSx_PWM bit should be set first.
Page 936: Register Definition
MOTIX™ TLE985xQX High-Side Switch 26.4 Register Definition This chapter describes all necessary registers to control the high-side module and monitor its operation status. Table 503 Register Address Space Module Base Address End Address Note 40024000 40027FFF High-Side Switch Table 504 Register Overview Register Short Name Register Long Name...
Page 937 MOTIX™ TLE985xQX High-Side Switch Field Bits Type Description 31:14 Reserved Always read as 0 HS1_OC_SEL 13:12 High Side 1 Overcurrent Threshold Selection IOCTH0, 26 mA min. IOCTH1, 51 mA min. IOCTH2, 101 mA min. IOCTH3, 151 mA min. 11:10 Reserved Always read as 0 HS1_SR_CTRL_SEL High Side 1 Slew Rate Control select...
Page 938 MOTIX™ TLE985xQX High-Side Switch HS1_ HS1_ HS1_ HS1_ HS1_ OL_* OT_* OC_* OL_* OT_* rwhxr rwhxr rwhxr rwhxre rwhxre Field Bits Type Description 31:15 Reserved Always read as 0 HS1_OL_STS rwhxr High Side 1 Open Load Status no Open Load, no open load Condition occurred. Open Load, open load occurred;...
Page 939 MOTIX™ TLE985xQX High-Side Switch High-Side Interrupt Status Register Clear Register HS_IRQCLR Offset Reset Value High Side Driver Interrupt Status Clear Table 507 Register HS1_ HS1_ HS1_ HS1_ HS1_ OL_* OT_* OC_* OL_* OT_* Field Bits Type Description 31:15 Reserved Always read as 0 HS1_OL_SC High Side 1 Open Load Status Clear no Clear,...
Page 940 MOTIX™ TLE985xQX High-Side Switch High-Side Interrupt Enable Register HS_IRQEN Offset Reset Value High Side Driver Interrupt Enable Register Table 508 HS1_ HS1_ HS1_ OC_* OL_* OT_* Field Bits Type Description 31:8 Reserved Always read as 0 HS1_OC_IEN High Side 1 Overcurrent Interrupt Enable disable, enable, HS1_OL_IEN...
Page 941 MOTIX™ TLE985xQX High-Side Switch HS1_SRC_SE Field Bits Type Description 31:6 Reserved Always read as 0 HS1_SRC_SEL HS1 PWM Source Selection Note: Can only be written when HS_CTRL.HS1_PWM = 0 CC60, PWM output of CCU6 CC61, PWM output of CCU6 CC62, PWM output of CCU6 COUT60, PWM output of CCU6 COUT61, PWM output of CCU6 COUT62, PWM output of CCU6...
Page 942: Interrupt Generation - And Status Bit Logic
MOTIX™ TLE985xQX High-Side Switch Field Bits Type Description 31:28 Reserved Always read as 0 27:24 Reserved Always read as 0 23:22 Reserved Always read as 0 21:19 Reserved Always read as 0 18:16 Reserved Always read as 0 15:14 Reserved Always read as 0 13:10 Reserved...
Page 943: Application Information
MOTIX™ TLE985xQX High-Side Switch overtemperature status of the overtemperature condition can then still be monitored in the dedicated status register, which is placed in the same interrupt status register. Open Load detection: the open load detection interrupt flag is an edge sensitive interrupt flag. This flag is set when the open condition occurs, but can be cleared immediately.
Page 944: Bridge Driver (Incl. Charge Pump)
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Bridge Driver (incl. Charge Pump) 27.1 Features The Bridge Driver is intended to drive external normal-level MOSFETs in bridge configuration and provides many diagnostic possibilities to detect faults. Functional Features • Flexible control by SFRs of Bridge Driver module or PWM output signals of CCU6 module •...
Page 945: Introduction
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.2 Introduction 27.2.1 Block Diagram CP1H CP1L CP2H CP2L PWM-Unit 2-Stage CCU6 Charge Pump (not part of the module) Pre-Driver BDRV_TRIM_DRVx. BDRV_TRIM_DRVx. BDRV_CTRL3. HSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL DSMONVTH Spike Blank High Side Filt er Filter Driver GG ND BDRV_CTRL1.HSx_PWM...
Page 946: Current-Driven Output Stages
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.2.3 Current-Driven Output Stages The Bridge Driver output stages generate source and sink currents to charge and discharge the gates of the external n-channel MOSFETs. The gate current values are programmable to vary the slew rate at the bridge output.
Page 947: Switch-On
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) • post-charge subphase: the gate of the external MOSFET is post-charged until the maximum V the gate driver is able to provide; the external MOSFET is on and its R decreases to its minimum value DS(on) Subphases of the discharging phase: •...
Page 948: Switch-Off
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.2.3.3 Switch-Off Figure 220 shows the detailed behavior of the gate driver output stage in the switch-off phase and the corresponding electrical characteristic parameters. Control Signal ≠ 0, V >V off _SHx off_SHx GS(off ) dly(off ) rise(off )
Page 949 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) • In sequencer mode an advanced gate current profile is defined by SFRs where the gate charging phase and the gate discharging phase each are split into consecutive sub phases with individual current set point values and duration values (see Figure 221):...
Page 950: Adjustable Cross-Conduction Protection
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Gate Current Set Point Gate Current Duration set(seq) max. typ. Gate Current min. Profile gate max. typ. min. max. typ. set(seq) min. Figure 222 Gate current settling time 27.2.4 Adjustable Cross-Conduction Protection The Bridge Driver protects half bridges of external MOSFETs against cross conduction. After switching off one of the MOSFETs of a half bridge the complementary MOSFET cannot be switched on for an optionally programmable time defined by SFRs.
Page 951: Brake Mode
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.2.7 Brake Mode In Brake Mode either both external high-side MOSFETs or both external low-side MOSFETs are statically switched on to short circuit the motor coil to brake the motor or keep it actively blocked during standstill. Since in brake mode no PWM capability is needed the charge pump is set into low-power mode to reduce the current consumption I from the VSD pin.
Page 952: Adaptive Control Mode
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Figure 224 shows the thresholds V and V and propagation delay t of the fast comparators and SH(high) SH(low) cdly the measured slope timing parameters t , and t during PWM actuation of the sdly(on) sdur(on) sdly(off)
Page 953: Adjustable Voltage Monitoring
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.2.12 Adjustable Voltage Monitoring The supply voltages of the Bridge Driver (VSD and VCP) are monitored by the Measurement Unit. The Bridge Driver including the charge pump can be optionally disabled at undervoltage or overvoltage of the monitored signals.
Page 954: Current-Driven Output Stages
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Table 511 Recommended settings for the BDRV_PWMSRCSEL register BDRV_PWMSRCSEL bit field Default/reset settings Recommended settings LS1_SRC_SEL : CC60 : COUT60 LS2_SRC_SEL : CC60 : COUT61 HS1_SRC_SEL : CC60 : CC60 HS2_SRC_SEL : CC60 : CC61 27.3.2 Current-Driven Output Stages...
Page 955 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Depending on the application needs, the clamping current set point values can be programmed • to low values in order to be robust against external shorts, or • to high values in order to be robust against fast transients. Note: The time values T1ON/T1OFF have to be chosen according to the actual entire MOSFET switching time in order to be able to control the switching slopes by I1ON/I1OFF.
Page 956 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) PWM ON TyON TyOFF GATE IyON Gate Current Set Point ICLMPON Profile ICLMPOFF IyOFF MOSFET Voltages MOSFET Current Figure 227 MOSFET switching phases and corresponding gate current set points The 4 phases of switching on a MOSFET are: •...
Page 957: Adjustable Cross-Conduction Protection
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) The nominal gate currents (I ) for the respective set point values (x) can be estimated by GATE (27.1) 1.35 (x) = 7 mA + 313 mA * ( GATE and are shown in Table 512.
Page 958: High-Current Discharge Mode
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Table 513 Cross-conduction protection time settings DRV_CCP_TMUL= DRV_CCP_TMUL= DRV_CCP_TMUL= DRV_CCP_TMUL= DRV_CCP_TIMSEL=00 0.2 µs 0.4 µs 0.8 µs 1.6 µs DRV_CCP_TIMSEL=01 0.4 µs 0.8 µs 1.6 µs 3.2 µs DRV_CCP_TIMSEL=10 0.8 µs 1.6 µs 3.2 µs 6.4 µs DRV_CCP_TIMSEL=11...
Page 959: Channel Turn On/Off Delay Measurement
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Table 514 Timing measurement results Half Bridge 1 Half Bridge 2 on delay HB1_T12ONCNT in BDRV_HB1ASEQONVAL HB2_T12ONCNT in BDRV_HB2ASEQONVAL on slope HB1_T3ONCNT in BDRV_HB1ASEQONVAL HB2_T3ONCNT in BDRV_HB2ASEQONVAL off delay HB1_T1OFFCNT in BDRV_HB1ASEQOFFVAL HB2_T1OFFCNT in BDRV_HB2ASEQOFFVAL off slope HB1_T2OFFCNT in...
Page 960: Adaptive Control Mode
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) unfiltered VDS comparator outputs VDScomp_o_LSx , x: 1..2 DLY_DIAG_STS VDScomp_o_HSx , x: 1..2 mi_clk_i reset hold stop DLY_DIAG_CHSEL DLY_DIAG_TIM 10 bit up counter start mi_clk_i reset LSx_ON , x: 1..2 Registered outputs from CCPlogic HSx_ON , x: 1..2 Clear DLY_DIAG_STS...
Page 961: Optimizer Activation
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.3.9.3 Optimizer Activation The adaptive control mode is individually set up for each half bridge and separately for on and off phases by the bits of the BDRV_ASEQC register according to Table 516: Table 516 Adaptive Sequencer Mode control bits Half bridge...
Page 962: Adjustable Voltage Monitoring
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) DRV_CP_CLK_CTRL CP1L SYSCLKSEL CP1H SCU_APCLK1_CTRL1 {FCP, DITH_UPPER} INTOSC CP_C LK SY S C P_C LK _SCU Pumping CPCLK_DIV {1,2} Stages CP2L {FCP, DITH_LOWER} LP_CLK CP-Control CP2H SCU_DM Charge Pump Figure 230 Clock Generation of Charge Pump Block The charge pump clock f is derived from the system clock f .
Page 963: Register Definition
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.4 Register Definition The Bridge Driver registers are located in the address space below. Table 517 Register Address Space Module Base Address End Address Note BDRV 40034000 40037FFF Bridge Driver Table 518 Register Overview Register Short Name Register Long Name Offset Address...
Page 964 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Table 518 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value BDRV_ONSEQHB2TC Turn-on Slewrate Sequencer Half Bridge 2 Time Table 537 Control BDRV_ONSEQHB2IC Turn-on Slewrate Sequencer Half Bridge 2 Table 538 Current Control Register...
Page 965: Driver Register
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Table 518 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value Register Definition, Charge Pump Control and Status Register BDRV_CP_CTRL Charge Pump Control and Status Register Table 557 BDRV_CP_CLK_CTRL Charge Pump Clock Control Register Table 558 BDRV_CP_IRQS...
Page 966 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description HS2_OC_DIS High Side Driver Overcurrent Shutdown Select Global Shutdown, all bridges will be shut down in case of overcurrent Local Shutdown, only local driver will be shut down in case of overcurrent Reserved Always read as 0 HS2_SUPERR_STS...
Page 967 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description HS1_SUPERR_STS High Side Driver 1 Supply Error Status NORMAL, supply is in required range. SUPPLY ERROR, detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. Reserved Always read as 0 HS1_DCS_EN High Side Driver 1 Diagnosis Current Source Enable...
Page 968 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description LS2_PWM rwhir Low Side Driver 2 PWM Enable Note: This bit can only be set if HS2_ON and LS2_ON are 0 and PWM enable only takes effect if the bits HS2_PWM and/or LS2_PWM are 1.
Page 969 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) H-Bridge Driver Control Register 2 BDRV_CTRL2 Offset Reset Value H-Bridge Driver Control 2 Table 520 DLY_ DLY_DIAG_C DLY_ DLY_ DLY_DIAG_TIM DIA* HSEL DIA* DIA* HB2O HB1O HB2O HB1O FFS* FFS* NSE* NSE* Field Bits Type Description...
Page 970 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description HB1OFFSEQCNF Half Bridge 1 Off Sequencer Configuration Normal Mode, OFF-Sequencer is disabled and driver operates with constant current. Sequencer Mode, OFF-Sequencer is enabled. HB2ONSEQCNF Half Bridge 2 On Sequencer Configuration Normal Mode, ON-Sequencer is disabled and driver operates with constant current.
Page 971 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) H-Bridge Driver Control 3 BDRV_CTRL3 Offset Reset Value H-Bridge Driver Control 3 Table 521 DRV_ DRV_CCP DRV_CCP DSMONVTH CCP* _TMUL _TIMSEL Field Bits Type Description Reserved Always read as 0 DRV_CCP_DIS Dynamic cross conduction protection Disable Note: the cross condution protection consists of two stages.
Page 972 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description DSMONVTH 18:16 Voltage Threshold for Drain-Source Monitoring of external FETs 0.125_V, Threshold 0 for VDS at 0.125 V 0.25_V, Threshold 1 for VDS at 0.25 V 0.50_V, Threshold 2 for VDS at 0.50 V 0.75_V, Threshold 3 for VDS at 0.75 V 1.00_V, Threshold 4 for VDS at 1.00 V 1.25_V, Threshold 5 for VDS at 1.25 V...
Page 973 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) PWM Source Selection Register BDRV_PWMSRCSEL Offset Reset Value PWM Source Selection Register Table 522 HS2_SRC HS1_SRC _SEL _SEL LS2_SRC LS1_SRC _SEL _SEL Field Bits Type Description 31:21 Reserved Always read as 0 HS2_SRC_SEL 20:19 HS2 PWM Source Selection Note:...
Page 974 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description Reserved Always read as 0 LS1_SRC_SEL LS1 PWM Source Selection Note: Can only be written if DRV_CTRL1.LS1_PWM=0. CC60, PWM output of CCU6 CC61, PWM output of CCU6 COUT60, PWM output of CCU6 COUT61, PWM output of CCU6 Table 522 RESET of...
Page 975 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Gate Current Clamping Value Control On State BDRV_IGATECLMPONC Offset Reset Value Gate Current Clamping Value in ON State Table 523 HB2AF_ICLMPON HB1AF_ICLMPON HB2_ICLMPON HB1_ICLMPON Field Bits Type Description 31:30 Reserved Always read as 0 HB2AF_ICLMPON 29:24 Half Bridge 2-active freewheeling-current clamping...
Page 976 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Gate Current Clamping Value Control On State BDRV_IGATECLMPOFFC Offset Reset Value Gate Current Clamping Value in OFF State Table 524 HB2AF_ICLMPOFF HB1AF_ICLMPOFF HB2_ICLMPOFF HB1_ICLMPOFF Field Bits Type Description 31:30 Reserved Always read as 0 HB2AF_ICLMPOFF 29:24 Half Bridge 2-active freewheeling-current clamping...
Page 977 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) H-Bridge (Half Bridge) Driver Interrupt Status Register BDRV_IRQS Offset Reset Value H-Bridge Driver Interrupt Status Table 525 SEQ_ERR HS2_OC_ HS2_DS_ HS2_DS_ HS1_OC_ HS1_DS_ HS1_DS_ LS2_OC_ LS2_DS_ LS2_DS_ LS1_OC_ LS1_DS_ LS1_DS_ HB2_ASE HB1_ASE Q_IS Q_IS Field Bits...
Page 978 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description HS1_OC_IS External High Side 1 FET Over-current Interrupt Status no Over-current, no over-current Condition occurred. Over-current, over-current occurred; switch is automatically shutdown. HS1_DS_STS High Side Driver 1 Drain Source Monitoring Status in OFF-State no short on external FET, no short detected.
Page 979 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description HB2_ASEQ_IS Half Bridge 2 Adaptive Sequencer Interrupt Status Note: Interrupt is set on any HB2 Error reported in BDRV_ASEQSTS no error in SEQ, no sequencer Error detected. error in SEQ, sequencer Error detected. HB1_ASEQ_IS Half Bridge 1 Adaptive Sequencer Interrupt Status Note:...
Page 980 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description SEQ_ERR_ISC Driver Sequence Error Status Clear no Clear, Clear, HS2_OC_ISC External High Side 2 FET Over-current Status Clear no Clear, Clear, HS2_DS_SC High Side Driver 2 Drain Source Monitoring Status Clear in OFF-State no Clear, Clear,...
Page 981 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description LS1_OC_ISC External Low Side 1 FET Over-current Status Clear no Clear, Clear, LS1_DS_SC Low Side Driver 1 Drain Source Monitoring Status Clear in OFF-State no Clear, Clear, LS1_DS_ISC Low Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State no Clear, Clear,...
Page 982 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) SEQ_ERR HS2_OC_ HS2_DS_ _IEN HS1_OC_ HS1_DS_ LS2_OC_ LS2_DS_ LS1_OC_ LS1_DS_ HB2_ASE HB1_ASE Q_IEN Q_IEN Field Bits Type Description SEQ_ERR_IEN Driver Sequence Error Interrupt Enable disable, enable, HS2_OC_IEN External High Side 2 FET Over-current Interrupt Enable disable, enable, Reserved...
Page 983: Sequencer Configuration Registers
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Field Bits Type Description LS2_OC_IEN External Low Side 2 FET Over-current Interrupt Enable disable, enable, Reserved Always read as 0 LS2_DS_IEN Low Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State disable, enable, 11:7 Reserved...
Page 984: Half Bridge 1 - Slew Rate Configuration Registers For Switch-Off/On
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Slewrate Sequencer Mapping Register BDRV_SEQMAP Offset Reset Value Slewrate Sequencer Mapping Register Table 528 HB2_ HB1_ SEQ* SEQ* Field Bits Type Description 31:3 Reserved Always read as 0 HB2_SEQMAP Half Bridge 2 Sequencer Mapping Note: as the sequencer and adaptive sequencer driver functionality is only available per half bridge,...
Page 985 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) • configuration register for the discharge timing with four current settings for the four phases during switch- • configuration register for the discharge current with four current settings for the four phases during switch-off •...
Page 986 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-off Slewrate Sequencer HB1 Time Control BDRV_OFFSEQHB1TC Offset Reset Value Turn-off Slewrate Sequencer Half Bridge 1 Table 529 Time Control HB1_T4OFF HB1_T3OFF HB1_T2OFF HB1_T1OFF Field Bits Type Description HB1_T4OFF 31:24 Half Bridge 1-slew rate sequencer off-phase 4 time setting 50ns, 50ns phase duration 12.8us, 12.8us phase duration...
Page 987 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-off Slewrate Sequencer HB1 Current Control BDRV_OFFSEQHB1IC Offset Reset Value Turn-off Slewrate Sequencer Half Bridge 1 Table 530 Current Control HB1_I4OFF HB1_I3OFF HB1_I2OFF HB1_I1OFF Field Bits Type Description 31:30 Reserved Always read as 0 HB1_I4OFF 29:24 Half Bridge 1-slew rate sequencer off-phase 4 current...
Page 988 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-on Slewrate Sequencer HB1 Time Control BDRV_ONSEQHB1TC Offset Reset Value Turn-on Slewrate Sequencer Half Bridge 1 Table 531 Time Control HB1_T4ON HB1_T3ON HB1_T2ON HB1_T1ON Field Bits Type Description HB1_T4ON 31:24 Half Bridge 1-slew rate sequencer on-phase 4 time setting 50ns, 50ns phase duration 12.8us, 12.8us phase duration...
Page 989 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-on Slewrate Sequencer HB1 Current Control BDRV_ONSEQHB1IC Offset Reset Value Turn-on Slewrate Sequencer Half Bridge 1 Table 532 Current Control HB1_I4ON HB1_I3ON HB1_I2ON HB1_I1ON Field Bits Type Description 31:30 Reserved Always read as 0 HB1_I4ON 29:24 Half Bridge 1-slew rate sequencer on-phase 4 current...
Page 990: Half Bridge 1 - Slew Rate Configuration Registers For Active Freewheeling
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.4.4 Half Bridge 1 - Slew Rate Configuration Registers for Active Freewheeling. The switch off/on behaviour of the half bridge driver during active freewheeling can be configured by one dedicated gate current configuration register: •...
Page 991 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Slewrate Sequencer Active Freewheeling HB1 Current Control BDRV_SEQAFHB1IC Offset Reset Value Slewrate Sequencer-Active Freewheeling- Table 533 Half Bridge 1 Current Control HB1AF_ION HB1AF_IOFF Field Bits Type Description 31:22 Reserved Always read as 0 HB1AF_ION 21:16 Half Bridge 1-active freewheeling-slew rate sequencer...
Page 992: Half Bridge 2 - Slew Rate Configuration Registers For Switch-Off/On
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Slewrate Sequencer Active Freewheeling HB1 Clamping Current Delay BDRV_SEQAFHB1CD Offset Reset Value Slewrate Sequencer-Active Freewheeling- Table 534 Half Bridge 1 Clamping Current Delay HB1AF_TDICLMPON HB1AF_TDICLMPOFF Field Bits Type Description 31:16 Reserved Always read as 0 HB1AF_TDICLMPON 15:8 Clamping current delay during active freewheeling for...
Page 993 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-off Slewrate Sequencer HB2 Time Control BDRV_OFFSEQHB2TC Offset Reset Value Turn-off Slewrate Sequencer Half Bridge 2 Table 535 Time Control HB2_T4OFF HB2_T3OFF HB2_T2OFF HB2_T1OFF Field Bits Type Description HB2_T4OFF 31:24 Half Bridge 2-slew rate sequencer off-phase 4 time setting 50ns, 50ns phase duration 12.8us, 12.8us phase duration...
Page 994 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-off Slewrate Sequencer HB2 Current Control BDRV_OFFSEQHB2IC Offset Reset Value Turn-off Slewrate Sequencer Half Bridge 2 Table 536 Current Control HB2_I4OFF HB2_I3OFF HB2_I2OFF HB2_I1OFF Field Bits Type Description 31:30 Reserved Always read as 0 HB2_I4OFF 29:24 Half Bridge 2-slew rate sequencer off-phase 4 current...
Page 995 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-on Slewrate Sequencer HB2 Time Control BDRV_ONSEQHB2TC Offset Reset Value Turn-on Slewrate Sequencer Half Bridge 2 Table 537 Time Control HB2_T4ON HB2_T3ON HB2_T2ON HB2_T1ON Field Bits Type Description HB2_T4ON 31:24 Half Bridge 2-slew rate sequencer on-phase 4 time setting 50ns, 50ns phase duration 12.8us, 12.8us phase duration...
Page 996 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Turn-on Slewrate Sequencer HS1 Current Control BDRV_ONSEQHB2IC Offset Reset Value Turn-on Slewrate Sequencer Half Bridge 2 Table 538 Current Control HB2_I4ON HB2_I3ON HB2_I2ON HB2_I1ON Field Bits Type Description 31:30 Reserved Always read as 0 HB2_I4ON 29:24 Half Bridge 2-slew rate sequencer on-phase 4 current...
Page 997: Half Bridge 2 - Slew Rate Configuration Registers For Active Freewheeling
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) 27.4.6 Half Bridge 2 - Slew Rate Configuration Registers for Active Freewheeling The switch off/on behaviour of the half bridge driver during active freewheeling can be configured by one dedicated gate current configuration register: •...
Page 998 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Slewrate Sequencer Active Freewheeling HB2 Current Control BDRV_SEQAFHB2IC Offset Reset Value Slewrate Sequencer-Active Freewheeling- Table 539 Half Bridge 2 Current Control HB2AF_ION HB2AF_IOFF Field Bits Type Description 31:22 Reserved Always read as 0 HB2AF_ION 21:16 Half Bridge 2-active freewheeling-slew rate sequencer...
Page 999: Adaptive Slew Rate Sequencer Control And Status Registers
MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Slewrate Sequencer Active Freewheeling HB2 Clamping Current Delay BDRV_SEQAFHB2CD Offset Reset Value Slewrate Sequencer-Active Freewheeling- Table 540 Half Bridge 2 Clamping Current Delay HB2AF_TDICLMPON HB2AF_TDICLMPOFF Field Bits Type Description 31:16 Reserved Always read as 0 HB2AF_TDICLMPON 15:8 Clamping current delay during active freewheeling for...
Page 1000 MOTIX™ TLE985xQX Bridge Driver (incl. Charge Pump) Adaptive Slewrate Sequencer Control Register BDRV_ASEQC Offset Reset Value Adaptive Slewrate Sequencer Control Table 541 Register HB2O HB2O HB2O HB2O HB2A HB2A FFH* NHY* PTO* PTO* SMO* SMO* HB1O HB1O HB1O HB1O HB1A HB1A FFH* NHY*...

Infineon MOTIX TLE985xQX User Manual

Quick Links

Related Manuals for Infineon MOTIX TLE985xQX

Summary of Contents for Infineon MOTIX TLE985xQX