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NEC mPD789479 Sub Series User Manual

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User's Manual

μ

PD789479 Subseries

8-Bit Single-Chip Microcontrollers

μ

PD789477

μ

PD789478

μ

PD789479

μ

PD78F9478

μ

PD78F9479

Document No. U15400EJ4V0UD00 (4th edition)

Date Published August 2007 NS

Printed in Japan

©

2001

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Summary of Contents for NEC mPD789479 Sub Series

Page 1 User’s Manual μ PD789479 Subseries 8-Bit Single-Chip Microcontrollers μ PD789477 μ PD789478 μ PD789479 μ PD78F9478 μ PD78F9479 Document No. U15400EJ4V0UD00 (4th edition) Date Published August 2007 NS Printed in Japan 2001 ©...
Page 2 [MEMO] User’s Manual U15400EJ4V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 [MEMO] User’s Manual U15400EJ4V0UD...
Page 7 INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of μ PD789479 Subseries and design and develop application systems and programs using these devices. Target products: μ μ • PD789479 Subseries: PD789477, 789478, 789479, 78F9478, 78F9479 Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 8 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 9 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Page 10 CONTENTS CHAPTER 1 GENERAL...........................24 Features ............................24 Applications..........................24 Ordering Information .........................25 Pin Configuration (Top View)....................26 78K/0S Series Lineup.........................29 Block Diagram ..........................32 Overview of Functions.......................33 CHAPTER 2 PIN FUNCTIONS .......................35 List of Pin Functions........................35 Description of Pin Functions ....................38 2.2.1 P00 to P07 (Port 0) ........................38 2.2.2 P10, P11 (Port 1) ..........................
Page 11 3.1.2 Internal data memory space......................52 3.1.3 Special function register (SFR) area ..................... 52 3.1.4 Data memory addressing ......................53 Processor Registers ........................58 3.2.1 Control registers..........................58 3.2.2 General-purpose registers ......................61 3.2.3 Special function registers (SFRs)....................62 Instruction Address Addressing ....................66 3.3.1 Relative addressing........................
Page 12 5.4.2 Subsystem clock oscillator ......................102 5.4.3 Example of incorrect resonator connection ................. 103 5.4.4 Divider circuit..........................104 5.4.5 When subsystem clock is not used ..................... 104 Subsystem clock × 4 multiplication circuit ................... 104 5.4.6 Clock Generator Operation .....................105 Changing Setting of System Clock and CPU Clock .............106 5.6.1 Time required for switching between system clock and CPU clock..........
Page 13 Watchdog Timer Configuration ....................168 Watchdog Timer Control Registers ..................169 Watchdog Timer Operation.....................171 9.4.1 Operation as watchdog timer ...................... 171 9.4.2 Operation as interval timer ......................172 CHAPTER 10 8-BIT A/D CONVERTER ....................173 10.1 8-Bit A/D Converter Functions ....................173 10.2 8-Bit A/D Converter Configuration ..................173 10.3 8-Bit A/D Converter Control Registers ..................176 10.4 8-Bit A/D Converter Operation....................179 10.4.1...
Page 14 13.8 Example of LCD Drive Power Connections................265 CHAPTER 14 MULTIPLIER ........................266 14.1 Multiplier Function ........................266 14.2 Multiplier Configuration......................266 14.3 Multiplier Control Register ......................268 14.4 Multiplier Operation .........................269 CHAPTER 15 REMOTE CONTROLLER RECEIVER .................270 15.1 Remote Controller Receiver Functions .................270 15.2 Remote Controller Receiver Configuration................270 15.3 Registers to Control Remote Controller Receiver..............276 15.4 Operation of Remote Controller Receiver ................278 15.4.1...
Page 15 19.1.2 Communication mode ......................... 319 19.1.3 On-board pin processing......................322 19.1.4 Connection of adapter for flash writing..................325 μ 19.2 Cautions on PD78F9478 and 78F9479 .................328 CHAPTER 20 MASK OPTIONS ......................329 CHAPTER 21 INSTRUCTION SET ......................330 21.1 Operation ..........................330 21.1.1 Operand identifiers and description methods ................
Page 16 LIST OF FIGURES (1/6) Figure No. Title Page I/O Circuit Types .............................44 μ Memory Map ( PD789477)..........................46 μ Memory Map ( PD789478)..........................47 μ Memory Map ( PD78F9478) ..........................48 μ Memory Map ( PD789479)..........................49 μ Memory Map ( PD78F9479) ..........................50 μ Data Memory Addressing ( PD789477) ......................53 μ...
Page 17 LIST OF FIGURES (2/6) Figure No. Title Page Format of Processor Clock Control Register ....................98 Format of Subclock Oscillation Mode Register ....................99 Format of Subclock Control Register ......................100 Format of Subclock Selection Register......................100 External Circuit of Main System Clock Oscillator ..................101 External Circuit of Subsystem Clock Oscillator .....................102 Examples of Incorrect Resonator Connection....................103 5-10...
Page 18 LIST OF FIGURES (3/6) Figure No. Title Page 7-19 Timing of Interval Timer Operation with 16-Bit Resolution ................144 7-20 Timing of External Event Counter Operation with 16-Bit Resolution .............146 7-21 Timing of Square-Wave Output with 16-Bit Resolution .................148 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) ..........150 7-22 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M <...
Page 19 LIST OF FIGURES (4/6) Figure No. Title Page 11-1 Block Diagram of Serial Interface 20 ......................188 11-2 Block Diagram of Baud Rate Generator 20 ....................189 11-3 Format of Serial Operation Mode Register 20 ....................191 11-4 Format of Asynchronous Serial Interface Mode Register 20.................192 11-5 Format of Asynchronous Serial Interface Status Register 20 ...............194 11-6...
Page 20 LIST OF FIGURES (5/6) Figure No. Title Page 13-9 Example of Connecting Three-Time Slice LCD Panel ..................260 13-10 Three-Time Slice LCD Drive Waveform Examples (1/3 Bias Method) ............261 13-11 Four-Time Slice LCD Display Pattern and Electrode Connections ...............262 13-12 Example of Connecting Four-Time Slice LCD Panel ..................263 13-13 Four-Time Slice LCD Drive Waveform Examples (1/3 Bias Method) ............264 13-14...
Page 21 LIST OF FIGURES (6/6) Figure No. Title Page 17-1 Format of Oscillation Stabilization Time Selection Register................306 17-2 Releasing HALT Mode by Interrupt.......................308 17-3 Releasing HALT Mode by RESET Input .......................309 17-4 Releasing STOP Mode by Interrupt ......................311 17-5 Releasing STOP Mode by RESET Input ......................312 18-1 Block Diagram of Reset Function .........................313 18-2...
Page 22 LIST OF TABLES (1/2) Table No. Title Page Types of Pin I/O Circuits ..........................42 Internal ROM Capacity............................51 Vector Table ..............................51 Internal High-Speed RAM and Internal Low-Speed RAM ................52 Special Function Registers ..........................63 Port Functions..............................76 Configuration of Port ............................76 Port Mode Registers and Output Latch Settings When Using Alternate Functions.........92 Configuration of Clock Generator........................95 Maximum Time Required for Switching CPU Clock ..................106 16-Bit Timer 20 Configuration ........................108...
Page 23 LIST OF TABLES (2/2) Table No. Title Page 11-1 Configuration of Serial Interface 20 ......................187 11-2 Serial Interface 20 Operation Mode Settings ....................193 11-3 Example of Relationships Between System Clock and Baud Rate...............196 11-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ..197 11-5 Example of Relationships Between System Clock and Baud Rate...............204 11-6...
Page 24 CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Program Memory Data Memory (ROM) Internal RAM LCD Display RAM Part Number μ 28 × 4 bits PD789477 Mask ROM 24 KB 768 bytes μ PD789478 32 KB 1,024 bytes μ...
Page 25 CHAPTER 1 GENERAL 1.3 Ordering Information <R> Part Number Package Internal ROM μ 80-pin plastic QFP (14 × 14) PD789477GC-×××-8BT Mask ROM μ 80-pin plastic TQFP (fine pitch) (12 × 12) PD789477GK-×××-9EU Mask ROM μ 80-pin plastic QFP (14 × 14) PD789478GC-×××-8BT Mask ROM μ...
Page 26 CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) μ PD789477, 789478, 78F9478 80-pin plastic QFP (14 × 14) 80-pin plastic TQFP (fine pitch) (12 × 12) μ μ PD789477GC-×××-8BT PD789477GK-×××-9EU μ μ PD789478GC-×××-8BT PD789478GK-×××-9EU μ μ PD78F9478GC-8BT PD78F9478GK-9EU μ μ PD789477GC-×××-8BT-A PD789477GK-×××-9EU-A μ...
Page 27 CHAPTER 1 GENERAL μ PD789479, 78F9479 80-pin plastic QFP (14 × 14) 80-pin plastic TQFP (fine pitch) (12 × 12) μ μ PD789479GC-×××-8BT PD789479GK-×××-9EU μ μ PD78F9479GC-8BT PD78F9479GK-9EU μ μ PD789479GC-×××-8BT-A PD789479GK-×××-9EU-A μ μ PD78F9479GC-8BT-A PD78F9479GK-9EU-A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P20/SCK20/ASCK20 P21/SO20/TxD20 P22/SI20/RxD20...
Page 28 CHAPTER 1 GENERAL Pin Name ANI0 to ANI7: Analog input RESET: Reset ASCK20: Asynchronous serial input RIN: Remote control input Analog power supply RxD0: Receive data Analog ground S0 to S27: Segment output COM0 to COM3: Common output SCK10: Serial clock input/output CPT20: Capture trigger input SI10:...
Page 29 CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup <R> The products in the 78K/0S microcontrollers are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications μ...
Page 30 CHAPTER 1 GENERAL The major differences between the subseries are shown below. Series for General-Purpose Applications and LCD Drive Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity 8-Bit 16-Bit Watch WDT MIN.Value Subseries (Bytes) μ − − − Small- PD789046 16 K 1 ch 1 ch...
Page 31 CHAPTER 1 GENERAL Series for ASSP Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity 8-Bit 16-Bit Watch WDT Subseries (Bytes) MIN.Value μ − − − − − PD789800 2 ch 1 ch 2 ch (USB: 1ch) 4.0 V μ − −...
Page 32 CHAPTER 1 GENERAL 1.6 Block Diagram CPT20/TO20/P33 Port 0 P00 to P07 16-bit timer 20 P10 to P11 TO50/P30 Port 1 8-bit timer 50 TMI60/P30 8-bit timer/ P20 to P25 Port 2 event counter 60 TO60/P31 8-bit timer/ P30 to P34 Port 3 TMI61/TO61/P32 event counter 61...
Page 33 CHAPTER 1 GENERAL 1.7 Overview of Functions (1/2) μ μ μ μ μ Item PD789477 PD789478 PD78F9478 PD789479 PD78F9479 Internal memory 24 KB 32 KB 32 KB (flash 48 KB 48 KB (flash memory) memory) High-speed RAM 768 bytes 1024 bytes 1536 bytes −...
Page 34 CHAPTER 1 GENERAL (2/2) μ μ μ μ μ Item PD789477 PD789478 PD78F9478 PD789479 PD78F9479 • Reset by RESET signal input Reset • Internal reset by watchdog timer Supply voltage = 1.8 to 5.5 V = −40 to +85°C Operating ambient temperature •...
Page 35 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions Port pins (1/2) Pin Name Function After Reset Alternate Function Note 1 P00 to P07 Port 0. Input KR0 to KR7 Note 2 8-bit I/O port. KR00 to KR07 Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register B0 (PUB0) or the key return mode register (KRM00).
Page 36 CHAPTER 2 PIN FUNCTIONS Port pins (2/2) Pin Name Function After Reset Alternate Function − Note 1 P70 to P73 Input Port 7. Input 4-bit input port. (Only when input port is selected by mask option or port function register) −...
Page 37 CHAPTER 2 PIN FUNCTIONS Non-port pins (2/2) Pin Name Function After Reset Alternate Function TxD20 Output Serial data output of asynchronous serial interface Input P21/SO20 RxD20 Input Serial data input of asynchronous serial interface Input P22/SI20 Input Remote control receive data input Input S0 to S15 Output...
Page 38 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. Port mode These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0).
Page 39 CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P34 (Port 3) These pins constitute a 5-bit I/O port. In addition, they also function as timer I/O, external interrupt inputs, and input of remote control receive data. Port 3 can be specified in the following operation modes in 1-bit units. Port mode In this mode, P30 to P34 function as a 5-bit I/O port.
Page 40 CHAPTER 2 PIN FUNCTIONS 2.2.6 P60 to P67 (Port 6) This is an 8-bit input-only port. In addition to a general-purpose input port function, it has an A/D converter input Note function and key return signal detection function Port mode In this mode, P60 to P67 function as an 8-bit input-only port.
Page 41 CHAPTER 2 PIN FUNCTIONS 2.2.14 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.15 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation.
Page 42 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1.
Page 43 CHAPTER 2 PIN FUNCTIONS Table 2-1. Types of Pin I/O Circuits (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins – Input Connect directly to V – Leave open. RESET Input – – – Connect directly to V Independently connect a 10 kΩ...
Page 44 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (1/2) Type 2 Type 2-H Input enable Schmitt-triggered input with hysteresis characteristics. Type 5-A Type 5-K Pull-up P-ch enable Data P-ch IN/OUT Data P-ch Output N-ch disable IN/OUT Output N-ch disable Input enable Input...
Page 45 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (2/2) Type 13-W Type 13-V Mask Data IN/OUT option Output N-ch Data disable IN/OUT Output N-ch disable Input enable Middle-voltage input buffer Input enable Middle-voltage input buffer Type 17 Type 18 P-ch P-ch P-ch...
Page 46 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space μ PD789479 Subseries can access 64 KB of memory space. Figures 3-1 to 3-5 show the memory maps. μ Figure 3-1. Memory Map ( PD789477) F F F F H Special function registers 256 ×...
Page 47 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-2. Memory Map ( PD789478) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 1,024 × 8 bits F B 0 0 H F A F F H Reserved...
Page 48 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-3. Memory Map ( PD78F9478) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 1,024 × 8 bits F B 0 0 H F A F F H Reserved...
Page 49 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-4. Memory Map ( PD789479) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 1,024 × 8 bits F B 0 0 H F A F F H Reserved...
Page 50 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-5. Memory Map ( PD78F9479) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 1,024 × 8 bits F B 0 0 H F A F F H Reserved...
Page 51 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). μ Internal ROM (or flash memory) with the following capacity is provided for each product in the PD789479 Subseries.
Page 52 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space Internal high-speed RAM and internal low-speed RAM μ PD789479 Subseries products incorporate internal high-speed RAM and internal low-speed RAM of the following capacity for each product. The internal high-speed RAM can also be used as a stack. The internal low-speed RAM cannot be used as a stack.
Page 53 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing μ PD789479 Subseries is provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that correspond to the particular function of an area such as the special function registers are available.
Page 54 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-7. Data Memory Addressing ( PD789478) F F F F H Special function registers SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 55 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-8. Data Memory Addressing ( PD78F9478) F F F F H Special function registers SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 56 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-9. Data Memory Addressing ( PD789479) F F F F H Special function registers 256 × 8 bits SFR addressing F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short direct addressing...
Page 57 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-10. Data Memory Addressing ( PD78F9479) F F F F H Special function registers 256 × 8 bits SFR addressing F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short direct addressing...
Page 58 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers μ PD789479 Subseries is provided with the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence status and stack memory. The program counter, program status word, and stack pointer are control registers. Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 59 CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable interrupts are all disabled. When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgement enable is controlled by the interrupt mask flag for the corresponding interrupt source.
Page 60 CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10...
Page 61 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 62 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 63 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (1/3) Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 64 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (2/3) Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − FF48H 16-bit timer mode control register 20 TMC20 √...
Page 65 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (3/3) Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − FF80H A/D converter mode register 0 ADML0 √ √...
Page 66 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 67 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 68 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 69 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 70 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 71 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 72 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 73 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 74 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 75 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions μ PD789479 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. The functions of each port are shown in Table 4-1. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 76 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P07 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register B0 (PUB0).
Page 77 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B0 (PUB0).
Page 78 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B1 (PUB1).
Page 79 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 6-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P25 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B2 (PUB2).
Page 80 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 PUB2 PUB21 P-ch PORT Output latch P21/SO20/TxD20 (P21) PM21 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15400EJ4V0UD...
Page 81 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 and P25 PUB2 PUB22, PUB25 P-ch Alternate function PORT Output latch P22/SI20/ (P22, P25) RxD20, P25/SI10 PM22, PM25 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15400EJ4V0UD...
Page 82 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P23 PUB2 PUB23 P-ch Alternate function PORT Output latch P23/SCK10 (P23) PM23 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15400EJ4V0UD...
Page 83 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P24 PUB2 PUB24 P-ch PORT Output latch P24/SO10 (P24) PM24 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15400EJ4V0UD...
Page 84 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 5-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3). When using the P30 to P34 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B3 (PUB3).
Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P34 PUB3 PUB34 P-ch Alternate function PORT Output latch P34/RIN (P34) PM34 PUB3: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal User’s Manual U15400EJ4V0UD...
Page 86 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option.
Page 87 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 This is an 8-bit input-only port. Note This port is also used for the analog input of an A/D converter and of key return signal input Figure 4-12 shows a block diagram of port 6. μ...
Page 88 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P60 to P67 (2/2) μ PD789479 and 78F9479 Alternate function KRM01 KRM010, KRM014 to KRM017 P60/ANI0/KR10 to P67/ANI7/KR17 A/D converter − KRM01: Key return mode register 01 RD: Port 6 read signal User’s Manual U15400EJ4V0UD...
Page 89 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 This is a 4-bit input-only port. Only the bits for which the port function is selected can be used, by using a mask μ μ option in the PD789477, 789478, and 789479 or port function register 7 (PF7) in the PD78F9478 and 78F9479.
Page 90 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 This is an 8-bit I/O port with an output latch. Only the bits for which the port function is selected can be used, by μ μ using a mask option in the PD789477, 789478, and 789479 or port function register 8 (PF8) in the PD78F9478 and 78F9479.
Page 91 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0 to PM3, PM5, PM8) • Pull-up resistor option registers (PUB0 to PUB3) • Port function registers (PF7, PF8) ( μ...
Page 92 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function PM×× P×× Name × P00 to P07 KR0 to KR7 or KR00 to KR07 Input × INTP0 Input TO50 Output ×...
Page 93 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option registers (PUB0 to PUB3) These registers set whether to use on-chip pull-up resistors for pins P00 to P07, P10, P11, P20 to P25, and P30 to P34. An on-chip pull-up resistor can be used only for those bits set to the input mode in a port for which the use of the on-chip pull-up resistor has been specified using PUB0 to PUB3.
Page 94 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 95 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 96 CHAPTER 5 CLOCK GENERATOR μ Figure 5-1. Clock Generator Block Diagram ( PD789477, 789478, and 789479) Internal bus A/D converter Mask option Subclock oscillation mode register ×4 FRC SCC ×2 (SCKM) multiplication multiplication circuit circuit Mask option Subsystem Timer 50 clock Watch timer oscillator...
Page 97 CHAPTER 5 CLOCK GENERATOR μ Figure 5-2. Clock Generator Block Diagram ( PD78F9478, 78F9479) Internal bus A/D converter Subclock oscillation Subclock selection mode register (SCKM) FRC SCC ×4 ×2 register (SSCK) multiplication multiplication circuit circuit Selector Timer 50 Subsystem Watch timer clock oscillator LCD controller/driver Clock to peripheral...
Page 98 CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following four registers. • Processor clock control register (PCC) • Subclock oscillation mode register (SCKM) • Subclock control register (CSS) μ • Subclock selection register (SSCK) ( PD78F9478 and 78F9479 only) Processor clock control register (PCC) This register is used to select the CPU clock and set the frequency division ratio.
Page 99 CHAPTER 5 CLOCK GENERATOR Subclock oscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-4.
Page 100 CHAPTER 5 CLOCK GENERATOR Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the CPU clock operation status. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSS to 00H.
Page 101 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin.
Page 102 CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin.
Page 103 CHAPTER 5 CLOCK GENERATOR 5.4.3 Example of incorrect resonator connection Figure 5-9 shows examples of incorrect resonator connection. Figure 5-9. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current...
Page 104 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. 5.4.4 Divider circuit The divider circuit divides the output of the main system clock oscillator (f ) to generate various clocks.
Page 105 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register (PCC), subclock oscillation mode register (SCKM), and subclock control register (CSS), as follows.
Page 106 CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 107 CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-10. Switching Between System Clock and CPU Clock RESET Interrupt request signal System clock CPU clock Low-speed High-speed High-speed operation...
Page 108 CHAPTER 6 16-BIT TIMER 20 6.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value match. Timer output Timer output can be controlled when a count value and compare value match.
Page 109 CHAPTER 6 16-BIT TIMER 20 Figure 6-1. Block Diagram of 16-Bit Timer 20 Internal bus 16-bit timer mode control register 20 (TMC20) PM33 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 output latch TO20/CPT20 /INTP3/P33 16-bit compare register 20 (CR20) TOD20 16-bit timer mode Match control register 20...
Page 110 CHAPTER 6 16-BIT TIMER 20 6.3 Registers Controlling 16-Bit Timer 20 16-bit timer 20 is controlled by the following three registers. • 16-bit timer mode control register 20 (TMC20) • Port mode register 3 (PM3) • Port 3 (P3) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of the count clock, capture edge, etc.
Page 111 CHAPTER 6 16-BIT TIMER 20 Figure 6-2. Format of 16-Bit Timer Mode Control Register 20 Symbol <7> <6> <0> Address After reset Note 1 TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 FF48H TOD20 Timer output data Timer output is “0” Timer output is “1”...
Page 112 CHAPTER 6 16-BIT TIMER 20 (2) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P33/INTP3/CPT20/TO20 pin as a capture input (CPT20), set PM33 to 1. When using the above pin as a timer output (TO20), set the PM33 and P33 output latches to 0.
Page 113 CHAPTER 6 16-BIT TIMER 20 6.4 16-Bit Timer 20 Operation 6.4.1 Operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is equal to one cycle of the count clock set in TCL201 and TCL200.
Page 114 CHAPTER 6 16-BIT TIMER 20 Figure 6-5. Timing of Timer Interrupt Operation Count clock 0000H 0001H 0000H 0001H FFFFH TM20 count value CR20 INTTM20 Interrupt Interrupt acknowledgement acknowledgement TO20 TOF20 Overflow flag set Remark N = 0000H to FFFFH User’s Manual U15400EJ4V0UD...
Page 115 CHAPTER 6 16-BIT TIMER 20 6.4.2 Operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in TCL201 and TCL200.
Page 116 CHAPTER 6 16-BIT TIMER 20 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 20 (TM20) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC20 as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation. Figure 6-8.
Page 117 CHAPTER 6 16-BIT TIMER 20 6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out using a 16-bit manipulation instruction. TM20 readout is performed via the counter read buffer. The counter read buffer latches the TM20 count value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises, and the count value is retained.
Page 118 CHAPTER 6 16-BIT TIMER 20 6.5 Cautions on Using 16-Bit Timer 20 6.5.1 Restrictions when rewriting 16-bit compare register 20 Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0) before rewriting the compare register (CR20). If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite.
Page 119 CHAPTER 6 16-BIT TIMER 20 <Countermeasure B> When rewriting using 16-bit access <1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0). <2> Rewrite CR20 (16 bits). <3> Wait for one cycle or more of the count clock. <4>...
Page 120 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.1 Functions of 8-Bit Timers 50, 60, and 61 One 8-bit timer channel (timer 50) and two 8-bit timer/event counter channels (timer 60 and 61) are incorporated in μ PD789479 Subseries. The operation modes listed in the following table can be set via mode register settings. Table 7-1.
Page 121 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (5) PPG output mode (PPG: Programmable Pulse Generator) Pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse width are programmable). (6) 24-bit event counter mode Operation as an external event counter with 24-bit resolution is enabled using 16-bit timer 20 and timer 61.
Page 122 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.2 Configuration of 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 include the following hardware. Table 7-2. Configuration of 8-Bit Timers 50, 60, and 61 Item Configuration 8 bits × 3 (TM50, TM60, TM61) Timer counter Compare registers: 8 bits ×...
Page 123 <R> Figure 7-2. Block Diagram of Timer 50 Internal bus 8-bit timer mode control register 50 (TMC50) TEG50 TOE50 TCE50 TCL502 TCL501 TCL500 TMD501 TMD500 PM30 output latch 8-bit compare register 50 Decoder (CR50) Timer 50 match signal Match to Figure 7-3(F) (in cascade connection mode) Bit 7 of TM60 INTTM50...
Page 124 <R> Figure 7-3. Block Diagram of Timer 60 Internal bus 8-bit timer mode control Carrier generator output register 60 (TMC60) control register 60 (TCA60) 8-bit H width compare 8-bit compare register 60 register 60 (CR60) TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600 RMC60 NRZB60 NRZ60 (CRH60) Decoder...
Page 125 Figure 7-4. Block Diagram of Timer 61 Internal bus 8-bit timer mode control register 61 (TMC61) 8-bit H width compare 8-bit compare register 61 (CRH61) register 61 (CR61) TCE61 TCL612 TCL611 TCL610 TMD611 TMD610 TOE610 PM32 output latch Decoder Selector Match TO61/TMI61 /INTP2/P32...
Page 126 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-5. Block Diagram of Output Controller (Timer 60) <R> TOE60 RMC60 NRZ60 output latch PM31 TO60/INTP1/P31 Carrier clock Carrier generator mode (1) 8-bit compare register 50 (CR50) This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer counter 50 (TM50) and to issue an interrupt request (INTTM50) when a match occurs.
Page 127 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (4) 8-bit H width compare registers 60 and 61 (CRH60, CRH61) <R> This 8-bit register is used to continually compare the value set to CRH6n with the count value in TM6n and to issue an interrupt request (INTTM6n) when a match occurs.
Page 128 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.3 Control Registers for 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 are controlled by the following six registers. • 8-bit timer mode control register 50 (TMC50) • 8-bit timer mode control register 60 (TMC60) •...
Page 129 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (2/2) Symbol <7> <6> <0> Address After reset TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH Note 4 TOE50 Control of timer output Output disabled Output enabled Notes 1.
Page 130 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-7. Format of 8-Bit Timer Mode Control Register 60 Symbol <7> <0> Address After reset TMC60 TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600 FF4EH Note 1 TCE60 Control of TM60 count operation Clear TM60 count value and stops operation (the count value is also cleared for TM50 in cascade connection mode) Start count operation (the count operation is also started for TM50 in cascade connection mode)
Page 131 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (3) Carrier generator output control register 60 (TCA60) This register is used to set the timer output data in carrier generator mode. TCA60 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 132 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (4) 8-bit timer mode control register 61 (TMC61) 8-bit timer mode control register 61 (TMC61) is used to control the timer 61 count clock setting and the operation mode setting. TMC61 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 133 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (5) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P30/INTP0/TO50/TMI60 pin as a timer output (TO50), set PM30 and the P30 output latch to 0. When used as a timer input (TMI60), set PM30 to 1.
Page 134 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4 Operation of 8-Bit Timers 50, 60, and 61 7.4.1 Operation as 8-bit timer counter Timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. •...
Page 135 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 Minimum Interval Time Maximum Interval Time Resolution μ μ μ (0.2 (51.2 (0.2 μ μ μ (1.6 (409.6 (1.6 μ μ (25.6 (6.55 ms) (25.6 μ...
Page 136 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) <R> Count clock TMnm Clear Clear Clear CRnm TCEnm Count start Count stop INTTMnm Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement TOnm Interval time Interval time...
Page 137 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH) <R> Count clock TMnm Clear Clear Clear Clear CRnm TCEnm Count start INTTMnm TOnm Remark nm = 50, 60, 61 Figure 7-14.
Page 138 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-15. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N > M)) Count clock N − 1 TMnm Clear Clear Clear Clear CRnm TCEnm TMnm overflows because M <...
Page 139 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-16. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Count Clock) Timer 60 count clock TM60 Clear Clear Clear Clear CR60 TCE60 Count start INTTM60...
Page 140 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as external event counter with 8-bit resolution (timer 60 and timer 61 only) The external event counter counts the number of external clock pulses input to the TMI6m pin by using 8-bit timer counter 6m (TM6m).
Page 141 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (CRnm). To operate timer nm for square-wave output, settings must be made in the following sequence. <1>...
Page 142 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Table 7-7. Square-Wave Output Range of Timer 60 TCL602 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width Resolution μ μ μ (51.2 (0.2 (0.2 μ μ μ (204 (0.8 (0.8 input cycle × 2 input cycle input cycle /2 input cycle ×...
Page 143 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls reset and clear.
Page 144 Figure 7-19. Timing of Interval Timer Operation with 16-Bit Resolution Count clock TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start TM50 count pulse...
Page 145 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60 pin by TM50 and TM60. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence.
Page 146 Figure 7-20. Timing of External Event Counter Operation with 16-Bit Resolution TMI60 pin input TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start...
Page 147 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 148 Figure 7-21. Timing of Square-Wave Output with 16-Bit Resolution Count clock TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start TM50 count pulse X −...
Page 149 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1>...
Page 150 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figures 7-22 to 7-24 show the operation timing of the carrier generator. Figure 7-22. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) <R> TM60 count clock TM60 count value Clear...
Page 151 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-23. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N)) <R> TM60 count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock TM50...
Page 152 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-24. Timing of Carrier Generator Operation (When CR60 = CRH60 = N) TM60 count clock TM60 count value Clear Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock TM50 count clock TM50...
Page 153 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.4 PWM output mode operation (timer 50) <R> In the PWM output mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-running). To operate timer 50 in the PWM output mode, settings must be made in the following sequence.
Page 154 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-26. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) When setting CR50 > TM50 after overflow Count clock TM50 Overflow Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 CR50 overwrite When setting CR50 <...
Page 155 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-27. Operation Timing in PWM Output Mode (When Both Edges Are Selected) CR50 = Even number Count clock TM50 Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 When CR50 = Odd number Count clock TM50 2N + 1...
Page 156 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-28. Operation Timing in PWM Output Mode (When Both Edges Are Selected) (When CR50 Is Overwritten) Count clock 2N + 1 TM50 Overflow Overflow Overflow CR50 2N + 1 TCE50 Count start INTTM50 TO50 CR50 overwrite...
Page 157 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.5 Operation as PPG output mode (timer 60 and timer 61) <R> In the PPG output mode, a pulse of any duty ratio can be output by setting a low-level width using CR6m and a high-level width using CRH6m.
Page 158 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-29. PPG Output Mode Timing (Basic Operation) Count clock TM6m count value Clear Clear Clear Clear CR6m CRH6m TCE6m Count start INTTM6m Note TO6m Note The initial value of TO6m is low level when output is enabled (TOE6m0 = 1). Remark N, M = 00H to FFH m = 0, 1...
Page 159 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-30. PPG Output Mode Timing (When CR6m and CRH6m Are Overwritten) Count clock TM6m count value Clear Clear Clear Clear CR6m CRH6m TCE6m Count start INTTM6m Note TO6m Note The initial value of TO6m is low level when output is enabled (TOE6m0 = 1). Remark N, M, X, Y = 00H to FFH m = 0, 1...
Page 160 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61 <R> Error on starting timer An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated.
Page 161 CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 shows a block diagram of the watch timer. Figure 8-1.
Page 162 CHAPTER 8 WATCH TIMER (1) Watch timer An interrupt request (INTWT) occurs at an interval of 0.5 second when using either the 4.19 MHz main system clock or the 32.768 kHz subsystem clock. Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz subsystem clock via a setting in the watch timer interrupt time selection register (WTIM).
Page 163 CHAPTER 8 WATCH TIMER 8.3 Control Registers for Watch Timer The watch timer is controlled by the following registers. • Watch timer mode control register (WTM) • Watch timer interrupt time selection register (WTIM) (1) Watch timer mode control register (WTM) This register is used to control the watch timer count clock, operation enable/disable status, prescaler interval time, and the 5-bit counter operation.
Page 164 CHAPTER 8 WATCH TIMER (2) Watch timer interrupt time selection register (WTIM) This register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for the subsystem clock to be input to watch timer. WTIM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 165 CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz subsystem clock via a setting in the watch timer interrupt time selection register (WTIM).
Page 166 CHAPTER 8 WATCH TIMER Figure 8-4. Watch Timer/Interval Timer Operation Timing 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval time (T) Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (WTM0) of the watch timer mode control register (WTM) to 1, the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the watch timer...
Page 167 CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect a program loop.
Page 168 CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Figure 9-1. Block Diagram of Watchdog Timer Internal bus WDTMK Prescaler...
Page 169 CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock selection register (WDCS) • Watchdog timer mode register (WDTM) Watchdog timer clock selection register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction.
Page 170 CHAPTER 9 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3.
Page 171 CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock selection register (WDCS).
Page 172 CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
Page 173 CHAPTER 10 8-BIT A/D CONVERTER 10.1 8-Bit A/D Converter Functions The 8-bit A/D converter is a 8-bit resolution converter used to convert analog inputs into digital signals. This converter can control eight channels (ANI0 to ANI7) of analog inputs. A/D conversion can only be started by software. One of analog inputs ANI0 to ANI7 is selected for A/D conversion.
Page 174 CHAPTER 10 8-BIT A/D CONVERTER Figure 10-1. Block Diagram of 8-Bit A/D Converter <R> P-ch ANI0/P60 Sample & hold circuit ANI1/P61 ANI2/P62 Voltage comparator ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 ANI7/P67 Successive approximation register (SAR) A/D converter mode register 1 Band-gap circuit (ADML1) ADSEL1 Controller...
Page 175 CHAPTER 10 8-BIT A/D CONVERTER Series resistor string The series resistor string is configured between AV and AV . It generates the reference voltages against which analog inputs are compared. ANI0 to ANI7 The ANI0 to ANI7 pins are the 8-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion.
Page 176 CHAPTER 10 8-BIT A/D CONVERTER 10.3 8-Bit A/D Converter Control Registers The 8-bit A/D converter is controlled by the following three registers. • A/D converter mode register 0 (ADML0) • A/D converter mode register 1 (ADML1) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADML0) ADML0 specifies the A/D conversion time for analog inputs.
Page 177 CHAPTER 10 8-BIT A/D CONVERTER μ Cautions 1. Start conversion (ADCS0 = 1) after 14 s have elapsed following the setting of ADCE0. If ADCE0 is not used, the conversion result immediately after the setting of ADCS0 is undefined. 2. The conversion result may be undefined after ADCS0 has been cleared to 0. To read the conversion result, perform the read operation during A/D conversion.
Page 178 CHAPTER 10 8-BIT A/D CONVERTER Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 179 CHAPTER 10 8-BIT A/D CONVERTER 10.4 8-Bit A/D Converter Operation 10.4.1 Basic operation of 8-bit A/D converter <1> Bit 0 of A/D converter mode register 0 (ADML0) is set (ADCE0 = 1). <2> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). μ...
Page 180 CHAPTER 10 8-BIT A/D CONVERTER Figure 10-5. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCRL0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADML0) is reset (0) by software. If an attempt is made to write to ADML0 or analog input channel specification register 0 (ADS0) during A/D conversion, the A/D conversion in progress is canceled.
Page 181 CHAPTER 10 8-BIT A/D CONVERTER Figure 10-6. Relationship Between Analog Input Voltage and A/D Conversion Result A/D conversion result (ADCRL0) Input voltage/AV User’s Manual U15400EJ4V0UD...
Page 182 CHAPTER 10 8-BIT A/D CONVERTER 10.4.3 Operation mode of 8-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI7 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADML0).
Page 183 CHAPTER 10 8-BIT A/D CONVERTER 10.5 Cautions Related to 8-Bit A/D Converter <R> Power consumption in standby mode In standby mode, the A/D converter stops operation. Clearing bit 7 (ADCS0) and bit 0 (ADCE0) of A/D converter mode register 0 (ADML0) to 0 can reduce the power consumption. Figure 10-8 shows how to reduce the power consumption in standby mode.
Page 184 CHAPTER 10 8-BIT A/D CONVERTER Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 185 CHAPTER 10 8-BIT A/D CONVERTER Noise prevention To maintain a resolution of 8 bits, watch for noise at the AV and ANI0 to ANI7 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 10-11.
Page 186 CHAPTER 10 8-BIT A/D CONVERTER Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADML0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may be set for the previous analog input immediately before rewriting ADML0.
Page 187 CHAPTER 11 SERIAL INTERFACE 20 11.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 188 <R> Figure 11-1. Block Diagram of Serial Interface 20 Internal bus Serial operation mode Asynchronous serial interface Asynchronous serial interface register 20 (CSIM20) status register 20 (ASIS20) mode register 20 (ASIM20) Receive buffer CSIE20 DIR20 CSCK20 PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20 register 20 (RXB20) Switch of the first bit Transmit shift register...
Page 189 Figure 11-2. Block Diagram of Baud Rate Generator 20 Clock for receive detection Transmit clock counter Transmit shift clock (3 bits) Receive shift clock Receive clock counter (3 bits) TXE20 ASCK20/SCK20/P20 RXE20 CSIE20 Receive detection TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus...
Page 190 CHAPTER 11 SERIAL INTERFACE 20 Transmit shift register 20 (TXS20) TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20 triggers transmission.
Page 191 CHAPTER 11 SERIAL INTERFACE 20 11.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following six registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) •...
Page 192 CHAPTER 11 SERIAL INTERFACE 20 Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Figure 11-4.
Page 193 CHAPTER 11 SERIAL INTERFACE 20 Table 11-2. Serial Interface 20 Operation Mode Settings Operation stop mode ASIM20 CSIM20 PM22 PM21 PM20 First Shift P22/SI20/ P21/SO20/ P20/SCK20/ Clock RxD20 Pin TxD20 Pin ASCK20 Pin TXE20 RXE20 CSIE20 DIR20 CSCK20 Function Function Function ×...
Page 194 CHAPTER 11 SERIAL INTERFACE 20 Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 195 CHAPTER 11 SERIAL INTERFACE 20 Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 11-6. Format of Baud Rate Generator Control Register 20 Symbol Address After reset...
Page 196 CHAPTER 11 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal scaled obtained by dividing the clock input to the ASCK20 pin. (a) Generation of UART baud rate transmit/receive clock from system clock The transmit/receive clock is generated by dividing the system clock.
Page 197 CHAPTER 11 SERIAL INTERFACE 20 (b) Generation of UART baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 198 CHAPTER 11 SERIAL INTERFACE 20 11.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
Page 199 CHAPTER 11 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 200 CHAPTER 11 SERIAL INTERFACE 20 11.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates a UART-dedicated baud rate generator that enables communications at the desired baud rate.
Page 201 CHAPTER 11 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 202 CHAPTER 11 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS20 to 00H. Symbol <2> <1> <0> Address After reset ASIS20 PE20 FE20 OVE20 FF71H PE20...
Page 203 CHAPTER 11 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 Selection of baud rate generator source clock...
Page 204 CHAPTER 11 SERIAL INTERFACE 20 Table 11-5. Example of Relationship Between System Clock and Baud Rate Baud Rate (bps) BRGC20 Set Value Error (%) = 5.0 MHz = 4.9152 MHz 1,200 1.73 2,400 4,800 9,600 19,200 38,400 76,800 <R> Caution Do not select n = 1 when f >...
Page 205 CHAPTER 11 SERIAL INTERFACE 20 Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out using asynchronous serial interface mode register 20 (ASIM20).
Page 206 CHAPTER 11 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 207 CHAPTER 11 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 208 CHAPTER 11 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by BRGC20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 209 CHAPTER 11 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20).
Page 210 CHAPTER 11 SERIAL INTERFACE 20 (f) Reading receive data When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the value of receive buffer register 20 (RXB20). To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled (RXE20 = 1).
Page 211 CHAPTER 11 SERIAL INTERFACE 20 Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
Page 212 CHAPTER 11 SERIAL INTERFACE 20 11.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL, 78K, and 17K microcontrollers. Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 213 CHAPTER 11 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol <7>...
Page 214 CHAPTER 11 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 Selection of baud rate generator source clock...
Page 215 CHAPTER 11 SERIAL INTERFACE 20 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20).
Page 216 CHAPTER 11 SERIAL INTERFACE 20 Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing (CSCK20=1) SIO20 write SCK20 SI20 SO20 Note INTCSI20 Note The value of the last bit previously output is output. Transfer start Serial transfer is started by setting transfer data to transmit shift register 20 (TXS20/SIO20) when the following two conditions are satisfied.
Page 217 CHAPTER 12 SERIAL INTERFACE 1A0 12.1 Function of Serial Interface 1A0 Serial interface 1A0 has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function Operation stop mode This mode is used when serial transfer will not be performed.
Page 218 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-1. Block Diagram of Serial Interface 1A0 Automatic data transmit/receive Buffer RAM address pointer 0 (ADTP0) Internal bus Automatic data Automatic data transmit/receive Serial operation ATE0 transmit/receive interval specification mode register 1A0 control register 0 register 0 (ADTI0) (ADTC0) (CSIM1A0)
Page 219 CHAPTER 12 SERIAL INTERFACE 1A0 Serial I/O shift register 1A0 (SIO1A0) This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception in synchronization with the serial clock. SIO1A0 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is 1, writing data to SIO1A0 starts a serial operation.
Page 220 CHAPTER 12 SERIAL INTERFACE 1A0 12.3 Control Registers for Serial Interface 1A0 Serial interface 1A0 is controlled by the following five registers. • Serial operation mode register 1A0 (CSIM1A0) • Automatic data transmit/receive control register 0 (ADTC0) • Automatic data transmit/receive interval specification register 0 (ADTI0) •...
Page 221 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-2. Format of Serial Operation Mode Register 1A0 Symbol <7> <5> <4> Address After reset CSIM1A0 CSIE10 DIR10 ATE0 LSCK10 SCL101 SCL100 FF78H CSIE10 Specification of operation enable/disable Note Shift register operation Serial counter Port Operation stopped Cleared...
Page 222 CHAPTER 12 SERIAL INTERFACE 1A0 Automatic data transmit/receive control register 0 (ADTC0) This register sets automatic reception enable/disable, the operation mode, and displays the state of automatic transmit/receive control. ADTC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 223 CHAPTER 12 SERIAL INTERFACE 1A0 Automatic data transmit/receive interval specification register 0 (ADTI0) This register sets the automatic data transmit/receive function data transfer interval. ADTI0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 12-4.
Page 224 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (2/2) Symbol <7> <4> <3> <2> <1> <0> Address After reset ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 FF7BH ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification Note 2 = 5.0 MHz, f...
Page 225 CHAPTER 12 SERIAL INTERFACE 1A0 12.4 Serial Interface 1A0 Operation Serial interface 1A0 provides the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 12.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption.
Page 226 CHAPTER 12 SERIAL INTERFACE 1A0 12.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL, 78K, and 17K microcontrollers. Communication is performed using three lines: a serial clock (SCK10), serial output (SO10), and serial input (SI10).
Page 227 CHAPTER 12 SERIAL INTERFACE 1A0 Symbol <7> <5> <4> Address After reset CSIM1A0 CSIE10 DIR10 ATE0 LSCK10 SCL101 SCL100 FF78H CSIE10 Specification of operation enable/disable Note Shift register operation Serial counter Port Operation stopped Cleared Port function Operation enabled Count operation enabled Serial function + port function DIR10 Specification of first bit of serial transfer data...
Page 228 CHAPTER 12 SERIAL INTERFACE 1A0 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Serial I/O shift register 1A0 (SIO1A0) shift operations are performed in synchronization with the fall of the serial clock (SCK10).
Page 229 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-5. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing SIO1A0 write SCK10 SI10 SO10 Note INTCSI10 Note The value of the last bit previously output is output. User’s Manual U15400EJ4V0UD...
Page 230 CHAPTER 12 SERIAL INTERFACE 1A0 MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 12-6 shows the configuration of serial I/O shift register 1A0 (SIO1A0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 231 CHAPTER 12 SERIAL INTERFACE 1A0 12.4.3 3-wire serial I/O mode with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 16-byte data without the use of software. Once transfer is started, the set number of bytes of the data prestored in the RAM can be transmitted, and the set number of bytes of data can be received and stored in the RAM.
Page 232 CHAPTER 12 SERIAL INTERFACE 1A0 Symbol <7> <5> <4> Address After reset CSIM1A0 CSIE10 DIR10 ATE0 LSCK10 SCL101 SCL100 FF78H CSIE10 Specification of operation enable/disable Note Shift register operation Serial counter Port Operation stopped Cleared Port function Operation enabled Count operation enabled Serial function + port function DIR10 Specification of first bit of serial transfer data...
Page 233 CHAPTER 12 SERIAL INTERFACE 1A0 (b) Automatic data transmit/receive control register 0 (ADTC0) ADTC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Symbol <7> <6> <3> Address After reset Note 1 ADTC0 ARLD0 TRF0...
Page 234 CHAPTER 12 SERIAL INTERFACE 1A0 (c) Automatic data transmit/receive interval specification register 0 (ADTI0) ADTI0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Symbol <7> <4> <3> <2> <1> <0> Address After reset ADTI0 ADTI07...
Page 235 CHAPTER 12 SERIAL INTERFACE 1A0 Symbol <7> <4> <3> <2> <1> <0> Address After reset ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 FF7BH ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification Note 2 = 5.0 MHz, f = 1.25 MHz) μ...
Page 236 CHAPTER 12 SERIAL INTERFACE 1A0 Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FFA0H of buffer RAM (up to FFAFH). The transmit data should be in the order from higher address to lower address. <2>...
Page 237 CHAPTER 12 SERIAL INTERFACE 1A0 Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1.
Page 238 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-8. Basic Transmit/Receive Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger)
Page 239 CHAPTER 12 SERIAL INTERFACE 1A0 In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) are 0 and 1, respectively) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 12-9 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 240 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception FFAFH FFA5H Receive data 1 (R1) Receive data 4 (R4) SIO1A0 Receive data 2 (R2) Receive data 3 (R3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5)
Page 241 CHAPTER 12 SERIAL INTERFACE 1A0 (b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) is set to 0.
Page 242 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-11. Basic Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger)
Page 243 CHAPTER 12 SERIAL INTERFACE 1A0 In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) are 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 12-12 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 244 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FFAFH FFA5H Transmit data 1 (T1) SIO1A0 Transmit data 2 (T2) Transmit data 3 (T3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5) FFA0H Transmit data 6 (T6)
Page 245 CHAPTER 12 SERIAL INTERFACE 1A0 (c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1A0 (SIO1A0) when bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) is set to 0.
Page 246 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-14. Repeat Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger)
Page 247 CHAPTER 12 SERIAL INTERFACE 1A0 In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) are 1 and 0, respectively) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 12-15 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 248 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FFAFH FFA5H Transmit data 1 (T1) SIO1A0 Transmit data 2 (T2) Transmit data 3 (T3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5)
Page 249 CHAPTER 12 SERIAL INTERFACE 1A0 (d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) to 0. During 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE10) is set to 0. It is suspended upon completion of 8-bit data transfer.
Page 250 CHAPTER 12 SERIAL INTERFACE 1A0 Timing of interrupt request signal generation The interrupt request signal is generated in synchronization with the timing shown in Table 12-2. Table 12-2. Timing of Interrupt Request Signal Generation Operation Mode Timing of Interrupt Request Signal Single mode Master mode 10th serial clock at end of transfer...
Page 251 CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions μ The functions of the LCD controller/driver of the PD789479 Subseries are as follows. Automatic output of segment and common signals based on automatic display data memory read Two different display modes: •...
Page 252 CHAPTER 13 LCD CONTROLLER/DRIVER The correspondence with the LCD display RAM is shown in Figure 13-1 below. Figure 13-1. Correspondence with LCD Display RAM Address Segment → S27 Note FA1BH → S26 Note FA1AH → S25 Note FA19H → S24 Note FA18H →...
Page 253 Figure 13-2. LCD Controller/Driver Block Diagram Internal bus LCD clock control LCD display mode Display data memory register 0 (LCDC0) register 0 (LCDM0) FA00H ..FA0FH FA10H ..FA1BH LIPS0 LCDC03 LCDC02 LCDC01 LCDC00 LCDON0 LCDM00 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0...
Page 254 CHAPTER 13 LCD CONTROLLER/DRIVER 13.3 Registers Controlling LCD Controller/Driver The LCD controller/driver is controlled by the following two registers. • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display. It also specifies the segment/common pin output and display mode.
Page 255 CHAPTER 13 LCD CONTROLLER/DRIVER LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and number of time slices. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H.
Page 256 CHAPTER 13 LCD CONTROLLER/DRIVER 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the LCD clock using LCD clock control register 0 (LCDC0). <2> Set the time slice using LCDM00 (bit 0 of LCD display mode register 0 (LCDM0)). <3>...
Page 257 CHAPTER 13 LCD CONTROLLER/DRIVER 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V ). It turns off when the potential difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it.
Page 258 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-6 shows the common signal waveforms, and Figure 13-7 shows the voltages and phases of the common and segment signals. Figure 13-6. Common Signal Waveforms COMn (Three-time-slice mode) = 3 × T COMn (Four-time-slice mode) = 4 ×...
Page 259 CHAPTER 13 LCD CONTROLLER/DRIVER 13.7 Display Modes 13.7.1 Three-time-slice display example Figure 13-9 shows how a nine-digit LCD panel having the display pattern shown in Figure 13-8 is connected to the μ segment signals (S0 to S26) and the common signals (COM0 to COM2) of the PD789479 Subseries chip.
Page 260 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-9. Example of Connecting Three-Time-Slice LCD Panel COM 3 Open COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 S 15 S 16 FA10H S 17 S 18 S 19 S 20 S 21...
Page 261 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-10. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 +1/3V COM0-S9 −1/3V −V +1/3V COM1-S9 −1/3V −V +1/3V COM2-S9 −1/3V −V User’s Manual U15400EJ4V0UD...
Page 262 CHAPTER 13 LCD CONTROLLER/DRIVER 13.7.2 Four-time-slice display example Figure 13-12 shows how a 14-digit LCD panel having the display pattern shown in Figure 13-11 is connected to μ the segment signals (S0 to S27) and the common signals (COM0 to COM3) of the PD789479 Subseries chip.
Page 263 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-12. Example of Connecting Four-Time-Slice LCD Panel COM 3 COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 S 15 S 16 FA10H S 17 S 18 S 19 S 20 S 21...
Page 264 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-13. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 +1/3V COM0-S16 −1/3V −V +1/3V COM1-S16 −1/3V −V Remark The waveforms of COM2-S16 and COM3-S16 are not shown. User’s Manual U15400EJ4V0UD...
Page 265 CHAPTER 13 LCD CONTROLLER/DRIVER 13.8 Examples of LCD Drive Power Connections Since the µPD789479 Subseries employs a divider resistor system for generating LCD drive power, it requires external voltage divider resistors. Figure 13-14 shows an example of LCD drive power connections. The LCD drive voltage is supplied to V , and 2/3 and 1/3 of V are supplied to the V...
Page 266 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function. • Calculation of 8 bits × 8 bits = 16 bits 14.2 Multiplier Configuration 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed.
Page 267 CHAPTER 14 MULTIPLIER Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication data Multiplication data register A (MRA0) register B (MRB0) Counter value CPU clock Selector 3-bit counter Start Clear 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) MULST0...
Page 268 CHAPTER 14 MULTIPLIER 14.3 Multiplier Control Register The multiplier is controlled by the following register. • Multiplier control register 0 (MULC0) Multiplier control register 0 (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 269 CHAPTER 14 MULTIPLIER 14.4 Multiplier Operation The multiplier of the µPD789479 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1>...
Page 270 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.1 Remote Controller Receiver Functions The remote controller receiver uses the following remote controller modes. • Type A reception mode … Guide pulse (half clock) provided 15.2 Remote Controller Receiver Configuration The remote controller receiver includes the following hardware. Table 15-1.
Page 271 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-1. Block Diagram of Remote Controller Receiver <R> Noise Edge INTRIN RIN/P34 canceler detection Remote controller receive data register (RMDR) RMEN RMIN Clock Remote controller receive counter shift register (RMSR) Remote Compare register controller shift RMGPHL RMGPHS register receive...
Page 272 CHAPTER 15 REMOTE CONTROLLER RECEIVER (2) Remote controller receive data register (RMDR) This register holds the remote controller reception data. When the remote controller receive shift register (RMSR) overflows, the data in RMSR is transferred to RMDR. Bit 7 stores the last data, and bit 0 stores the first data.
Page 273 CHAPTER 15 REMOTE CONTROLLER RECEIVER (4) Remote controller receive GPHS compare register (RMGPHS) This register is used to detect the high level of a remote controller guide pulse (short side). RMGPHS is set with an 8-bit memory manipulation instruction. RESET input sets RMGPHS to 00H. (5) Remote controller receive GPHL compare register (RMGPHL) This register is used to detect the high level of a remote controller guide pulse (long side).
Page 274 CHAPTER 15 REMOTE CONTROLLER RECEIVER (8) Remote controller receive DH0S compare register (RMDH0S) This register is used to detect the high level of remote controller data 0 (short side). RMDH0S is set with an 8-bit memory manipulation instruction. RESET input sets RMDH0S to 00H. (9) Remote controller receive DH0L compare register (RMDH0L) This register is used to detect the high level of remote controller data 0 (long side).
Page 275 CHAPTER 15 REMOTE CONTROLLER RECEIVER (12) Remote controller receive end-width select register (RMER) This register determines the interval between the timing at which the INTREND signal is output. RMER is set with an 8-bit memory manipulation instruction. RESET input sets RMER to 00H. Data Counter value = RMER RMDLL...
Page 276 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.3 Registers to Control Remote Controller Receiver The remote controller receiver is controlled by the following register. • Remote controller receive control register (RMCN) (1) Remote controller receive control register (RMCN) This register is used to enable/disable remote controller reception and to set the noise elimination width, clock internal division, input invert signal, and source clock.
Page 277 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-3. Format of Remote Controller Receive Control Register (2/2) <R> Symbol Address After reset RMCN RMEN PRSEN RMIN RMCK1 RMCK0 FF60H RMCK1 RMCK0 Selection of source clock (f ) of remote controller counter (62.5 kHz) (31.3 kHz) (15.6 kHz) (32.768 kHz)
Page 278 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.4 Operation of Remote Controller Receiver The following remote controller reception mode is used for this remote controller receiver. • Type A reception mode with guide pulse (half clock) 15.4.1 Format of type A reception mode Figure 15-4 shows the data format for type A.
Page 279 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-5. Operation Flow of Type A Reception Mode Start Set compare registers Operation enabled (RMEN = 1) Guide pulse high level width OK? Generate INTGP Data low level width OK? Generate INTRERR Note Clear RMSR and RMSCR Read RMDR Data high level...
Page 280 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.4.3 Timing Operation varies depending on the positions of the PIN input waveform below. (1) Guide pulse high level width determination <1> <2> <3> RMGPHS RMGPHL Allowable range Relationship Between Position of Waveform Corresponding Operation RMGPHS/RMGPHL/Counter Counter <...
Page 281 CHAPTER 15 REMOTE CONTROLLER RECEIVER (3) Data high level width determination <1> <3> <2> <4> <5> RMDH0S RMDH0L RMDH1S RMDH1L Allowable Allowable range range Δ Relationship Between Position of Waveform Corresponding Operation RMDH0S/RMDH0L/RMDH1S/RMDH1L/Counter Counter < RMDH0S <1>: Short Error interrupt INTRERR is generated. Measuring the guide pulse high-level width is started at the next rising edge.
Page 282 CHAPTER 15 REMOTE CONTROLLER RECEIVER (4) End width determination <1> <2> RMDLS RMDLL RMER Δ Relationship Between RMER/Counter Position of Waveform Corresponding Operation Counter < RMER <1>: Short Error interrupt INTRERR is generated. Measuring the guide pulse high-level width is started. RMER ≤...
Page 283 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-6. Setting Example (Where n1 = 1, n2 = 2) Clock RMGPHS/RMDH0S/RMDH1S RMDLS RMER RMDLL RMGPHL/RMDH0L/RMDH1L RIN_1 RIN_2 (1) Formula for RMGPHS, RMDLS, RMDH0S, and RMDH1S × (1 − a/100) − 2 − n1 (2) Formula for RMGPHL, RMDLL, RMDH0L, and RMDH1L ×...
Page 284 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.4.5 Error interrupt generation timing After the guide pulse has been detected normally, the INTRERR signal is generated under any of the following conditions. • Counter < RMDLS at the rising edge of RIN • RMDLL ≤ counter and counter after RMDLL < RMER at the rising edge of RIN •...
Page 285 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-7. Generation Timing of INTRERR Signal RMDLL RMDH1L RMGPHL RMDH1S RMER RMDLS RMDH0L RMGPHS RMDH0S Basic waveform INTRERR Example 1 Counter < RMGPHS → INTRERR is not generated. INTRERR Example 2 RMGPHL ≤ counter →...
Page 286 CHAPTER 15 REMOTE CONTROLLER RECEIVER 15.4.6 Noise elimination This remote controller receiver provides a function that supplies the signals input from the outside to the RIN pin after eliminating noise. Noise width can be eliminated by setting bit 5 (PRSEN) and bit 6 (NCW) of the remote controller receive control register (RMCN) as shown in Figure 15-2.
Page 287 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-8. Noise Elimination Operation Example (1/2) (a) 1-clock noise elimination (PRSEN = 0, NCW = 0) Clock RIN (ideal) Noise Synchronization samp1 samp2 Since synchronized signal = samp1 = H is not satisfied, samp1 is not latched. Internal RIN Delayed by 2 to 3 clocks Remark...
Page 288 CHAPTER 15 REMOTE CONTROLLER RECEIVER Figure 15-8. Noise Elimination Operation Example (2/2) (c) 2-clock noise elimination (PRSEN = 1, NCW = 0) Clock Clock divider RIN (ideal) Noise Synchronization samp1 Since synchronized signal = samp1 = H is not satisfied, samp1 is samp2 not latched.
Page 289 CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 290 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Sources Interrupt Type Default Interrupt Source Internal/ Vector Table Basic Note 1 Priority External Address Configuration Name Trigger Note 2 Type − Non-maskable INTWDT Watchdog timer overflow (with Internal 0004H watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow (with...
Page 291 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1,...
Page 292 CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 to IF2) • Interrupt mask flag registers (MK0 to MK2) • External interrupt mode registers (INTM0 and INTM1) •...
Page 293 CHAPTER 16 INTERRUPT FUNCTIONS Interrupt request flag registers (IF0 to IF2) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed.
Page 294 CHAPTER 16 INTERRUPT FUNCTIONS Interrupt mask flag registers (MK0 to MK2) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 to MK2 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 16-3.
Page 295 CHAPTER 16 INTERRUPT FUNCTIONS External interrupt mode registers (INTM0, INTM1) These registers are used to specify the valid edge for INTP0 to INTP3. INTM0 and INTM1 are set with an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 16-4.
Page 296 CHAPTER 16 INTERRUPT FUNCTIONS Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read and written in 8-bit units, and can be manipulated by using bit manipulation instructions and dedicated instructions (EI and DI).
Page 297 CHAPTER 16 INTERRUPT FUNCTIONS Key return mode register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (falling edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 298 CHAPTER 16 INTERRUPT FUNCTIONS μ Key return mode register 01 (KRM01) ( PD789479 and 78F9479 only) This register is used to set the pin that is to detect the key return signal (falling edge of port 6). KRM01 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 299 CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operation 16.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded the PC, and then program execution branches.
Page 300 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT:...
Page 301 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 302 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-14. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Saving PSW and PC, and MOV A, r Interrupt servicing program jump to interrupt servicing Interrupt If the interrupt request has generated an interrupt request flag (××IF×) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n −...
Page 303 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-16. Example of Multiple Interrupt Servicing Example 1. Acknowledging multiple interrupts INTxx servicing INTyy servicing Main servicing IE = 0 IE = 0 INTxx INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupt servicing is performed.
Page 304 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
Page 305 CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 306 CHAPTER 17 STANDBY FUNCTION 17.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request generation until oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 307 CHAPTER 17 STANDBY FUNCTION 17.2 Standby Function Operation 17.2.1 HALT mode HALT mode The HALT mode is set by executing the HALT instruction. The operation statuses in the HALT mode are shown in the following table. Table 17-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status During Main HALT Mode Operation Status During Subsystem...
Page 308 CHAPTER 17 STANDBY FUNCTION Releasing HALT mode The HALT mode can be released by the following three sources. Release by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed.
Page 309 CHAPTER 17 STANDBY FUNCTION Release by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 17-3. Releasing HALT Mode by RESET Input Wait HALT : 6.55 ms)
Page 310 CHAPTER 17 STANDBY FUNCTION 17.2.2 STOP mode Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 311 CHAPTER 17 STANDBY FUNCTION Releasing STOP mode The STOP mode can be released by the following two sources. Release by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed.
Page 312 CHAPTER 17 STANDBY FUNCTION Release by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 17-5. Releasing STOP Mode by RESET Input Wait STOP : 6.55 ms) instruction RESET...
Page 313 CHAPTER 18 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer program loop time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 314 CHAPTER 18 RESET FUNCTION Figure 18-2. Reset Timing by RESET Input Oscillation During normal Reset period Normal operation stabilization operation (oscillation stops) (reset processing) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 18-3. Reset Timing by Overflow in Watchdog Timer Oscillation Reset period During normal...
Page 315 CHAPTER 18 RESET FUNCTION Table 18-1. Status of Hardware After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose registers...
Page 316 CHAPTER 18 RESET FUNCTION Table 18-1. Status of Hardware After Reset (2/2) Hardware Status After Reset Serial interface 1A0 Operation mode register (CSIM1A0) Shift register (SIO1A0) Buffer memory (SBMEM0 to SBMEMF) Undefined Automatic data transmit/receive control register (ADTC0) Automatic data transmit/receive address pointer (ADTP0) Undefined Automatic data transmit/receive transfer interval specification register (ADTI0) A/D converter...
Page 317 CHAPTER 19 FLASH MEMORY VERSION μ μ PD78F9478 is available as the flash memory version of the PD789477 and 789478 (mask ROM versions). μ μ PD78F9479 is available as the flash memory version of the PD789479 (mask ROM version). μ The differences between the PD78F9478, 78F9479 and the mask ROM versions are shown in Table 19-1.
Page 318 CHAPTER 19 FLASH MEMORY VERSION 19.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- μ PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the PD78F9478 or 78F9479 mounted on the target system (on-board).
Page 319 CHAPTER 19 FLASH MEMORY VERSION 19.1.2 Communication mode Use the communication mode shown in Table 19-2 to perform communication between the dedicated flash μ μ programmer and PD78F9478 or PD78F9479. Table 19-2. Communication Mode List Note 1 Communication TYPE Setting Pins Used Number of Pulses...
Page 320 CHAPTER 19 FLASH MEMORY VERSION Figure 19-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O μ Dedicated flash programmer PD78F9478, 78F9479 VPP1 RESET RESET SCK20 SI20 SO20 Note 1 (b) 3-wire serial I/O with handshake μ Dedicated flash programmer PD78F9478, 78F9479 VPP1 RESET...
Page 321 CHAPTER 19 FLASH MEMORY VERSION If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash μ programmer, the following signals are generated for the PD78F9478 and 78F9479. For details, refer to the manual of Flashpro III/Flashpro IV.
Page 322 CHAPTER 19 FLASH MEMORY VERSION 19.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases.
Page 323 CHAPTER 19 FLASH MEMORY VERSION Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 324 CHAPTER 19 FLASH MEMORY VERSION <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed.
Page 325 CHAPTER 19 FLASH MEMORY VERSION 19.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 19-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O VDD (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 μ...
Page 326 CHAPTER 19 FLASH MEMORY VERSION <R> Figure 19-9. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O with Handshake VDD (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 μ...
Page 327 CHAPTER 19 FLASH MEMORY VERSION Figure 19-10. Wiring Example for Flash Writing Adapter with UART VDD (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 μ...
Page 328 CHAPTER 19 FLASH MEMORY VERSION μ 19.2 Cautions on PD78F9478 and 78F9479 When using HALT mode with subclock multiplied by four μ Observe the following constraints when using the flash version ( PD78F9478 and 78F9479) in the HALT mode with the subclock multiplied by 4 as the CPU clock. •...
Page 329 CHAPTER 20 MASK OPTIONS μ PD789477, 789478, and 789479 have the following mask options. • Pin function The segment pins of the LCD and port 7 (input port) can be selected in 1-bit units. <1> S (16 + n) <2> P7n (n = 0 to 3) The segment pins of the LCD and port 8 (I/O port) can be selected in 1-bit units.
Page 330 CHAPTER 21 INSTRUCTION SET μ This chapter lists the instruction set of the PD789479 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 21.1 Operation 21.1.1 Operand identifiers and description methods Operands are described in the “Operand”...
Page 331 CHAPTER 21 INSTRUCTION SET 21.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 332 CHAPTER 21 INSTRUCTION SET 21.2 Operation List Mnemonic Operands Bytes Clocks Operation Flag Z AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 333 CHAPTER 21 INSTRUCTION SET Mnemonic Operands Bytes Clocks Operation Flag Z AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 334 CHAPTER 21 INSTRUCTION SET Mnemonic Operands Bytes Clocks Operation Flag Z AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...
Page 335 CHAPTER 21 INSTRUCTION SET Mnemonic Operands Bytes Clocks Operation Flag Z AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...
Page 336 CHAPTER 21 INSTRUCTION SET Mnemonic Operands Bytes Clocks Operation Flag Z AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 337 CHAPTER 21 INSTRUCTION SET 21.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr [DE] [HL] None !addr16 [HL+byte] $addr16 1st Operand Note ADDC...
Page 338 CHAPTER 21 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 339 CHAPTER 21 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U15400EJ4V0UD...
Page 340 CHAPTER 22 ELECTRICAL SPECIFICATIONS <R> Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Power supply voltage = AV –0.3 to +6.5 μ Note 1 PD78F9478, 78F9479 only –0.3 to +10.5 Note 3 Input voltage P00 to P07, P10, P11, P20 to P25, P30 to –0.3 to V + 0.3 Note 2...
Page 341 CHAPTER 22 ELECTRICAL SPECIFICATIONS Notes 1. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. • When supply voltage rises must exceed V 10 µs or more after V has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below).
Page 342 CHAPTER 22 ELECTRICAL SPECIFICATIONS Main System Clock Oscillator Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Note 1 Ceramic Oscillation frequency (f resonator Oscillation stabilization After V reaches Note 2 time...
Page 343 CHAPTER 22 ELECTRICAL SPECIFICATIONS Subsystem Clock Oscillator Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation frequency 32.768 Note 1 resonator Oscillation stabilization = 4.5 to 5.5 V Note 2 time = 1.8 to 5.5 V...
Page 344 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (1/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin All pins Output current, high Per pin –1 All pins –15 Input voltage, high P10, P11, P60 to P67...
Page 345 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (2/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ Input leakage current, P00 to P07, P10, P11, LIH1 high P20 to P25, P30 to P34, P60 to P67, P70 to Note 1 Note 1...
Page 346 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (3/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation Note 1 current operation mode = 3.0 V ±10% Note 3...
Page 347 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (4/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation Note 1 current operation mode = 3.0 V ±10% Note 3...
Page 348 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (5/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation Note 1 current operation mode = 3.0 V ±10% Note 3...
Page 349 CHAPTER 22 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (6/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation 12.0 Note 1 current operation mode = 3.0 V ±10%...
Page 350 CHAPTER 22 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ Cycle time (minimum Operating with main system = 2.7 to 5.5 V instruction execution clock μ...
Page 351 CHAPTER 22 ELECTRICAL SPECIFICATIONS (2) Serial interface 20 (SIO20) (T = –40 to +85°C, V = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time = 2.7 to 5.5 V KCY1 = 1.8 to 5.5 V 3200...
Page 352 CHAPTER 22 ELECTRICAL SPECIFICATIONS (d) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time = 2.7 to 5.5 V KCY3 = 1.8 to 5.5 V 3200 ASCK20 high-/low-level = 2.7 to 5.5 V width = 1.8 to 5.5 V 1600 Transfer rate...
Page 353 CHAPTER 22 ELECTRICAL SPECIFICATIONS (3) Serial interface 1A0 (SIO1A0) (T = –40 to +85°C, V = 1.8 to 5.5 V) (a) 3-wire serial I/O mode, 3-wire serial I/O mode with automatic transmit/receive function (internal clock output) Parameter Symbol Conditions MIN. TYP.
Page 354 CHAPTER 22 ELECTRICAL SPECIFICATIONS AC Timing Measurement Points (Excluding X1 and XT1 Inputs) 0.8V 0.8V Point of measurement 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) Capture Input Timing CPTH CPTL CPT20 TMI Timing TMI60, TMI61 Interrupt Input Timing INTL INTH...
Page 355 CHAPTER 22 ELECTRICAL SPECIFICATIONS Key Return Input Timing KR0 to KR7 μ ( PD789477, 789478, 78F9478) KR00 to KR07, KR10 to KR17 μ ( PD789479, 78F9479) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10, SCK20 SIKm KSIm SI10, SI20...
Page 356 CHAPTER 22 ELECTRICAL SPECIFICATIONS 8-Bit A/D Converter Characteristics = –40 to +85°C, 1.8 V ≤ AV ≤ 5.5 V, AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±0.6 Note 1 Overall error = 2.7 to 5.5 V %FSR ±1.2 = 1.8 to 5.5 V...
Page 357 CHAPTER 22 ELECTRICAL SPECIFICATIONS Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T = –40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention power DDDR supply voltage μ Release signal set time SREL Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode...
Page 358 CHAPTER 22 ELECTRICAL SPECIFICATIONS μ Writing and Erasing Characteristics (T = 10 to 40°C, V = 1.8 to 5.5 V) ( PD78F9478, 78F9479 only) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write operation frequency = 2.7 to 5.5 V = 1.8 to 5.5 V 1.25 Note Write current (V...
Page 359 CHAPTER 23 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20...
Page 360 CHAPTER 23 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 14.0±0.2 its true position (T.P.) at maximum material condition. 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 361 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS μ PD789479 subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Page 362 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS Table 24-1. Surface Mounting Type Soldering Conditions (2/3) μ PD78F9479GC-8BT: 80-pin plastic QFP (14x14) Soldering Method Soldering Conditions Recommended Condition Symbol Interface reflow Package peak temperature: 235°C, Time:30 seconds max. (at 210°C or higher), IR35-107-2 Note Count: Twice or less, Exposure limit: 7 days (after that, prebake at 125°C for...
Page 363 Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative.
Page 364 APPENDIX A DEVELOPMENT TOOLS μ The following development tools are available for development of systems using the PD789479 Subseries. Figure A-1 shows development tools. • Support for PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX Series.
Page 365 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package · Software package Language processing software Debugging software · Assembler package · Integrated debugger · · C compiler package System simulator · Device file · Note 1 C library source file Control software ·...
Page 366 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software tools for development of the 78K/0S microcontrollers are combined in this package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files μ Part number: S××××SP78K0S ×××× in the part number differs depending on the OS used Remark μ...
Page 367 APPENDIX A DEVELOPMENT TOOLS ×××× in the part number differs depending on the host machine and operating system to be used. Remark μ S××××RA78K0S μ S××××CC78K0S ×××× Host Machine Supply Medium AB13 PC-9800 series, Japanese Windows 3.5" 2HD FD IBM PC/AT compatible BB13 English Windows AB17...
Page 368 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of an application system using the In-circuit emulator 78K/0S microcontrollers. Can be used with the integrated debugger ID78K0S-NS. Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine.
Page 369 APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the Integrated debugger 78K/0S microcontrollers. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 370 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figures B-1 to B-6 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Page 371 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When NP-80GC-TQ Is Used) Emulation board IE-789488-NS-EM1 Emulation probe NP-80GC-TQ 24.8 mm Conversion adapter TGC-080SBP 11 mm 25 mm 21 mm 21 mm 40 mm 34 mm Target system Figure B-3.
Page 372 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (2) NP-80GK, NP-H80GK-TQ Figure B-4. Distance Between In-Circuit Emulator and Conversion Adapter (80GK) In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789488-NS-EM1 Note 170 mm Emulation probe Conversion adapter NP-80GK, NP-H80GK-TQ TGK-080SDW Note When NP-H80GK-TQ is used, the distance is 370 mm.
Page 373 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-5. Connection Conditions of Target System (When NP-80GK Is Used) Emulation board IE-789488-NS-EM1 Emulation probe NP-80GK 24.8 mm Conversion adapter TGK-080SDW 11 mm 25 mm 18 mm 18 mm 40 mm 34 mm Target system Figure B-6.
Page 374 APPENDIX C REGISTER INDEX C.1 Register Index (Register Names in Alphabetic Order) A/D conversion result register 0 (ADCRL0).........................174 A/D converter mode register 0 (ADML0) ........................176 A/D converter mode register 1 (ADML1) ........................177 Analog input channel specification register 0 (ADS0)....................178 Asynchronous serial interface mode register 20 (ASIM20) ..................192 Asynchronous serial interface status register 20 (ASIS20) ..................194 Automatic data transmit/receive address pointer 0 (ADTP0)..................219 Automatic data transmit/receive control register 0 (ADTC0) ..................222...
Page 375 APPENDIX C REGISTER INDEX Key return mode register 01 (KRM01) ........................298 LCD clock control register 0 (LCDC0) .........................255 LCD display mode register 0 (LCDM0) ........................254 Multiplication data register A0 (MRA0)........................266 Multiplication data register B0 (MRB0)........................266 Multiplier control register 0 (MULC0)...........................268 Oscillation stabilization time selection register (OSTS) ....................306 Port 0 (P0) ..................................77 Port 1 (P1) ..................................78...
Page 376 APPENDIX C REGISTER INDEX Remote controller receive GPHS compare register (RMGPHS)..................273 Remote control receive shift register (RMSR) ......................271 Remote controller shift register receive counter register (RMSCR)................272 16-bit capture register 20 (TCP20) ..........................109 16-bit compare register 20 (CR20) ..........................109 16-bit multiplication result storage register H (MUL0H) ....................266 16-bit multiplication result storage register L (MUL0L) ....................266 16-bit timer counter 20 (TM20)............................109 16-bit timer mode control register 20 (TMC20)......................110...
Page 377 C.2 Register Index (Register Symbols in Alphabetic Order) ADCRL0: A/D conversion result register 0 ......................174 ADML0: A/D converter mode register 0 ........................176 ADML1: A/D converter mode register 1 ........................177 ADS0: Analog input channel specification register 0 ..................178 ADTC0: Automatic data transmit/receive control register 0...................222 ADTI0: Automatic data transmit/receive interval specification register 0 .............223 ADTP0:...
Page 378 APPENDIX C REGISTER INDEX MUL0H: 16-bit multiplication result storage register H...................266 MUL0L: 16-bit multiplication result storage register L ...................266 MULC0: Multiplier control register 0........................268 OSTS: Oscillation stabilization time selection register..................306 Port 0................................ 77 Port 1................................ 78 Port 2................................ 79 Port 3................................ 84 Port 5................................
Page 379 APPENDIX C REGISTER INDEX SSCK: Subclock selection register........................100 TCA60: Carrier generator output control register 60 ....................131 TCP20: 16-bit capture register 20 ........................109 TM20: 16-bit timer counter 20 ..........................109 TM50: 8-bit timer counter 50 ..........................127 TM60: 8-bit timer counter 60 ..........................127 TM61: 8-bit timer counter 61 ..........................127 TMC20:...
Page 380 APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/2) Page Description Classification CHAPTER 1 OUTLINE p. 25 Change of 1.3 Ordering Information p. 29 Change of 1.5 78K/0S Series Lineup CHAPTER 4 PORT FUNCTIONS p. 77 Modification of Figure 4-2. Block Diagram of P00 to P07 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 60, AND 61 p.
Page 381 APPENDIX D REVISION HISTORY (2/2) Page Description Classification CHAPTER 11 SERIAL INTERFACE 20 p. 200 Addition of Caution 2 to (a) of 11.4.2 Asynchronous serial interface (UART) mode p. 203 Change of Cautions 2 and 3 in (d) of 11.4.2 Asynchronous serial interface (UART) mode p.
Page 382 APPENDIX D REVISION HISTORY D.2 Revision History of Preceding Editions The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/2) Edition Major Revision from Previous Edition Applied to: μ...
Page 383 APPENDIX D REVISION HISTORY (2/2) Edition Major Revision from Previous Edition Applied to: μ Addition of PD789479 and 78F9479 Throughout Addition of 80-pin plastic TQFP (fine pitch) (12 ×12) Update of series lineup diagram in 1.5 78K/0S Series Lineup CHAPTER 1 GENERAL Addition of Table 3-3 Internal High-Speed RAM, Internal Low-Speed RAM CHAPTER 3 CPU Capacity...
Page 384 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

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