Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
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The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Major Revisions in This Edition Page Description P.87 Addition of Caution regarding setting values for memory size switching register to 5.1 Memory Spaces P.161, 162 Change and addition of Caution to 8.3 16-bit Timer/Event Counter Configuration (2) Capture/ compare register00(CR00), (3) Capture/compare register01(CR01) P.163 Change in Figure 8-2 16-bit Timer Mode Control Register (TMC0) Format P.164...
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INTRODUCTION Readers This manual has been prepared for user engineers who understand the functions of the µ PD780024, 780034, 780024Y, and 780034Y Subseries and wish to design and develop application systems and programs for these devices. µ PD780024 Subseries : µ PD780021, 780022, 780023, 780024 µ...
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How To Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. • For readers who use this as an (A) product: → Standard products differ from (A) products in their quality grade only. Re-read the product name as indicated below if your products is an (A) product.
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Chapter Organization This manual divides the descriptions for the subseries into different chapters as shown below. Read only the chapters related to the device you use. µ PD780024 µ PD780034 µ PD780024Y µ PD780034Y Chapter Subseries Subseries Subseries Subseries Outline ( µ PD780024, 780034 Subseries) Chapter 1 —...
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Differences between µ PD780024, 780034 Subseries and µ PD780024Y, 780034Y Subseries: The µ PD780024, 780034 Subseries and µ PD780024Y, 780034Y Subseries are different in the following functions of the serial interface channel 0. µ PD780024, 780034 Subseries µ PD780024Y, 780034Y Subseries Serial Interface 3-wire serial I/O mode 2 ch (SIO30, SIO31)
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for µ PD780024 Subseries Document No. Document name Japanese English µ PD780021, 780022, 780023, 780024 Data Sheet U12299J U12299E µ...
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• Related documents for µ PD780034 Subseries Document No. Document name Japanese English µ PD780031, 780032, 780033, 780034 Data Sheet U12300J U12300E µ PD78F0034 Data Sheet U11993J U11993E µ PD780024, 780034, 780024Y, 780034Y Subseries User’s Manual U12022J This manual 78K/0 Series User’s Manual-Instructions U12326J U12326E 78K/0 Series Instruction Applications Table...
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• Related documents for development tool (User’s Manuals) Document No. Document name Japanese English RA78K0 Assembler Package Operation U11802J U11802E Language U11801J U11801E Structured Assembly Language U11789J U11789E RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402 CC78K0 C Compiler Operation U11517J U11517E Language U11518J...
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Japanese English IC PACKAGE MANUAL C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
CONTENTS CHAPTER 1 OUTLINE ( µ PD780024, 780034 SUBSERIES) ............1.1 Features ..........................1.2 Applications ......................... 1.3 Ordering Information ......................1.4 Quality Grade ........................1.5 Pin Configuration (Top View) ....................1.6 78K/0 Series Expansion ...................... 1.7 Block Diagram ........................1.8 Outline of Function ......................1.9 Difference between Standard Grade and Special Grade ..........
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3.2.16 V and V ..........................3.2.17 V (flash memory versions only) ....................3.2.18 IC (mask ROM version only) ...................... 3.3 Pin Input/output Circuits and Recommended Connection of Unused Pins ....CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) ........4.1 Pin Function List ........................
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5.4.2 Register addressing ........................5.4.3 Direct addressing ........................5.4.4 Short direct addressing ......................5.4.5 Special-function register (SFR) addressing ................5.4.6 Register indirect addressing ....................... 5.4.7 Based addressing ........................5.4.8 Based indexed addressing ......................5.4.9 Stack addressing ........................CHAPTER 6 PORT FUNCTIONS ..................... 121 6.1 Port Functions ........................
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CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS ........223 12.1 Clock Output/Buzzer Output Control Circuit Functions ..........223 12.2 Clock Output/Buzzer Output Control Circuit Configuration ..........224 12.3 Register to Control Clock Output/Buzzer Output Control Circuit ........224 12.4 Clock Output/Buzzer Output Control Circuit Operations ..........227 12.4.1 Operation as clock output ......................
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17.4 Serial Interface Operations ....................289 17.4.1 Operation stop mode ........................17.4.2 3-wire serial I/O mode ........................ CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) .... 293 18.1 Serial Interface Functions ....................293 18.2 Serial Interface Configuration ..................... 296 18.3 Registers to Control Serial Interface ..................
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CHAPTER 21 STANDBY FUNCTION ....................381 21.1 Standby Function and Configuration ................381 21.1.1 Standby function ........................21.1.2 Standby function control register ....................21.2 Standby Function Operations ..................... 383 21.2.1 HALT mode ..........................21.2.2 STOP mode ..........................CHAPTER 22 RESET FUNCTION ....................389 22.1 Reset Function ........................
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LIST OF FIGURES (1/5) Figure No. Title Page Pin Input/Output Circuit of List ......................Pin Input/Output Circuit of List ......................Memory Map ( µ PD780021, 780031, 780021Y, 780031Y) ..............Memory Map ( µ PD780022, 780032, 780022Y, 780032Y) ..............Memory Map ( µ PD780023, 780033, 780023Y, 780033Y) ..............Memory Map ( µ...
LIST OF FIGURES (2/5) Figure No. Title Page 16-Bit Timer/Event Counter Block Diagram ..................16-Bit Timer Mode Control Register (TMC0) Format ................ Capture/Compare Control Register 0 (CRC0) Format ..............16-Bit Timer Output Control Register L (TOC0) Format ..............Prescaler Mode Register 0 (PRM0) Format ..................Port Mode Register 7 (PM7) Format ....................
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LIST OF FIGURES (3/5) Figure No. Title Page External Event Counter Operation Timings (with Rising Edge Specified) ........Square-wave Output Operation Timing .................... 9-10 PWM Output Operation Timing ......................9-11 Timing of Operation by Change of CR5n ..................9-12 16-Bit Resolution Cascade Connection Mode .................. 9-13 8-Bit Counters Start Timing .......................
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LIST OF FIGURES (4/5) Figure No. Title Page 14-9 Example of Method of Reducing Current Consumption in Standby Mode ........14-10 Analog Input Pin Connection ......................14-11 A/D Conversion End Interrupt Request Generation Timing .............. 14-12 Pin Connection ........................16-1 Serial Interface (UART0) Block Diagram ..................
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LIST OF FIGURES (5/5) Figure No. Title Page 19-3 Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format ............19-4 Priority Specify Flag Register (PR0L, PR0H, PR1L) Format ............19-5 External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format ........................
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LIST OF TABLES (1/2) Table No. Title Page Mask Options of Mask ROM Versions ....................Mask Options of Mask ROM Versions ....................Pin Input/Output Circuit Types ......................Pin Input/Output Circuit Types ......................Internal ROM Capacity ........................Vector Table ............................Internal High-Speed RAM Capacity ....................Internal High-Speed RAM Area ......................
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LIST OF TABLES (2/2) Table No. Title Page 14-1 A/D Converter Configuration ......................Differences between µ PD780024, 780034 Subseries and µ PD780024Y, 780034Y Subseries ..15-1 16-1 Serial Interface (UART0) Configuration .................... 16-2 Relationship between 5-Bit Counter’s Source Clock and “n” Value ..........16-3 Relationship between Main System Clock and Baud Rate ...............
64-pin plastic LQFP (12 × 12 mm) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grades on the devices and its recommended applications.
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64-pin plastic LQFP (12 × 12 mm) Standard Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grades on the devices and its recommended applications.
CHAPTER 1 OUTLINE ( µ PD780024, 780034 SUBSERIES) 1.6 78K/0 Series Expansion 78K/0 Series expansion is shown below. The names in frames are subseries. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
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CHAPTER 1 OUTLINE ( µ PD780024, 780034 SUBSERIES) Major differences among those subseries are indicated below. Function Timer 8-bit 10-bit 8-bit External Serial Interface Capacity MIN. value extension Subseries 8-bit 16-bit Watch WDT µ PD78075B 32 K to 40 K 4 ch √...
CHAPTER 1 OUTLINE ( µ PD780024, 780034 SUBSERIES) 1.9 Difference between Standard Grade and Special Grade Standard Grade : µ PD780021, 780022, 780023, 780024 µ PD780031, 780032, 780033, 780034, 78F0034 : µ PD780021(A), 780022(A), 780023(A), 780024(A) Special Grade µ PD780031(A), 780032(A), 780033(A), 780034(A) The standard and the special grade differ only in the quality level.
64-pin plastic LQFP (12 × 12 mm) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grades on the devices and its recommended applications.
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64-pin plastic LQFP (12 × 12 mm) Standard Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grades on the devices and its recommended applications.
CHAPTER 2 OUTLINE ( µ PD780024Y, 780034Y SUBSERIES) 2.6 78K/0 Series Expansion 78K/0 Series expansion is shown below. The names in frames are subseries. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
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CHAPTER 2 OUTLINE ( µ PD780024Y, 780034Y SUBSERIES) The major differences among Y subseries are indicated below. Function ROM Capacity Serial Interface Configuration Subseries MIN. value µ PD78078Y Control 48 K to 60 K 3-wire/2-wire/I : 1 ch 1.8 V 3-wire with auto-transmit/receive : 1 ch µ...
CHAPTER 2 OUTLINE ( µ PD780024Y, 780034Y SUBSERIES) 2.9 Difference between Standard Grade and Special Grade Standard Grade : µ PD780021Y, 780022Y, 780023Y, 780024Y µ PD780031Y, 780032Y, 780033Y, 780034Y, 78F0034Y : µ PD780021Y(A), 780022Y(A), 780023Y(A), 780024Y(A) Special Grade µ PD780031Y(A), 780032Y(A), 780033Y(A), 780034Y(A) The standard and the special grade differ only in the quality level.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.1 Pin Function List (1) Port Pins (1/2) Alternate Pin Name Input/Output Function After Reset Function Input/Output Port 0 Input INTP0 4-bit input/output port INTP1 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up resistor can be used by software.
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CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) (1) Port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function Input/Output Input TI00/TO0 Port 7 6-bit input/output port TI01 Input/output mode can be specified bit-wise. TI50/TO50 If used as an input port, an on-chip pull-up resistor can be used by software.
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CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) (2) Non-port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function WAIT Input Wait insertion when accessing external memory Input ASTB Output Strobe output externally latching address information Input output to ports 4, 5 to access external memory ANI0 to ANI7 Input A/D converter analog input...
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P03 (Port 0) These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt input, and A/D converter external trigger input. The following operating modes can be specified bit-wise.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.2.3 P20 to P25 (Port 2) These are 6-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/from the serial interface and clock input/output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 6-bit input/output ports.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The interrupt request flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified bit-wise.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.2.8 P70 to P75 (Port 7) These are 6-bit input/output ports. Besides serving as input/output ports, they function as a timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 6-bit input/output port.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.2.12 RESET This is a low-level active system reset input pin. 3.2.13 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input clock signal to X1 and its inverted signal to X2.
CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) 3.3 Pin Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the types of pin input/output circuit and the recommended connections of unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
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CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/output circuit type Input/output Recommended connection of unused pins P50/A8 to P57/A15 Input/output Independently connect to V or V via a resistor. P64/RD Input/output P65/WR...
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CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) Figure 3-1 Pin Input/Output Circuit of List (1/2) TYPE 2 TYPE 13-P IN/OUT data N-ch output disable Schmitt-Triggered Input with Hysteresis Characteristics input enable TYPE 5-H TYPE 13-Q Mask ...
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CHAPTER 3 PIN FUNCTION ( µ PD780024, 780034 SUBSERIES) Figure 3-1 Pin Input/Output Circuit of List (2/2) TYPE 13-S TYPE 25 Mask Option IN/OUT P-ch data Comparator N-ch output disable – N-ch (threshold voltage) input enable TYPE 16...
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.1 Pin Function List (1) Port Pins (1/2) Alternate Pin Name Input/Output Function After Reset Function Input/Output Port 0 Input INTP0 4-bit input/output port INTP1 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up resistor can be used by software.
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CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) (1) Port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function Input/Output Port 7 Input TI00/TO0 6-bit input/output port TI01 Input/output mode can be specified bit-wise. TI50/TO50 If used as an input port, an on-chip pull-up resistor can be used by software.
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CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) (2) Non-port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function ANI0 to ANI7 Input A/D converter analog input Input P10 to P17 ADTRG Input A/D converter trigger signal input Input P03/INTP3 Input...
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P03 (Port 0) These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt input, and A/D converter external trigger input pins. The following operating modes can be specified bit-wise.
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.2.3 P20 to P25 (Port 2) These are 6-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/from the serial interface and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 6-bit input/output ports.
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The interrupt request flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified bit-wise.
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.2.8 P70 to P75 (Port 7) These are 6-bit input/output ports. Besides serving as input/output ports, they function as a timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 6-bit input/output port.
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.2.12 RESET This is a low-level active system reset input pin. 4.2.13 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input the clock signal to X1 and its inverted signal to X2.
CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) 4.3 Pin Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the types of pin input/output circuit and the recommended connections of unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
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CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/output circuit type Input/output Recommended connection of unused pins P50/A8 to P57/A15 Input/output Independently connect to V or V via a resistor. P64/RD Input/output P65/WR...
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CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) Figure 4-1 Pin Input/Output Circuit of List (1/2) TYPE 2 TYPE 13-P IN/OUT data N-ch output disable Schmitt-Triggered Input with Hysteresis Characteristics input enable TYPE 5-H TYPE 13-Q Mask ...
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CHAPTER 4 PIN FUNCTION ( µ PD780024Y, 780034Y SUBSERIES) Figure 4-1 Pin Input/Output Circuit of List (2/2) TYPE 16 TYPE 25 feedback cut-off P-ch Comparator P-ch – N-ch (threshold voltage) input enable...
CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces µ PD780024, 780034, 780024Y, 780034Y Subseries can access 64-Kbyte memory space respectively. Figures 5-1 to 5-5 show memory maps. Caution In case of the internal memory capacity, the initial value of memory size switching register (IMS) of all products ( µ...
CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780024, 780034, 780024Y, and 780034Y Subseries products incorporate an on-chip ROM (or flash memory), as listed below.
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CHAPTER 5 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16- bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 5.3 Instruction Address Addressing).
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CHAPTER 5 CPU ARCHITECTURE Figure 5-7. Data Memory Addressing ( µ PD780022, 780032, 780022Y, 780032Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH...
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CHAPTER 5 CPU ARCHITECTURE Figure 5-8. Data Memory Addressing ( µ PD780023, 780033, 780023Y, 780033Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH...
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CHAPTER 5 CPU ARCHITECTURE Figure 5-9. Data Memory Addressing ( µ PD780024, 780034, 780024Y, 780034Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH...
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CHAPTER 5 CPU ARCHITECTURE Figure 5-10. Data Memory Addressing ( µ PD78F0034, 78F0034Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1024 ×...
CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µ PD780024, 780034, 780024Y, 780034Y Subseries products incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
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CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-13. Stack Pointer Format SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
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CHAPTER 5 CPU ARCHITECTURE Table 5-5. Special Function Register List (1/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits √ √ FF00H Port0 — √ √ FF01H Port1 — √ √ FF02H Port2 —...
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CHAPTER 5 CPU ARCHITECTURE Table 5-5. Special-Function Register List (2/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 8 bits 16 bits 1 bit √ √ FF20H Port mode register 0 — √ √ FF22H Port mode register 2 —...
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CHAPTER 5 CPU ARCHITECTURE Table 5-5. Special-Function Register List (3/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits √ √ Note 1 FFA8H IIC control register IICC0 — √ √ Note 1 FFA9H IIC status register IICS0...
CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
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CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]...
CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.
CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 to RBS1). Register addressing is carried out when an instruction with the following operand format is executed.
CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
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CHAPTER 5 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration]...
CHAPTER 5 CPU ARCHITECTURE 5.4.5 Special-function register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated.
CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD780024, 780034, 780024Y, and 780034Y Subseries products incorporate eight input ports and forty-three input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on- chip hardware input/output pins.
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CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions ( µ PD780024, 780034 Subseries) Alternate Pin Name Function Function Port 0 INTP0 4-bit input/output port. INTP1 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up resistor can be used by software. INTP3/ADTRG P10 to P17 Port 1...
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CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD780024Y, 780034Y Subseries) Alternate Pin Name Function Function Port 0 INTP0 4-bit input/output port. INTP1 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up resistor can be used by software. INTP3/ADTRG P10 to P17 Port 1...
CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2 to 7) Pull-up resistor option register (PUOm,: m = 0, 2 to 7) Port Total: 51 ports (8 inputs, 43 inputs/outputs) Pull-up resistor...
CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 to P03 Configurations PU00 to PU03 P-ch Selector PORT P00/INTP0 to Output latch P02/INTP2, (P00 to P03) P03/INTP3/ADTRG PM00 to PM03 PU : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal 6.2.2 Port 1 Port 1 is an 8-bit input only port.
CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 Port 2 is a 6-bit input/output port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P25 pins are used as input ports, an on-chip pull-up resistor can be used for them in 1-bit units with a pull-up resistor option register 2 (PU2).
CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 3 ( µ PD780024, 780034 Subseries) Port 2 is a 7-bit input/output port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). This port has the following functions for pull-up resistors.
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CHAPTER 6 PORT FUNCTIONS Figure 6-6. P34 to P36 Configurations ( µ PD780024, 780034 Subseries) PU34 to PU36 P-ch Selector PORT P34/SI31, Output latch P35/SC31, (P34 to P36) P36/SCK31 PM34 to PM36 PU : Pull-up resistor option register PM : Port mode register RD : Port 3 read signal WR : Port 3 write signal...
CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 ( µ PD780024Y, 780034Y Subseries) Port 3 is a 7-bit input/output port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). This port has the following functions for pull-up resistors.
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CHAPTER 6 PORT FUNCTIONS Figure 6-7. P30 and P31 Configurations ( µ PD780024Y, 780034Y Subseries) Mask option resistor Mask ROM versions only No pull-up resistor for flash memory versions Selector PORT Output latch P30, P31 (P30, P31) PM30, PM31 PM : Port mode register RD : Port 3 read signal WR : Port 3 write signal Figure 6-8.
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CHAPTER 6 PORT FUNCTIONS Figure 6-9. P34 to P36 Configurations ( µ PD780024Y, 780034Y Subseries) PU34 to PU36 P-ch Selector PORT Output latch P34 to P36 (P34 to P36) PM34 to PM36 PU : Pull-up resistor option register PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal...
CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1-bit units with port mode register 4 (PM4). When the P40 to P47 pins are used as input ports, a pull-up resistor can be connected to them in 1-bit units with pull-up resistor option register 4 (PU4).
CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. The P50 to P57 pins can specify the input mode/output mode in 1-bit units with port mode register 5 (PM5). When the P50 to P57 pins are used as input ports, an on-chip pull- up resistor can be used for them in 1-bit units with pull-up resistor option register 5 (PU5).
CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is a 4-bit input/output port with output latch. The P64 to P67 pins can specify the input mode/output mode in 1-bit units with port mode register 6 (PM6). When pins P64 to P67 are used as input ports, an on-chip pull-up resistor can be used for them in 1-bit units with pull-up resistor option register 6 (PU6).
CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 6-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P75 are used as input port pins, an on-chip pull-up resistor can be used as a 1-bit unit by means of pull-up resistor option register 7 (PU7).
CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM7) • Pull-up resistor option register (PU0, PU2 to PU7) (1) Port mode registers (PM0, PM2 to PM7) These registers are used to set port input/output in 1-bit units.
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CHAPTER 6 PORT FUNCTIONS Figure 6-15. Port Mode Register (PM0, PM2 to PM7) Format Address: FF20H After Reset : FFH Symbol PM03 PM02 PM01 PM00 Address: FF22H After Reset : FFH Symbol PM25 PM24 PM23 PM22 PM21 PM20 Address: FF23H After Reset : FFH Symbol PM36 PM35...
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CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PU0, PU2 to PU7) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with PU0, PU2 to PU7.
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CHAPTER 6 PORT FUNCTIONS Figure 6-16. Pull-Up Resistor Option Register (PU0, PU2 to PU7) Format Address: FF30H After Reset : 00H Symbol PU03 PU02 PU01 PU00 Address: FF32H After Reset : 00H Symbol PU25 PU24 PU23 PU22 PU21 PU20 Address: FF33H After Reset : 00H Symbol PU36 PU35...
CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
CHAPTER 6 PORT FUNCTIONS 6.5 Selection of Mask Option The following mask option is provided in the mask ROM version. The flash memory versions have no mask options. Table 6-6. Comparison Between Mask ROM Version and Flash Memory Version Pin Name Mask ROM Version Flash Memory Version Note...
CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
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CHAPTER 7 CLOCK GENERATOR Figure 7-1. Clock Generator Block Diagram Subsystem Watch timer clock clock oscillator output Prescaler function Clock to Main system peripheral clock hardware Prescaler oscillator Standby Wait CPU clock control control circuit circuit To INTP0 sampling clock STOP MCC FRC CSS PCC2 PCC1 PCC0...
CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register (PCC) Format Note 1 Address: FFFBH After Reset: 04H Symbol PCC2 PCC1 PCC0 Note 2 Main system clock oscillation control Oscillation possible Oscillation stopped Subsystem clock feedback resistor select Internal feedback resistor used Internal feedback resistor not used CPU clock status Main system clock...
CHAPTER 7 CLOCK GENERATOR The fastest instructions of µ PD780024, 780034, 780024Y, and 780034Y Subseries are carried out in 2 CPU clocks. The relationship of CPU clock (f ) and minimum instruction execution time is shown in table 7-2. Table 7-2 Relationship of CPU Clock and Min. Instruction Execution Time CPU Clock (f Min.
CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an inversed-phase clock signal to the XT2 pin.
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CHAPTER 7 CLOCK GENERATOR Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in Figures 7-4 and 7-5 to prevent any effects from wiring capacitance. • Minimize the wiring length. •...
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CHAPTER 7 CLOCK GENERATOR Figure 7-6. Examples of Incorrect Oscillator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (f ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC).
CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
CHAPTER 7 CLOCK GENERATOR Figure 7-7. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main system clock oscillation Subsystem clock oscillation CPU clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
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CHAPTER 7 CLOCK GENERATOR Table 7-3. Maximum Time Required for CPU Clock Switchover Set value before Set value After Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 ×...
CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between the system clock and CPU clock. Figure 7-8. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Lowest- Highest- Subsystem...
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timer Integrated in µ PD780024, 780034, 780024Y, 780034Y Subseries In this chapter, the 16-bit timer/event counter is described. The timers integrated in the µ PD780024, 780034, 780024Y, and 780034Y Subseries are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used as an interval timer, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency, or one-shot pulse output.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Capture/compare register 00(CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register •...
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare register 01 (CR01) CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0. •...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer Mode Control Register (TMC0) Format Address FF60H After Reset: 00H Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Operating Mode TMC03 TMC02 TMC01 TO0 output timing selection Interrupt request generation and Clear Mode Selection Operation stop No change Not generated...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-3.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip- flop (LV0) setting/resetting, output inversion enabling/disabling, 16-bit timer/event counter timer output enabling/ disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shot pulse by software.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Prescaler mode register 0 (PRM0) This register is used to set 16-bit timer (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets PRM0 value to 00H. Figure 8-5.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO0/TI00 pin for timer output, set PM70 and the output latch of P70 to 0. PM7 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM7 value to FFH.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-7 allows operation as an interval timer. Interrupt request is generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.2 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/TI00/P70 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16- bit capture/compare register 00 (CR00), respectively.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/TO0/P70 pin and TI01/P71 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/TO0/P70 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-12. Configuration Diagram for Pulse Width Measurement by Free-Running Counter 16-bit timer register OVF0 (TM0) 16-bit capture/compare TI00/TO0/P70 register (CR01) INTTM01 Internal bus Figure 8-13. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock TM0 count value...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-14), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/TO0/P70 pin and the TI01/P71 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER • Capture operation (Free-Running mode) Capture register operation in capture trigger input is shown. Figure 8-15. Capture Operation with Rising Edge Specified Count clock n–3 n–2 n–1 TI00 Rising edge detection CR01 INTTM01 Figure 8-16. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17), it is possible to measure the pulse width of the signal input to the TI00//TO0/P70 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/TO0/P70 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI00 pin input CR01 capture value CR00 capture value...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-19. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts at valid edge of TI00/TO0/P70 pin. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/TO0/P70 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the prescaler mode register 0 (PRM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-25. Square-Wave Output Operation Timing Count clock TM0 count value 0000H 0001H 0002H N–1 0000H 0001H 0002H N–1 0000H CR00 INTTM00 TO0 pin output 8.5.6 One-shot pulse output operation It is possible to output one-shot pulses by software trigger. If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-26, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/TI00/P70 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-26. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Free-running mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 CR00 as compare register...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. Timing of One-Shot Pulse Output Operation Using Software Trigger Sets 0CH to TMC0 (TM0 count starts) Count clock TM0 count value 0000H 0001H 0000H N–1 M–1 0000H 0001H CR01 set value CR00 set value OSPT INTTM01 INTTM00...
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 8-28.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/TO0/P70 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (TMIF01) is set upon detection of the valid edge.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag <1> OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (11) Compare operation <1> When the 16-bit capture/compare register (CR00/CR01) is overwritten during timer operation, match interrupt may be generated or clear operation may not be performed normally if that value is close to the timer value and larger than the timer value.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1 8-Bit Timer/Event Counter Functions 8-bit timer/event counter (TM50, TM51) has the following two modes. • Mode using 8-bit timer/event counters alone (individual mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.3 Registers to Control 8-Bit Timer/Event Counter The following three types of registers are used to control 8-bit timer/event counters. • Timer clock select register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-5 8-Bit Timer Mode Control Register 5n (TMC5n) Format Address: FF70H (TMC50) FF78H (TMC51) After Reset: 00H Symbol TMC5n TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n TCE5n TM5n Count Operation Control After cleaning to 0, count operation disabled (prescaler disabled) Count operation start TMC5n6 TM5n Operating Mode Selection...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer output, set PM72, PM73, and output latches of P72 and P73 to 0. PM7 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4 8-Bit Timer/Event Counter Operations 9.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 5n (CR5n). When the count values of the 8-bit counter 5n (TM5n) match the values set to CR5n, counting continues with the TM5n values cleared to 0 and the interrupt request signals (INTTM5n) are generated.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-7. Interval Timer Operation Timings (1/3) (a) Basic operation Count clock TM5n count Start count Clear Clear CR5n TCE5n INTTM5n Interrupt received Interrupt received TO5n Interval time Interval time Interval time Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH 2.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-7. Interval Timer Operation Timings (2/3) (b) When CR5n = 00H Count clock CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt received Interrupt received TO5n Interval time n = 0, 1...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-7. Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N) Count clock CR5n TCE5n INTTM5n TO5n CR5n transition TM5n overflows since M < N (e) Operated by CR5n transition (M > N) Count clock N–1 M–1...
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5n by the 8-bit counter 5n (TM5n). TM5n is incremented each time the valid edge specified with the timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.3. Square-wave output (8-bit resolution) operation A square wave with any selected frequency is output at intervals of the value preset to the 8-bit compare register 5n (CR5n). TO5n pin output status is reversed at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8- bit timer mode control register 5n (TMC5n) to 1.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.4 8-bit PWM output operation 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty rate pulse determined by the value set to 8-bit compare register 5n (CR5n). Set the active level width of PWM pulse to CR5n, and the active level can be selected with bit 1 of TMC5n (TMC5n1).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) Operated by CR5n transition Figure 9-11. Timing of Operation by Change of CR5n (a) CR5n value transits from N to M before overflow of TM5n Count clock TM5n N N+1 N+2 FFH 00H 01H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2...
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.5 Interval timer (16-bit) operations When “1” is set in bit 4 (TMC514) of 8-bit timer mode control register 51 (TM51), the 16-bit resolution timer/counter mode is entered. The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (CR50, CR51).
CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-12. 16-Bit Resolution Cascade Connection Mode Count clock TM50 N N+1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 M–1 M B 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time TO50 Interrupt request Operation...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) Operation after compare register transition during timer count operation If the values after the 8-bit compare register 5n (CR5n) is transmitted is smaller than the value of 8-bit counter 5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR5n is smaller than value (N) before transition, it is necessary to restart the timer after transitting CR5n.
CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1.
CHAPTER 10 WATCH TIMER (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 0.5 second or 0.25 second intervals. (2) Interval timer Interrupt requests (INTWTI) are generated at the preset time interval. Table 10-1.
CHAPTER 10 WATCH TIMER 10.3 Register to Control Watch Timer Watch timer mode control register (WTM) is a register to control watch timer. • Watch timer mode control register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 8.38-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer generates an interrupt request (INTWT) at the constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register (WTM) is set to 1, the 5-bit counter is cleared and the count operation stops.
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CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time n x T n x T...
CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Oscillation stabilization time selection Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM).
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CHAPTER 11 WATCHDOG TIMER (1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 11-1. Watchdog Timer Runaway Detection Times Runaway detection times (489 µ s) × 1/f ×...
CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Control register Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 11.3 Registers to Control the Watchdog Timer The following three types of registers are used to control the watchdog timer.
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CHAPTER 11 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 11-2. Watchdog Timer Clock Select Register (WDCS) Format Address: FF42H After Reset: 00H Symbol...
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CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register (WDTM) Format Address: FFF9H After Reset: 00H Symbol...
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CHAPTER 11 WATCHDOG TIMER (3) Oscillation Stabilization Time Select Register (OSTS) A register to select oscillation stabilization time from reset time or STOP mode released time to the time when oscillation is stabilized. OSTS is set by an 8-bit memory operation instruction. By RESET input, it is turned into 04H.
CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The runaway detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively.
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS 12.1 Clock Output/Buzzer Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square wave output of buzzer frequency selected with CKS.
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS 12.2 Clock Output/Buzzer Output Control Circuit Configuration The clock output/buzzer output control circuits consists of the following hardware. Table 12-1. Configuration of Clock Output/Buzzer Output Control Circuits Item Configuration Control register Clock output selection register (CKS) Note Port mode register (PM7) Note See Figure 6-14 P70 to P75 Configurations.
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CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS Figure 12-2. Clock Output Selection Register (CKS) Format Address: FF40H After Reset: 00H R/W Symbol BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ Output Enable/Disable Specification Stop clock division circuit operation. BUZ fixed to low level. Enable clock division circuit operation.
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CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS (2) Port mode register (PM7) This register sets port 7 input/output in 1-bit units. When using the P74/PCL pin for clock output and the P75/BUZ pin for buzzer output, set PM74, PM75 and the output latch of P74, P75 to 0.
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROL CIRCUITS 12.4 Clock Output/Buzzer Output Control Circuit Operations 12.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.1 A/D Converter Functions A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 8 analog input channels (ANI0 to ANI7). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 13-1. A/D Converter Configuration Item Configuration Analog input 8 channels (ANI0 to ANI7) Registers Successive approximation register (SAR) A/D conversion result register (ADCR0) Control register A/D converter mode register (ADM0)
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (6) ANI0 to ANI7 pins These are eight analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 are alternate-function pins that can also be used for digital input. Cautions 1.
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.3 Registers to Control A/D Converter The following 4 types of registers are used to control the A/D converter. • A/D converter mode register (ADM0) • Analog input channel specification register (ADS0) •...
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (2) Analog input channel specification register (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation. RESET input sets ADS0 to 00H. Figure 13-3.
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (3) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets EGP and EGN to 00H.
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D Converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) Figure 13-5. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of the A/D converter mode register (ADM0) is reset (0) by software.
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR0)) is shown by the following expression. ×...
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.4.3 A/D converter operation mode One analog input channel is selected from among ANI0 to ANI7 by the analog input channel specification register (ADS0) and start A/D conversion. A/D conversion can be started in either of the following two ways. •...
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of the A/D converter mode register (ADM0) are set to 0 and 1, respectively, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS0) starts.
CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) 13.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of the A/D converter mode register (ADM0) to 0). Figure 13-9 shows how to reduce the current consumption in the standby mode.
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) <4> Noise countermeasures To maintain the 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 13-10 to reduce noise.
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (7) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if the analog input channel specification register (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite.
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CHAPTER 13 8-BIT A/D CONVERTER ( µ PD780024, 780024Y SUBSERIES) (8) AV The AV pin is the analog circuit power supply pin. It supplies power to the input circuits of the ANI0 to ANI7 pins. Therefore, be sure to apply the same voltage as V to this pin even when the application circuit is designed so as to switch its power supply to a backup battery.
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) 14.1 A/D Converter Functions A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control up to 8 analog input channels (ANI0 to ANI7). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) (6) ANI0 to ANI7 pins These are eight analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 are dual-function pins that can also be used for digital input. Cautions 1.
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) (2) Analog input channel specification register (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation. RESET input sets ADS0 to 00H. Figure 14-3.
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) 14.4 A/D Converter Operation 14.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) Figure 14-5. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of the A/D converter mode register (ADM0) is reset (0) by software.
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) 14.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR0)) is shown by the following expression. ×...
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) 14.4.3 A/D converter operation mode Select one analog input channel from among ANI0 to ANI7 by the analog input channel specification register (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. •...
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of the A/D converter mode register (ADM0) are set to 0 and 1, respectively, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS0) starts.
CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) 14.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of the A/D converter mode register (ADM0) to 0). Figure 14-9 shows how to reduce the current consumption in the standby mode.
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) Figure 14-10. Analog Input Pin Connector If there is a possibility that noise equal to or higher than AV equal to or lower than AV may enter, clamp with a diode with a small V value (0.3 V or lower).
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) Figure 14-11. A/D Conversion End Interrupt Request Generation Timing ADM0 rewrite ADS0 rewrite ADIF is set but ANIm (start of ANIn conversion) (start of ANIn conversion) conversion has not ended. A/D conversion ANIn ANIn...
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CHAPTER 14 10-BIT A/D CONVERTER ( µ PD780034, 780034Y SUBSERIES) (8) AV The AV pin is the analog circuit power supply pin. It supplies power to the input circuits of the ANI0 to ANI7 pins. Therefore, be sure to apply the same potential as V to this pin even for applications designed to switch to a backup battery for power supply.
CHAPTER 15 SERIAL INTERFACE OUTLINE The µ PD780024, 780034 Subseries and the µ PD780024Y, 780034Y Subseries have differences in their interfaces. These differences are listed in Table 15-1. Table 15-1. Differences between µ PD780024, 780034 Subseries and µ PD780024Y, 780034Y Subseries µ...
CHAPTER 16 SERIAL INTERFACE (UART0) 16.1 Serial Interface Functions The serial interface (UART0) has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 16.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received.
CHAPTER 16 SERIAL INTERFACE (UART0) 16.2 Serial Interface Configuration The serial interface (UART0) includes the following hardware. Table 16-1. Serial Interface (UART0) Configuration Item Configuration Registers Transmit shift register (TXS0) Receive shift register (RX0) Receive buffer register (RXB0) Control registers Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0)
CHAPTER 16 SERIAL INTERFACE (UART0) (5) Reception control circuit The reception control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (ASIM0). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (ASIS0) according to the type of error that is detected.
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CHAPTER 16 SERIAL INTERFACE (UART0) Figure 16-2. Asynchronous Serial Interface Mode Register (ASIM0) Format Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P23 pin function TxD0/P24 pin function Operation stop Port function (P23) Port function (P24) UART mode Serial function (RxD0)
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CHAPTER 16 SERIAL INTERFACE (UART0) (2) Asynchronous serial interface status register (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Figure 16-3.
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CHAPTER 16 SERIAL INTERFACE (UART0) Figure 16-4. Baud Rate Generator Control Register (BRGC0) Format Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz) TPS02 TPS01 TPS00 Source clock selection for 5-bit counter P25/ASCK0 MDL03 MDL02...
CHAPTER 16 SERIAL INTERFACE (UART0) 16.4 Serial Interface Operations This section explains the three modes of the serial interface (UART0). 16.4.1 Operation stop mode Because serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as ordinary ports. (1) Register settings Operation stop mode are set by the asynchronous serial interface mode register (ASIM0).
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CHAPTER 16 SERIAL INTERFACE (UART0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P23 pin function TxD0/P24 pin function Operation stop Port function (P23) Port function (P24) UART mode Serial function (RxD0) (receive only) UART mode Port function (P23)
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CHAPTER 16 SERIAL INTERFACE (UART0) (b) Asynchronous serial interface status register (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Address: FFA1H After reset: 00H Symbol ASIS0 OVE0 Parity error flag No parity error Parity error (Incorrect parity bit detected) Framing error flag...
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CHAPTER 16 SERIAL INTERFACE (UART0) (c) Baud rate generator control register (BRGC0) BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets BRGC0 to 00H. Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz)
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CHAPTER 16 SERIAL INTERFACE (UART0) The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Transmit/receive clock generation for baud rate by using main system clock The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the main system clock is determined according to the following formula.
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CHAPTER 16 SERIAL INTERFACE (UART0) • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 16-3 describes the relationship between the main system clock and the baud rate and Figure 16- 5 shows an example of a baud rate error tolerance range.
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CHAPTER 16 SERIAL INTERFACE (UART0) Figure 16-5. Error Tolerance (when k = 0), Including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception...
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CHAPTER 16 SERIAL INTERFACE (UART0) (2) Communication operations (a) Data format Figure 16-6 shows the format of the transmit/receive data. Figure 16-6. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start Parity Stop bit Character bits 1 data frame consists of the following bits. •...
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CHAPTER 16 SERIAL INTERFACE (UART0) (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
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CHAPTER 16 SERIAL INTERFACE (UART0) (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt request (INTST0) is issued.
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CHAPTER 16 SERIAL INTERFACE (UART0) (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface mode register (ASIM0), and input via the RxD0 pin is sampled. The serial clock specified by ASIM0 is used to sample the RxD0 pin. When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
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CHAPTER 16 SERIAL INTERFACE (UART0) (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register (ASIS0), a receive error interrupt request (INTSER0) will occur.
CHAPTER 16 SERIAL INTERFACE (UART0) 16.4.3 Infrared data transfer mode In infrared data transfer mode, the following data format pulse output and pulse receiving are enabled. The relationship between the main system clock and baud rate is shown in table 16-3. (1) Data format Figure 16-10 compares the data format used in UART mode with that used in infrared data transfer mode.
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CHAPTER 16 SERIAL INTERFACE (UART0) (2) Bit rate and pulse width Table 16-5 lists bit rates, bit rate error tolerances, and pulse width values. Table 16-5. Bit Rate and Pulse Width Values 3/16 pulse width Bit rate Bit rate error tolerance Pulse width minimum value Maximum pulse width <nominal value>...
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CHAPTER 16 SERIAL INTERFACE (UART0) (3) Input data and internal signals • Transmit operation timing UART Start bit Stop bit output data UART (Inverted data) Infrared data transfer enable signal TxD0 pin output signal • Receive operation timing Data reception is delayed for one-half of the specified baud rate. UART Start bit Stop bit...
CHAPTER 17 SERIAL INTERFACE (SIO3) The serial interface (SIO3) incorporates two 3-wire serial I/O mode channels (SIO30, SIO31). These two channels have exactly the same functions. Therefore, unless otherwise specified, the SIO30 is used throughout this chapter to describe the functions of both the SIO30 and SIO31.
CHAPTER 17 SERIAL INTERFACE (SIO3) 17.1 Serial Interface Functions The serial interface (SIO3) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 17.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30).
CHAPTER 17 SERIAL INTERFACE (SIO3) 17.2 Serial Interface Configuration The serial interface (SIO30) includes the following hardware. Table 17-2. Serial Interface (SIO30) Configuration Item Configuration Registers Serial I/O shift register 30 (SIO30) Control registers Serial operation mode register 30 (CSIM30) (1) Serial I/O shift register 30 (SIO30) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.
CHAPTER 17 SERIAL INTERFACE (SIO3) 17.3 Register to Control Serial Interface The serial interface (SIO30) uses the following type of register to control functions. • Serial operation mode register 30 (CSIM30) (1) Serial operation mode register 30 (CSIM30) This register is used to enable or disable SIO30’s serial clock, operation modes, and specific operations. CSIM30 can be set by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE (SIO3) Notes 1. When CSIE30 = 0 (SIO30 operation stop status), the pins SI30, SO30, and SCK30 can be used for port functions. 2. When CSIE30 = 1 (SIO30 operation enabled state), the SI30 pin can be used as a port pin if only the send function is used, and the SO30 pin can be used as a port pin if only the receive-only mode is used.
CHAPTER 17 SERIAL INTERFACE (SIO3) 17.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30).
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CHAPTER 17 SERIAL INTERFACE (SIO3) Remarks 1. f : main system clock oscillation frequency 2. Figures in parentheses are for operation with f = 8.38 MHz. (2) Communication Operations In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.1 Serial Interface Functions The serial interface (IIC0) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-1 shows a block diagram of serial interface (IIC0). Figure 18-1. Serial Interface (IIC0) Block Diagram Internal bus IIC status register (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register (IICC0) Slave address...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-2 shows a serial bus configuration example. Figure 18-2. Serial Bus Configuration Example Using I C Bus Master CPU2 Serial data bus Master CPU1 SDA0 SDA0 Slave CPU2 Serial clock SCL0 Slave CPU1...
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.2 Serial Interface Configuration The serial interface (IIC0) includes the following hardware. Table 18-1. Serial Interface (IIC0) Configuration Item Configuration Registers IIC shift register (IIC0) Slave address register (SVA0) Control registers IIC control register (IICC0) IIC status register (IICS0)
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (8) Serial clock control circuit During master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait control circuit This circuit controls the wait timing. (10) ACK output circuit, stop condition detection circuit, start condition detection circuit, and ACK detection circuit These circuits are used to output and detect various control signals.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-3. IIC Control Register (IICC0) Format (1/3) Address: FFA8H After reset: 00H Symbol IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Stops operation. Presets expansion register (IICS0). Stops internal operation. Enables operation.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-3. IIC Control Register (IICC0) Format (2/3) WTIM0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock’s falling edge. Master mode : After output of eight clocks, clock output is set to low level and wait is set. Slave mode : After input of eight clocks, the clock is set to low level and wait is set for master device.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-3. IIC Control Register (IICC0) Format (3/3) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (2) IIC status register (IICS0) This register indicates the status of the I IICS0 can be set by a 1-bit or 8-bit memory manipulation instruction. IICS0n is a read-only register. RESET input sets the value to 00H.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-4. IIC Status Register (IICS0) Format (2/3) COI0 Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) •...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-4. IIC Status Register (IICS0) Format (3/3) STD0 Detection of start condition Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1) •...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (3) IIC clock select register (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IICCL0 to 00H.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-5. IIC Clock Select Register (IICCL0) Format (2/2) Note DFC0 Control of digital filter operation Digital filter ON Digital filter OFF Selection of transfer rate CL00 Standard mode High-speed mode /44 (191 kHz) /24 (350 kHz)
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.4 I C Bus Mode Functions 18.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0 ········· This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. Figure 18-7 shows the transfer timing for the “start condition”, “data”, and “stop condition” output via the I bus’s serial data bus.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.4 Acknowledge (ACK) signal The acknowledge (ACK) signal is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-13. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (master device transmits, slave receives, and ACKE0 = 1) Master and slave both wait Master after output of ninth clock IIC0 data write (cancel wait)
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.7 I C interrupt requests (INTIIC0) The INTIIC0 interrupt request timing and the IIC status register (IICS0) settings corresponding to that timing are described below. (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) When WTIM0 = 0 AD6-AD0...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop When WTIM0 = 0 (after restart, does not match with address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1 : IICS0 = 0101×110B (Example: when ALD0 is read during interrupt servicing) 2 : IICS0 = 0001×000B 3 : IICS0 = 0001×000B...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1 : IICS0 = 0110×010B (Example: when ALD0 is read during interrupt servicing) 2 : IICS0 = 0010×000B 3 : IICS0 = 0010×000B 4 : IICS0 = 00000001B...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6-AD0 D7-D0 D7-D0 1 : IICS0 = 01000110B (Example: when ALD0 is read during interrupt servicing) 2 : IICS0 = 00000001B Remark : Always generated...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1 : IICS0 = 10001110B 2 : IICS0 = 01000000B (Example: when ALD0 is read during interrupt servicing) 3 : IICS0 = 00000001B Remark : Always generated...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: matches with SVA0) AD6-AD0 D7-Dn AD6-AD0 D7-D0 1 : IICS0 = 1000×110B 2 : IICS0 = 01000110B (Example: when ALD0 is read during interrupt servicing) 3 : IICS0 = 00000001B Remark : Always generated...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (e) When loss occurs due to stop condition during data transfer AD6-AD0 D7-Dn 1 : IICS0 = 1000×110B 2 : IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6-AD0 D7-D0 1 : IICS0 = 1000×110B 2 : IICS0 = 1000×000B 3 : IICS0 = 01000001B Remark...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6-AD0 D7-D0 D7-D0 D7-D0 1 : IICS0 = 1000×110B 2 : IICS0 = 1000×000B 3 : IICS0 = 01000000B (Example: when ALD0 is read during interrupt servicing)
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) in the IIC control register (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 18-2.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.9 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt frequency (INTIIC0) occurs when a local address has been set to the slave address register (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.12 Arbitration When several master devices simultaneously output a start condition (when STT0 is set to 1 before STD0 is set Note to 1 ), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Table 18-4. Status during Arbitration and Interrupt Request Generation Timing Status during arbitration Interrupt request generation timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission...
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.14 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-15. Communication Reservation Timing STT0 Write to Program processing IIC0 Set SPD0 Communication Hardware processing reservation and INTIIC0 STD0 SCL0 SDA0 Output by master with bus access Remark IIC0 : IIC shift register STT0 : Bit 1 of IIC control register (IICC0) STD0 : Bit 1 of IIC status register (IICS0)
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-17. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM) Gets wait period set by software (see Table 18-5).
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.5.16 Communication operations (1) Master operations The following is a flow chart of the master operations. Figure 18-18. Master Operation Flow Chart START IICCL0 ← ××H Select transfer clock IICC0 ←...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) (2) Slave operation An example of slave operation is shown below. Figure 18-19. Slave Operation Flow Chart START IICC0 ← ××H IICE0=1 INTIIC0=1? EXC0=1? Communicate? COI0=1? LREL0=1 TRC0=1? WTIM0=0 ACKE0=1 WTIM0=1 Start IIC0 write transfer...
CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) 18.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IIC status register (IICS0)) that specifies the data transfer direction and then starts serial communication with the slave device.
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-20. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ←...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-20. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ← data IIC0 ← data IIC0 ACKD0 STD0...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-20. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← data IIC0 ←...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-21. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ←...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-21. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ← FFH Note IIC0 ←...
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CHAPTER 18 SERIAL INTERFACE (IIC0) ( µ PD780024Y, 780034Y SUBSERIES ONLY) Figure 18-21. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← FFH Note IIC0 ←...
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Interrupt Function Control Registers The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
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CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
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CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register, they are set with a 16-bit memory manipulation instruction.
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CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
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CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), External interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
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CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple processing are mapped.
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into PC and branched.
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Maskable interrupt acknowledge operation A maskable interrupt becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
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CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non-maskable interrupts).
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION 20.1 External Device Expansion Function The external device expansion function connects external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc.
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION The memory maps when the external device expansion function is used are as follows. Figure 20-1. Memory Map when Using External Device Function (1/2) (a) Memory map of µ PD780021, 780031, 780021Y, (b) Memory map of µ PD780022, 780032, 780022Y, 780031Y and of µ...
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION Figure 20-1. Memory Map when Using External Device Function (2/2) (c) Memory map of µ PD780023, 780033, 780023Y, (d) Memory map of µ PD780024, 780034, 780024Y, 780033Y and of µ PD78F0034, 78F0034Y when 780034Y and of µ PD78F0034, 780034Y when in- internal ROM (flash memory) size is 24 Kbytes ternal ROM (flash memory) size is 32 Kbytes FFFFH...
CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION 20.2 External Device Expansion Function Control Register The external device expansion function is controlled by the following two types of registers. • Memory expansion mode register (MEM) • Memory expansion wait setting register (MM) (1) Memory expansion mode register (MEM) MEM sets the external expansion area.
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory expansion wait setting register (MM) MM sets the number of waits. MM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 20-3. Memory Expansion Wait Setting Register (MM) Format Address: FFF8H After Reset: 10H R/W Symbol Wait Control...
CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION 20.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe output pin. The read strobe output pin is output in data accesses and instruction fetches from external memory.
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION Figure 20-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Instruction code AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Lower address Instruction code...
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION Figure 20-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Read data AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower address...
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION Figure 20-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower address Write data AD0 to AD7 Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...
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CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION Figure 20-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower AD0 to AD7 Read data Write data address Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...
CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION 20.4 Example of Connection with Memory This section provide an example of connecting the µ PD780024 with external memory (in this example, SRAM) in Figure 20-8. In addition, the external device expansion function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 Kbytes) are allocated for internal ROM, and the addresses after 8000H from SRAM.
CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode Halt instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
CHAPTER 21 STANDBY FUNCTION 21.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operations 21.2.1 HALT mode (1) HALT mode setting and operating statuses The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating statuses in the HALT mode are described below.
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CHAPTER 21 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is cleared. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
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CHAPTER 21 STANDBY FUNCTION (c) Clear upon RESET input When RESET signal is input, HALT mode is released. And, as in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 21-3. HALT Mode Release by RESET Input Wait HALT instruction : 15.6 ms)
CHAPTER 21 STANDBY FUNCTION 21.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
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CHAPTER 21 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
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CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input The STOP mode is cleared when RESET signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 21-5. STOP Mode Release by RESET Input Wait STOP instruction : 15.6 ms)
CHAPTER 22 RESET FUNCTION 22.1 Reset Function The following two operations are available to generate the reset function. (1) External reset input via RESET pin (2) Internal reset by watchdog timer runaway time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
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CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period stabilization Normal operation (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 22-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
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CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses after Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General register...
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CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses after Reset (2/2) Hardware Status After Reset Clock output/buzzer output controller Clock output selection register (CKS) A/D converter Conversion result registers (ADCR0) Mode register (ADM0) Analog input channel specification register (ADS0) Serial interface (UART0) Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0)
CHAPTER 23 µ PD78F0034, 78F0034Y The µ PD78F0034 and 78F0034Y are provided as the flash memory versions of the µ PD780024, 780024Y, 780034, 780034Y Subseries. For purposes of simplification, throughout this chapter, the µ PD78F0034 is used to refer to both the µ PD78F0034 and 78F0034Y.
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CHAPTER 23 µ PD78F0034, 78F0034Y Table 23-1. Differences among µ PD78F0034 and Mask ROM Versions µ PD78F0034 Item Mask ROM Versions Internal ROM configuration Flash memory Mask ROM µ PD780021, 780031: 8 Kbytes Internal ROM capacity 32 Kbytes µ PD780022, 780032: 16 Kbytes µ...
CHAPTER 23 µ PD78F0034, 78F0034Y 23.1 Memory Size Switching Register The µ PD78F0034 allows users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the µ PD780021, 780022, 780023, 780024 and µ PD780031, 780032, 780033, 780034 with a different size of internal memory capacity can be achieved.
CHAPTER 23 µ PD78F0034, 78F0034Y 23.2 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash programmer (Flashpro II (type FL-PR2)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II.
CHAPTER 23 µ PD78F0034, 78F0034Y 23.2.2 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 23-4. Table 23-4. Main Functions of Flash Memory Programming Function Description Reset...
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CHAPTER 23 µ PD78F0034, 78F0034Y Figure 23-4. Flashpro II Connection Using UART Method µ Flashpro II PD78F0034 RESET RESET RXD0 TXD0 Figure 23-5. Flashpro II Connection Using I C Bus Method µ Flashpro II PD78F0034Y RESET RESET SCL0 SDA0 Figure 23-6. Flashpro II Connection Using Pseudo 3-wire Serial I/O µ...
CHAPTER 24 INSTRUCTION SET This chapter lists each instruction set of the µ PD780024, 780034, 780024Y, 780034Y Subseries in table form. For details of its operation and operation code, refer to the separate document 78K/0 Series User’s Manual— Instructions (U12326E).
CHAPTER 24 INSTRUCTION SET 24.1 Legends Used in Operation List 24.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
CHAPTER 24 INSTRUCTION SET 24.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
CHAPTER 24 INSTRUCTION SET 24.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word 16-bit MOVW rp, #word – data (saddrp) ← word saddrp, #word transfer sfrp ← word sfrp, #word – AX ←...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr) – byte × ×...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A byte × 8-bit A, #byte – operation (saddr) ← (saddr) byte × saddr, #byte A ← A r ×...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) × AND1 CY, saddr.bit manipu- CY ← CY sfr.bit × CY, sfr.bit – late CY ← CY A.bit ×...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) Call/return CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
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CHAPTER 24 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 Condi- saddr.bit, $addr16 tional PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
APPENDIX A DIFFERENCES BETWEEN µ PD78014H, 78018F, 780024, AND 780034 SUBSERIES Table A-1 shows the major differences between µ PD78014H, 78018F, 780024, and 780034 Subseries. Table A-1. Major Differences between µ PD78014H, 78018F, 780024, and 780034 Subseries µ PD78014H Subseries µ...
APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD780024, 780034, 780024Y, and 780034Y Subseries. Figure B-1 shows the development tool configuration. Figure B-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator IE-78K0-NS Language Processing Software •...
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APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...
APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software This assembler converts programs written in mnemonics into an object codes RA78K/0 executable with a microcontroller. Assembler Package Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optical device file (DF780024 or DF780034).
APPENDIX B DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 µ S××××DF780024 µ S××××DF780034 µ S××××CC78K0-L ×××× Host Machine Supply Medium Notes 1, 2 AA13 PC-9800 series Windows (Japanese version) 3.5-inch 2HD FD Notes 1, 2...
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using the in-circuit emulator IE-78K0-NS Note The in-circuit emulator serves to debug hardware and software when developing IE-78K0-NS application systems using a 78K/0 Series product. It corresponds to integrated In-circuit Emulator debugger (ID78K0-NS).
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APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using the in-circuit emulator IE-78001-R-A Note The in-circuit emulator serves to debug hardware and software when developing IE-78001-R-A application systems using a 78K/0 Series product. It corresponds to integrated In-circuit Emulator debugger (ID78K0).
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
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APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) Note This debugger is a control program to debug 78K/0 Series microcontrollers. ID78K0-NS Integrated Debugger It adopts a graphical user interface, which is equivalent visually and operationally to Windows or OSF/Motif™. It also has an enhanced debugging function for C language (supporting in-circuit emulator programs, and thus trace results can be displayed on screen in C-language level by using IE-78K0-NS)
Table B-1. System-up Method from Former In-circuit Emulator for 78K/0 Series to the IE-78001-R-A Note In-circuit Emulator Owned In-circuit Emulator Cabinet System-up Board to be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note For system-up of a cabinet, send your in-circuit emulator to NEC.
APPENDIX C EMBEDDED SOFTWARE For efficient development and maintenance of the µ PD780024, 780024Y, 780034, and 780034Y Subseries, the following embedded products are available.
APPENDIX C EMBEDDED SOFTWARE Real-Time OS (1/2) RX 78K/0 is a real-time OS conforming to the µ ITRON specifications. RX78K/0 Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78/0) and device file (DF780024 or DF780034).
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APPENDIX C EMBEDDED SOFTWARE Real-Time OS (2/2) MX78K/0 is an OS for µ ITRON specification subsets. A nucleus for the MX78K/0 is MX78K0 also included as a companion product. This manages tasks, events, and time. In the task management, determining the task execution order and switching from task to the next task are performed.
APPENDIX D REGISTER INDEX D.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register 0 (ADCR0) … 230, 245 A/D converter mode register (ADM0) … 232, 249 Analog input channel specification register (ADS0) … 234, 251 Asynchronous serial interface mode register (ASIM0) …...
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APPENDIX D REGISTER INDEX Oscillation stabilization time select register (OSTS) … 382 Port 0 (P0) … 124 Port 1 (P1) … 125 Port 2 (P2) … 126 Port 3 (P3) … 127, 129 Port 4 (P4) … 132 Port 5 (P5) … 133 Port 6 (P6) …...
APPENDIX D REGISTER INDEX D.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR0 A/D conversion result register 0 … 230, 245 ADM0 A/D converter mode register … 232, 249 ADS0 Analog input channel specification register … 234, 251 ASIM0 Asynchronous serial interface mode register …...
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APPENDIX D REGISTER INDEX Port 0 … 124 Port 1 … 125 Port 2 … 126 Port 3 … 127, 129 Port 4 … 132 Port 5 … 133 Port 6 … 134 Port 7 … 135 Processor clock control register … 143 Port mode register 0 …...
APPENDIX E REVISION HISTORY The following shows the revision history up to present. Application portions signifies the chapter of each edition. (1/3) Edition No. Main revised contents from old edition Revised Sections CHAPTER 3 PIN FUNC- 2nd edition Recommended Connection of Unused IC, Vpp pins Changed TION ( µ...
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APPENDIX E REVISION HISTORY (2/3) Edition No. Main revised contents from old edition Revised Sections CHAPTER 19 INTER- 2nd edition The following two items removed from External Interrupt RUPT FUNCTIONS • Detect T100/P70/TO0 Pin Input Edge • Detect T101/P71 Pin Input Edge 1.8 V →...
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APPENDIX E REVISION HISTORY (3/3) Edition No. Main revised contents from old edition Revised Sections 4th Edition Addition of caution regarding setting values for memory size switching register CHAPTER 5 CPU to 5.1 Memory Spaces ARCHITECTURE CHAPTER 8 16-BIT Change and addition of Caution to 8.3 16-bit Timer/Event Counter Configu- TIMER/EVENT ration (2) Capture/compare register00(CR00), (3) Capture/compare COUNTER...
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Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.
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