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In applications of SEF protection, it must be ensured that any erroneous zero-phase current is
sufficiently low compared to the fault current, so that a highly sensitive setting is available.
The erroneous current may be caused with load current due to unbalanced configuration of the
distribution lines, or mutual coupling from adjacent lines. The value of the erroneous current
during normal conditions can be acquired on the metering screen of the relay front panel.
The earth fault current for SEF may be fed from a core balance CT, but if it is derived from three
phase CTs, the erroneous current may be caused also by the CT error in phase faults. Transient
false functioning may be prevented by a relatively long time delay.
Scheme Logic
Figure 2.1.19 shows the scheme logic of sensitive earth fault protection SEF1 with inverse time or
definite time selective two-stage earth fault protection.
In Figure 2.1.19, the definite time protection is selected by setting [MSE1] to "DT". The element
SEF1D is enabled for sensitive earth fault protection and stage 1 trip signal SEF1 TRIP is given
through the delayed pick-up timer TSE1.
The inverse time protection is selected by setting [MSE1] to either "IEC", "IEEE", "US" or
"CON" according to the inverse time characteristic to employ. The element SEF1I is enabled and
stage 1 trip signal SEF1 TRIP is given.
Both protection provide stage 2 trip signal SEF1-S2 through a delayed pick-up timer TSE12.
When the standby earth fault protection is applied by introducing earth current from the
transformer low voltage neutral circuit, stage 1 trip signals are used to trip the transformer low
voltage circuit breaker. If SEF1D or SEF1I continues operating after stage 1 has operated, the
stage 2 trip signal can be used to trip the transformer high voltage circuit breaker(s).
ICD is the inrush current detector ICD, which detects second harmonic inrush current during
transformer energisation, and can block the SEF1D element by the scheme switches [SEF1-2F].
See Section 2.1.7.
SEFHS element is used for blocked overcurrent protection. See Section 2.1.1.9.
The SEF protection can be disabled by the scheme switch [SE1EN] or binary input signal SEF1
BLOCK. Stage 2 trip of standby earth fault protection can be disabled by the scheme switch
[SE1S2].
The SEF2 protection provides the same logic of SEF1 except for the stage 2 trip as shown in
Figure 2.1.20.
F
Power
Transformer
Varistor
GRD150
Stabilising
SEF input
Resistor
Figure 2.1.18
High Impedance REF
⎯
⎯
28
6 F 2 S 0 8 4 2
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