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The OC1 and OC2 protections can be disabled by the scheme switches [OC1EN] and [OC2EN] or
PLC logic signals OC1 BLOCK and OC2 BLOCK.
Figure 2.1.11 and Figure 2.1.12 show the scheme logic of the definite time phase overcurrent
protection OC3 and OC4. The OC3 and OC4 give trip and alarm signals OC3 TRIP and OC4
ALARM through delayed pick-up timers TOC3 and TOC4.
The OC3 and OC4 protections can be disabled by the scheme switches [OC3EN] and [OC4EN] or
PLC logic signals OC3 BLOCK and OC4 BLOCK.
The OC3 and OC4 can also be blocked by the ICD.
Note:
For the symbols used in the scheme logic, see Appendix L.
20, 1712
A
21, 1713
OC1I
B
22, 1714
C
[MOC1]
+
"IEC"
"IEEE"
"US"
"CON"
"DT"
4, 1696
A
5, 1697
B
OC1D
6, 1698
C
OP. BLOCK
[OC1-2F]
+
&
"BLK"
28, 1720
A
29, 1721
≥1
B
ICD
30, 1722
C
ICD
[OC1EN]
+
"ON"
1
1536
OC1 BLOCK
Figure 2.1.9
&
&
&
TOC1
t
0
&
0
t
&
0
t
&
0.00 - 300.00s
OC1 Phase Fault Overcurrent Protection
⎯
⎯
19
6 F 2 S 0 8 4 2
386
OC1-A TRIP
≥1
387
OC1-B TRIP
≥1
388
OC1-C TRIP
≥1
385
≥ 1
OC1 TRIP
76, 1768
A
77, 1769
OCHS
B
78, 1770
C
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