IBM System x iDataPlex dx360 M4 7912 Service Manual page 332

Problem determination
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The following diagram lists the DIMM connectors on each memory channel.
The following table shows the memory channel interface layout with the DIMM
installation sequence for memory mirrored channel:
The following table shows the installation sequence for memory-mirroring mode:
Memory rank sparing
The memory rank sparing feature disables the failed memory from the system
configuration and activates a rank sparing DIMM to replace the failed active DIMM.
You can enable either memory rank sparing or memory mirrored channel in the
Setup utility (see "Using the Setup utility" on page 345). When you use the memory
rank sparing feature, consider the following information:
v The memory rank sparing feature is supported on server models with an Intel
v When you enable the memory rank sparing feature, you must install two or three
v The maximum available memory is reduced to two-thirds or one-half of the
Installing a DIMM
To install a DIMM, complete the following steps:
314
System x iDataPlex dx360 M4 Types 7912 and 7913: Problem Determination and Service Guide
Microprocessor 2
CPU2
Table 12. Memory channel interface layout
Memory channel
Channel 0
Channel 1
Channel 2
Channel 3
Table 13. Memory mirroring mode DIMM population sequence
Number of installed microprocessor
Microprocessor 1 (1 CPU only)
Microprocessor 1 and microprocessor 2
Xeon
E5-2600 series microprocessor.
DIMMs on the same channel per microprocessor at a time. The first two DIMMs
must be in the same channel. The sparing DIMM must be identical or larger in
size, type, rank, and organization, but not in speed. The channels run at the
speed of the slowest DIMM in any of the channels.
installed memory when memory rank sparing mode is enabled.
1. Read the safety information that begins on page vii and "Installation guidelines"
on page 275.
2. Turn off the server and peripheral devices and disconnect the power cords and
all external cables, if necessary.
Channel
Microprocessor 1
DIMM connector
7, 8, 15, 16
5, 6, 13, 14
1, 2, 9, 10
3, 4, 11, 12
DIMM connector in pair
1, 3-> 6, 8-> 2, 4-> 5, 7
1, 3, 9, 11-> 6, 8, 14, 16-> 2, 4, 10,
12-> 5, 7, 13, 15
CPU1

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