Sign In
Upload
Manuals
Brands
ST Manuals
Microcontrollers
STM32L021K4
ST STM32L021K4 Manuals
Manuals and User Guides for ST STM32L021K4. We have
1
ST STM32L021K4 manual available for free PDF download: Errata Sheet
ST STM32L021K4 Errata Sheet (23 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Summary of Device Errata
2
Description of Device Errata
4
System
4
Delay after an RCC Peripheral Clock Enabling
4
I2C and USART Cannot Wake up the Device from Stop Mode
4
LDM, STM, PUSH and POP Not Allowed in IOPORT Bus
4
BOOT_MODE Bits Do Not Reflect the Selected Boot Mode
5
NSS Pin Synchronization Required When Using Bootloader with SPI1 Interface on TSSOP14 Package
5
Dma
5
DMA Disable Failure and Error Flag Omission Upon Simultaneous Transfer Error and Global
5
Flag Clear
5
Byte and Half-Word Accesses Not Supported
5
Adc
6
Overrun Flag Is Not Set if EOC Reset Coincides with New Conversion End
6
Writing ADC_CFGR1 Register While ADEN Bit Is Set Resets RES[1:0] Bitfield
6
Out-Of-Threshold Value Is Not Detected in AWD1 Single Mode
6
Comp
6
COMP1_CSR and COMP2_CSR Lock Bit Reset by SYSCFGRST Bit in RCC_APB2RSTR
6
Register
6
Tim
7
PWM Re-Enabled in Automatic Output Enable Mode Despite of System Break
7
TRGO and TRGO2 Trigger Output Failure
7
Consecutive Compare Event Missed in Specific Conditions
7
Output Compare Clear Not Working with External Counter Reset
8
Lptim
8
Device May Remain Stuck in LPTIM Interrupt When Entering Stop Mode
8
Device May Remain Stuck in LPTIM Interrupt When Clearing Event Flag
9
LPTIM Events and PWM Output Are Delayed by 1 Kernel Clock Cycle
9
Iwdg
10
IWDG Does Not Always Reset the Device
10
RTC and TAMP
10
RTC Calendar Registers Are Not Locked Properly
10
RTC Interrupt Can be Masked by Another RTC Interrupt
10
Calendar Initialization May Fail in Case of Consecutive INIT Mode Entry
11
Alarm Flag May be Repeatedly Set When the Core Is Stopped in Debug
12
10-Bit Master Mode: New Transfer Cannot be Launched if First Part of the Address Is Not
12
Acknowledged by the Slave
12
Wrong Behavior in Stop Mode
13
Wrong Data Sampling When Data Setup Time (T SU;DAT ) Is Shorter than One I2C Kernel Clock Period
13
Spurious Bus Error Detection in Master Mode
13
Last-Received Byte Loss in Reload Mode
14
Spurious Master Transfer Upon Own Slave Address Match
14
START Bit Is Cleared Upon Setting ADDRCF, Not Upon Address Match
15
OVR Flag Not Set in Underrun Condition
15
Transmission Stalled after First Byte Transfer
15
Usart
16
RTS Is Active While RE = 0 or UE = 0
16
Receiver Timeout Counter Wrong Start in Two-Stop-Bit Configuration
16
Data Corruption Due to Noisy Receive Line
16
DMA Channel 3 (CH3) Not Functional When USART2_RX Used for Data Reception
16
Lpuart
16
DMA Channel 5 (CH5) Not Functional When LPUART1_RX Used for Data Reception
16
Spi
17
BSY Bit May Stay High When SPI Is Disabled
17
BSY Bit May Stay High at the End of Data Transfer in Slave Mode
17
Corrupted Last Bit of Data And/Or CRC, Received in Master Mode with Delayed SCK Feedback
17
Wrong CRC in Full-Duplex Mode Handled by DMA with Imbalanced Setting of Data Counters
18
CRC Error in SPI Slave Mode if Internal NSS Changes before CRC Transfer
18
Anticipated Communication Upon SPI Transit from Slave Receiver to Master
18
Revision History
20
Advertisement
Advertisement
Related Products
ST STM32L021 3 Series
ST STM32L021 4 Series
ST STM32L021G4
ST STM32L021F4
ST STM32L021D4
ST STM32L011 4 Series
ST STM32L011K4
ST STM32L011D3
ST STM32L011D4
ST STM32L011F3
ST Categories
Motherboard
Computer Hardware
Microcontrollers
Control Unit
Controller
More ST Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL