ST STM32F3 Series Programming Manual page 61

PM0214
Constant
You specify an operand2 constant in the form #constant, where constant can be:
•
Any constant that can be produced by shifting an 8-bit value left by any number of bits
within a 32-bit word.
•
Any constant of the form 0x00XY00XY
•
Any constant of the form 0xXY00XY00
•
Any constant of the form 0xXYXYXYXY
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can include a wider range of values.
These are described in the individual instruction descriptions.
When an operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS,
ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the
constant is greater than 255 and can be produced by shifting an 8-bit value. These
instructions do not affect the carry flag if operand2 is any other constant.
Instruction substitution
The assembler might be able to produce an equivalent instruction if a not permitted constant
is specified. For example, the instruction CMP Rd, #0xFFFFFFFE might be assembled as
the equivalent of instruction CMN Rd, #0x2.
Register with optional shift
An operand2 register is specified in the form Rm {, shift}, where:
•
Rm is the register holding the data for the second operand
•
Shift is an optional shift to be applied to Rm. It can be one of the following:
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is
used by the instruction. However, the contents in the Rm register remain unchanged.
Specifying a register with shift also updates the carry flag when used with certain
instructions. For information on the shift operations and how they affect the carry flag, see
Shift operations.
ASR #n: Arithmetic shift right n bits, 1 ≤ n ≤ 32
LSL #n: Logical shift left n bits, 1 ≤ n ≤ 31
LSR #n: Logical shift right n bits, 1 ≤ n ≤ 32
ROR #n: Rotate right n bits, 1 ≤ n ≤ 31
RRX: Rotate right one bit, with extend
—: If omitted, no shift occurs, equivalent to LSL #0
The STM32 Cortex-M4 instruction set
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