System Control Register (Scr) - ST STM32F3 Series Programming Manual

Core peripherals
4.4.6

System control register (SCR)

Address offset: 0x10
Reset value: 0x0000 0000
Required privilege: Privileged
The SCR controls features of entry to and exit from low power state.
31 30 29 28
15 14 13 12
Bits 31:5 Reserved, must be kept cleared
Bit 4 SEVEONPEND Send Event on Pending bit
When an event or interrupt enters pending state, the event signal wakes up the processor from
WFE. If the processor is not waiting for an event, the event is registered and affects the next
WFE.
The processor also wakes up on execution of an SEV instruction or an external event
Bit 3 Reserved, must be kept cleared
Bit 2 SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
Bit 1 SLEEPONEXIT
Configures sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to
1 enables an interrupt-driven application to avoid returning to an empty main application.
Bit 0 Reserved, must be kept cleared
230/262
27 26 25
11 10 9
Reserved
0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are
excluded
1: Enabled events and all interrupts, including disabled interrupts, can wakeup the
processor.
0: Sleep
1: Deep sleep.
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an interrupt service routine.
24 23 22
Reserved
8 7 6
PM0214 Rev 10
21 20 19 18
5 4 3 2
SEVON SLEEP
PEND DEEP
Res.
rw rw
PM0214
17 16
1 0
SLEEP
ON
Res.
EXIT
rw