Mpu Region Base Address Register (Mpu_Rbar) - ST STM32F3 Series Programming Manual

PM0214
4.2.8

MPU region base address register (MPU_RBAR)

Address offset: 0x0C
Reset value: 0x0000 0000
Required privilege: Privileged
The MPU_RBAR register defines the base address of the MPU region selected by the
MPU_RNR register, and can update the value of the MPU_RNR register.
Write to the MPU_RBAR register with the VALID bit set to 1 to change the current region
number and update the MPU_RNR register.
31 30 29 28
15 14 13 12
Bits 31:N ADDR[31:N]: Region base address field
The value of N depends on the region size.
The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N:
If the region size is configured to 4 GB, in the MPU_RASR register, there is no valid ADDR
field. In this case, the region occupies the complete memory map, and the base address is
0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be
aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000.
Bits N-1:5 Reserved, forced by hardware to 0.
Bit 4 VALID: MPU region number valid
Write:
Read:
Bits 3:0 REGION[3:0]: MPU region field
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR register.
27 26 25
11 10 9
....ADDR[31:N]
N = Log2(Region size in bytes),
0: MPU_RNR register not changed, and the processor:
– Updates the base address for the region specified in the MPU_RNR
– Ignores the value of the REGION field
1: the processor:
– updates the value of the MPU_RNR to the value of the REGION field
– updates the base address for the region specified in the REGION field.
Always read as zero.
24 23 22
ADDR[31:N]...
8 7 6
PM0214 Rev 10
Core peripherals
21 20 19 18
5 4 3 2
VALID REGION[3:0]
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17 16
1 0
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