Mpu Control Register (Mpu_Ctrl) - ST STM32F3 Series Programming Manual

PM0214
4.2.6

MPU control register (MPU_CTRL)

Address offset: 0x04
Reset value: 0x0000 0000
Required privilege: Privileged
The MPU_CTRL register:
•
Enables the MPU
•
Enables the default memory map background region
•
Enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in
Memory model on page
an enabled memory region behaves as defined by the default memory map.
•
Any access by unprivileged software that does not address an enabled memory region
causes a memory management fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the
value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled
for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is
set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the
same memory attributes as if the MPU is not implemented, see
behavior on page
and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are
always permitted. Other areas are accessible based on regions and whether PRIVDEFENA
is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the
handler for an exception with priority –1 or –2. These priorities are only possible when
handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the
HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
31 30 29 28
15 14 13 12
28. Any access by privileged software that does not address
30. The default memory map applies to accesses from both privileged
27 26 25 24
Reserved
11 10 9 8
Reserved
PM0214 Rev 10
23 22 21 20
7 6 5 4
Core peripherals
Section 2.2:
Table 13: Memory access
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3 2 1
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