Core Peripherals; About The Stm32 Cortex-M4 Core Peripherals; Memory Protection Unit (Mpu); Table 37. Stm32 Core Peripheral Register Regions - ST STM32F3 Series Programming Manual

PM0214
4

Core peripherals

4.1

About the STM32 Cortex-M4 core peripherals

The address map of the Private peripheral bus (PPB) is:
0xE000E010-0xE000E01F
0xE000E100-0xE000E4EF
0xE000ED00-0xE000ED3F System control block
0xE000ED88-0xE000ED8B
0xE000ED90-0xE000EDB8 Memory protection unit
0xE000EF00-0xE000EF03
0xE000EF30-0xE000EF44
In register descriptions,
•
Register type is described as follows:
–
–
–
•
Required privilege gives the privilege level required to access the register, as follows:
–
–
4.2

Memory protection unit (MPU)

This section describes the Memory protection unit (MPU) which is implemented in some
STM32 microcontrollers. Refer to the corresponding device datasheet to see if the MPU is
present in the STM32 type you are using.
The MPU divides the memory map into a number of regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
•
Independent attribute settings for each region
• Overlapping regions
•
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-
M4 MPU defines:
•
Eight separate memory regions, 0-7
•
A background region.

Table 37. STM32 core peripheral register regions

Address
System timer
Nested vectored interrupt
controller
Floating point unit
coprocessor access control
Nested vectored interrupt
controller
Floating point unit
RW: Read and write.
RO: Read-only.
WO: Write-only.
Privileged: Only privileged software can access the register.
Unprivileged: Both unprivileged and privileged software can access the register.
Core peripheral
PM0214 Rev 10
Core peripherals
Description
Table 55 on page 251
Table 49 on page 219
Table 53 on page 244
Table 56 on page 252
Table 44 on page 206
Table 49 on page 219
Table 56 on page 252
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