Level-Sensitive And Pulse Interrupts - ST STM32F3 Series Programming Manual

PM0214
4.3.9

Level-sensitive and pulse interrupts

STM32 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal.
Typically this happens because the ISR accesses the peripheral, causing it to clear the
interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral
must assert the interrupt signal for at least one clock cycle, during which the NVIC detects
the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see
the signal is not deasserted before the processor returns from the ISR, the interrupt
becomes pending again, and the processor must execute its ISR again. This means that the
peripheral can hold the interrupt signal asserted until it no longer needs servicing.
Hardware and software control of interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the
following reasons:
• The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
•
The NVIC detects a rising edge on the interrupt signal
• Software writes to the corresponding interrupt set-pending register bit, see
Section 4.3.4: Interrupt set-pending register x
an SGI pending, see
A pending interrupt remains pending until one of the following:
•
The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
–
–
•
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
–
–
Hardware and software control of
Section 4.3.8: Software trigger interrupt register
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR. If the
interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
Inactive, if the state was pending
Active, if the state was active and pending.
interrupts. For a level-sensitive interrupt, if
(NVIC_ISPRx), or to the STIR to make
PM0214 Rev 10
Core peripherals
(NVIC_STIR).
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