ST STM32F3 Series Programming Manual page 90

The STM32 Cortex-M4 instruction set
Restrictions
You can use SP and PC only in the MOV instruction, with the following restrictions:
•
The second operand must be a register without shift
•
You must not specify the S suffix
When Rd is PC in a MOV instruction:
• bit[0] of the value written to the PC is ignored
•
A branch occurs to the address created by forcing bit[0] of that value to 0.
Note: Though it is possible to use MOV as a branch instruction, Arm strongly recommends the use
of a BX or BLX instruction to branch for software portability to the Arm instruction set.
Condition flags
If S is specified, these instructions:
•
Update the N and Z flags according to the result
•
Can update the C flag during the calculation of operand2 (see
on page
•
Do not affect the V flag
Example
MOVS R11, #0x000B
MOV R1, #0xFA05
MOVS R10, R12
MOV R3, #23
MOV R8, SP
MVNS R2, #0xF
90/262
60).
; write value of 0x000B to R11, flags get updated
; write value of 0xFA05 to R1, flags not updated
; write value in R12 to R10, flags get updated
; write value of 23 to R3
; write value of stack pointer to R8
; write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
PM0214 Rev 10
PM0214
Flexible second operand