Interrupt Active Bit Register X (Nvic_Iabrx) - ST STM32F3 Series Programming Manual

Core peripherals
4.3.6

Interrupt active bit register x (NVIC_IABRx)

Address offset: 0x300 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_IABR0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_IABR1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_IABR6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_IABR7 bits 0 to 15 are for interrupt 224 to 239, respectively
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:0 ACTIVE: Interrupt active flags
A bit reads as 1 if the status of the corresponding interrupt is active or active and pending.
Bits 16 to 31 of the NVIC_IABR7 register are reserved.
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
214/262
27 26 25
r r r r
11 10 9
r r r r
0: Interrupt not active
1: Interrupt active
24 23 22
ACTIVE[31:16]
r r r
8 7 6
ACTIVE[15:0]
r r r
PM0214 Rev 10
21 20 19 18
r r r r
5 4 3 2
r r r r
PM0214
17 16
r r
1 0
r r