Usage Fault Status Register (Ufsr) - ST STM32F3 Series Programming Manual

Core peripherals
4.4.11

Usage fault status register (UFSR)

Bits 31:26 Reserved, must be kept cleared
Bit 25 DIVBYZERO: Divide by zero usage fault. When the processor sets this bit to 1, the PC value
stacked for the exception return points to the instruction that performed the divide by zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
Configuration and control register (CCR) on page
0: No divide by zero fault, or divide by zero trapping not enabled
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
Bit 24 UNALIGNED: Unaligned access usage fault. Enable trapping of unaligned accesses by
setting the UNALIGN_TRP bit in the CCR to 1, see
on page
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
0: No unaligned access fault, or unaligned access trapping not enabled
1: the processor has made an unaligned memory access.
Bits 23:20 Reserved, must be kept cleared
Bit 19 NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor
1: the processor has attempted to access a coprocessor.
Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that tried to perform the illegal load of the PC.
0: No invalid PC load usage fault
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an
invalid context, or an invalid EXC_RETURN value.
Bit 17 INVSTATE: Invalid state usage fault. When this bit is set to 1, the PC value stacked for the
exception return points to the instruction that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
0: No invalid state usage fault
1: The processor has attempted to execute an instruction that makes illegal use of the
EPSR.
Bit 16 UNDEFINSTR: Undefined instruction usage fault. When this bit is set to 1, the PC value
stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
0: No undefined instruction usage fault
1: The processor has attempted to execute an undefined instruction.
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PM0214 Rev 10
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Configuration and control register (CCR)
PM0214