System Handler Control And State Register (Shcsr) - ST STM32F3 Series Programming Manual

PM0214
4.4.9

System handler control and state register (SHCSR)

Address offset: 0x24
Reset value: 0x0000 0000
Required privilege: Privileged
The SHCSR enables the system handlers, and indicates:
•
The pending status of the bus fault, memory management fault, and SVC exceptions
•
The active status of the system handlers.
If you disable a system handler and the corresponding fault occurs, the processor treats the
fault as a hard fault.
You can write to this register to change the pending or active status of system exceptions.
An OS kernel can write to the active bits to perform a context switch that changes the
current exception type.
•
Software that changes the value of an active bit in this register without correct
adjustment to the stacked content can cause the processor to generate a fault
exception. Ensure software that writes to this register retains and subsequently
restores the current active status.
•
After you have enabled the system handlers, if you have to change the value of a bit in
this register you must use a read-modify-write procedure to ensure that you change
only the required bit.
31 30 29 28
15 14 13 12
SV BUS MEM USG
CALL FAULT FAULT FAULT
PEND PEND PEND PEND
ED ED ED ED
rw rw rw rw
Bits 31:19 Reserved, must be kept cleared
Bit 18 USGFAULTENA: Usage fault enable bit, set to 1 to enable
Bit 17 BUSFAULTENA: Bus fault enable bit, set to 1 to enable
Bit 16 MEMFAULTENA: Memory management fault enable bit, set to 1 to enable
Bit 15 SVCALLPENDED: SVC call pending bit, reads as 1 if exception is pending
Bit 14 BUSFAULTPENDED: Bus fault exception pending bit, reads as 1 if exception is pending
Bit 13 MEMFAULTPENDED: Memory management fault exception pending bit, reads as 1 if
exception is pending
Bit 12 USGFAULTPENDED: Usage fault exception pending bit, reads as 1 if exception is pending
Bit 11 SYSTICKACT: SysTick exception active bit, reads as 1 if exception is active
Bit 10 PENDSVACT: PendSV exception active bit, reads as 1 if exception is active
Bit 9 Reserved, must be kept cleared
27 26 25 24
Reserved
11 10 9 8
SYS PEND MONIT
TICK SV OR
Res.
ACT ACT ACT
rw rw rw
(2)
PM0214 Rev 10
23 22 21 20
7 6 5
SV
CALL
Reserved
ACT
rw
(1)
(1)
Core peripherals
19 18 17
USG BUS
FAULT FAULT
ENA ENA
rw rw
4 3 2 1
USG BUS
FAULT FAULT
Res.
ACT ACT
rw rw
(1)
(2)
(3)
16
MEM
FAULT
ENA
rw
0
MEM
FAULT
ACT
rw
(2)
(2)
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