Floating-Point Default Status Control Register (Fpdscr); Enabling The Fpu - ST STM32F3 Series Programming Manual

PM0214
4.6.5

Floating-point default status control register (FPDSCR)

Address offset: 0x0C
Reset value: 0x0000000
Required privilege: Privileged
The FPDSCR register holds the default values for the floating-point status control data.
31 30 29 28
Reserved
15 14 13 12
Bits 31:27 Reserved, must be kept cleared.
Bit 26 AHP: Default value for FPSCR.AHP
Bit 25 DN: Default value for FPSCR.DN
Bit 24 FZ: Default value for FPSCR.FZ
Bits 23:22 RMode: Default value for FPSCR.RMode
Bits 21:0 Reserved, must be kept cleared.
4.6.6

Enabling the FPU

The FPU is disabled from reset. You must enable it before you can use any floating-point
instructions.
The example shows an example code sequence for enabling the FPU in both privileged and
user modes. The processor must be in privileged mode to read from and write to the
CPACR.
Example
LDR.W
LDR
ORR
STR
DSB
;reset pipeline now the FPU is enabled
ISB
27 26 25
AHP DN
rw rw
11 10 9
; CPACR is located at address 0xE000ED88
R0, =0xE000ED88
; Read CPACR
R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
R1, [R0]; wait for store to complete
24 23 22
FZ RMode
rw rw rw
8 7 6
Reserved
PM0214 Rev 10
Core peripherals
21 20 19 18
Reserved
5 4 3 2
17 16
1 0
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