Interrupt Set-Pending Register X (Nvic_Isprx) - ST STM32F3 Series Programming Manual

Core peripherals
4.3.4

Interrupt set-pending register x (NVIC_ISPRx)

Address offset: 0x200 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_ISPR0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_ISPR1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_ISPR6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_ISPR7 bits 0 to 15 are for interrupt 224 to 239, respectively
31 30 29 28
rs rs rs rs
15 14 13 12
rs rs rs rs
Bits 31:0 SETPEND: Interrupt set-pending bits
Write:
Read:
Writing 1 to the ISPR bit corresponding to an interrupt that is pending has no effect.
Writing 1 to the ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to
pending.
Bits 16 to 31 of the NVIC_ISPR7 register are reserved.
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
212/262
27 26 25
rs rs rs
11 10 9
rs rs rs
0: No effect
1: Changes interrupt state to pending
0: Interrupt is not pending
1: Interrupt is pending
24 23 22
SETPEND[31:16]
rs rs rs
8 7 6
SETPEND[15:0]
rs rs rs
PM0214 Rev 10
21 20 19 18
rs rs rs rs
5 4 3 2
rs rs rs rs
PM0214
17 16
rs rs
1 0
rs rs