Configurable Fault Status Register (Cfsr; Ufsr+Bfsr+Mmfsr); Figure 20. Cfsr Subregisters - ST STM32F3 Series Programming Manual

PM0214
4.4.10

Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)

Address offset: 0x28
Reset value: 0x0000 0000
Required privilege: Privileged
The following subsections describe the subregisters that make up the CFSR:
•
Usage fault status register (UFSR) on page 238
•
Bus fault status register (BFSR) on page 239
•
Memory management fault address register (MMFSR) on page 240
The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
•
Access the complete CFSR with a word access to 0xE000ED28
•
Access the MMFSR with a byte access to 0xE000ED28
•
Access the MMFSR and BFSR with a halfword access to 0xE000ED28
•
Access the BFSR with a byte access to 0xE000ED29
•
Access the UFSR with a halfword access to 0xE000ED2A.
The CFSR indicates the cause of a memory management fault, bus fault, or usage fault.
31
31 30 29 28
Reserved
15 14 13 12
BFARV LSP STK
Reserv
ALID ERR ERR
ed
rw rw rw
Bits 31:16 UFSR: see
Bits 15:8 BFSR: see
Bits 7:0 MMFSR: see

Figure 20. CFSR subregisters

Usage Fault Status Register
UFSR
27 26 25
DIVBY UNALI
ZERO GNED
rc_w1 rc_w1
11 10 9
IMPRE
UNSTK PRECI IBUS
CIS
ERR S ERR ERR
ERR
rw rw rw
Usage fault status register (UFSR) on page 238
Bus fault status register (BFSR) on page 239
Memory management fault address register (MMFSR) on page 240
PM0214 Rev 10
16 15
Bus Fault Status
Register
BFSR
24 23 22 21
Reserved
8 7 6 5
MMAR MLSP
Reserv
VALID ERR
ed
rw rw rw
Core peripherals
8 7
Memory Management
Fault Status Register
MMFSR
20 19 18 17
INV
NOCP INVPC
STATE
rc_w1 rc_w1 rc_w1
4 3 2
M
MSTK DACC
UNSTK
ERR VIOL
Res.
ERR
rw rw rw
0
16
UNDEF
INSTR
rc_w1
1 0
IACC
VIOL
rw
237/262
261