Alinx ZYNQ UltraScale+ User Manual page 8

Figure 1-1-1: The Schematic Diagram of the AXU9EG
Through this diagram, you can see the interfaces and functions that the
AXU9EG FPGA Development Board contains:
 ZU9EG core board
It consists of ZU9EV +4GB DDR4 （PS） +2GB DDR4 （PL） +8GB eMMC
FLASH + 512Mb QSPI FLASH, and there are 2 crystal oscillators to
provide the clock, a single-ended 33.3333MHz crystal oscillator for the
PS system, and a differential 200MHz crystal oscillator for the PL logic
DDR reference clock.
 M.2 Interface
1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state
drives, with a communication speed of up to 6Gbps.
 DP Output Interface
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
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