Alinx ZYNQ7000 FPGA User Manual
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Alinx ZYNQ7000 FPGA User Manual

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ZYNQ7000 FPGA
Development Board
AX7Z100
User Manual

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  • Page 1 ZYNQ7000 FPGA Development Board AX7Z100 User Manual...

  • Page 2: Version Record

    ZYNQ FPGA Development Board AX7Z100 User Manual Version Record Version Date Release By Description Rev 1.0 2019-04-28 Rachel Zhou First Release Amazon Store: https://www.amazon.com/alinx 2 / 61...

  • Page 3: Table Of Contents

    Part 3.8: PCIe Slot ................51 Part 3.9: SD Card Slot ............... 53 Part 3.10: Expansion Header ............54 Part 3-11: LED Light ................56 Part 3-12: Reset Button and User Button .......... 57 Amazon Store: https://www.amazon.com/alinx 3 / 61...
  • Page 4 ZYNQ FPGA Development Board AX7Z100 User Manual Part 3-13: JTAG Debug Port ............. 58 Part 3-14: DIP Switch Configuration ..........58 Part 3-15: Power Supply ..............59 Part 3.16: Fan ..................60 Part 3.17: Dimensional structure ............60 Amazon Store: https://www.amazon.com/alinx 4 / 61...
  • Page 5 ZYNQ FPGA Development Board AX7Z100 User Manual This ZYNQ7000 FPGA development platform adopts the core board + carrier board mode, which is convenient for users to use the core board for secondary development. The core board uses XILINX's Zynq7000 SOC chip XC7Z100 solution, uses ARM+FPGA SOC technology to integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip.

  • Page 6: Part 1: Fpga Development Board Introduction

    PCIex8 slot, four SFP interfaces, two Gigabit Ethernet interfaces (one for PS and one for PL), four USB2.0 HOST interfaces, one HDMI output interface, one HDMI input interface, and one UART serial interface. 1 SD card interface, 40-pin expansion header and some buttons. Amazon Store: https://www.amazon.com/alinx 6 / 61...
  • Page 7 5GBaud.  4 SFP Interface The 4-channel high-speed transceiver of ZYNQ's GTX transceiver is connected to the transmission and reception of four optical modules to Amazon Store: https://www.amazon.com/alinx 7 / 61...
  • Page 8 The serial port chip adopts the USB-UAR chip of Silicon Labs CP2102GM, and the USB interface adopts the MINI USB interface.  Micro SD card holder 1-port Micro SD card holder, use to store operating system images and Amazon Store: https://www.amazon.com/alinx 8 / 61...

  • Page 9: Part 2: Ac7Z100 Core Board

     40-pin expansion port A 40-pin 2.54mm pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1 channel 5V power supply, 2 channel 3.3V power supply, 3 way ground, 34 IOs port.
  • Page 10 ZYNQ chip and the interface is equal length and differential processing, and the core board size is only 80*60 (mm), which is very suitable for secondary development. Figure 2-1-1: AC7Z100 Core Board (Front View) Amazon Store: https://www.amazon.com/alinx 10 / 61...

  • Page 11: Part 2.2: Zynq Chip

    Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface, UART interface, GPIO etc. The PS can operate independently and start up at power on or reset. Figure 2-2-1 detailed the Overall Block Diagram of the ZYNQ7000 Chip. Amazon Store: https://www.amazon.com/alinx 11 / 61...
  • Page 12  Two SD card, SDIO, MMC compatible controllers  2 SPIs, 2 UARTs, 2 I2C interfaces  54 multi-function IOs that can be configured as normal IO or peripheral control interfaces  High bandwidth connection within PS and PS to PL Amazon Store: https://www.amazon.com/alinx 12 / 61...
  • Page 13 XC7Z100-2FFG900I chip speed grade is -2, industrial grade, package is FGG900, pin pitch is 1.0mm the specific chip model definition of ZYNQ7000 series is shown in Figure 2-2-2 Figure 2-2-2: The Specific Chip Model Definition of ZYNQ7000 Series Amazon Store: https://www.amazon.com/alinx 13 / 61...

  • Page 14: Part 2.3: Ddr3 Dram

    BANK34 interfaces of the FPGA. The specific configuration of DDR3 SDRAM is shown in Table 2-3-1. Bit Number Chip Model Capacity Factory U4,U5,U7,U8 MT41J256M16HA-125 256M x 16bit Micron Table 2-3-1: DDR3 SDRAM Configuration The hardware design of DDR3 requires strict consideration of signal Amazon Store: https://www.amazon.com/alinx 14 / 61...
  • Page 15 DDR3. Figure 2-3-1: The Schematic Part of DDR3 DRAM on the PS side Figure 2-3-2: The Schematic Part of DDR3 DRAM on the PL side PS side DDR3 DRAM pin assignment: Amazon Store: https://www.amazon.com/alinx 15 / 61...
  • Page 16 PS_DDR_DQ7_502 PS_DDR3_D7 PS_DDR_DQ8_502 PS_DDR3_D8 PS_DDR_DQ9_502 PS_DDR3_D9 PS_DDR_DQ10_502 PS_DDR3_D10 PS_DDR_DQ11_502 PS_DDR3_D11 PS_DDR_DQ12_502 PS_DDR3_D12 PS_DDR_DQ13_502 PS_DDR3_D13 PS_DDR_DQ14_502 PS_DDR3_D14 PS_DDR_DQ15_502 PS_DDR3_D15 PS_DDR_DQ16_502 PS_DDR3_D16 PS_DDR_DQ17_502 PS_DDR3_D17 PS_DDR_DQ18_502 PS_DDR3_D18 PS_DDR_DQ19_502 PS_DDR3_D19 PS_DDR_DQ20_502 PS_DDR3_D20 PS_DDR_DQ21_502 PS_DDR3_D21 PS_DDR_DQ22_502 PS_DDR3_D22 PS_DDR_DQ23_502 PS_DDR3_D23 Amazon Store: https://www.amazon.com/alinx 16 / 61...
  • Page 17 PS_DDR_A4_502 PS_DDR3_A4 PS_DDR_A5_502 PS_DDR3_A5 PS_DDR_A6_502 PS_DDR3_A6 PS_DDR_A7_502 PS_DDR3_A7 PS_DDR_A8_502 PS_DDR3_A8 PS_DDR_A9_502 PS_DDR3_A9 PS_DDR_A10_502 PS_DDR3_A10 PS_DDR_A11_502 PS_DDR3_A11 PS_DDR_A12_502 PS_DDR3_A12 PS_DDR_A13_502 PS_DDR3_A13 PS_DDR_A14_502 PS_DDR3_A14 PS_DDR_BA0_502 PS_DDR3_BA0 PS_DDR_BA1_502 PS_DDR3_BA1 PS_DDR_BA2_502 PS_DDR3_BA2 PS_DDR_CS_B_502 PS_DDR3_S0 PS_DDR_RAS_B_502 PS_DDR3_RAS PS_DDR_CAS_B_502 PS_DDR3_CAS Amazon Store: https://www.amazon.com/alinx 17 / 61...
  • Page 18 IO_L21N_T3_DQS_33 PL_DDR3_DQS4_N IO_L5N_T0_33 PL_DDR3_D0 IO_L1N_T0_33 PL_DDR3_D1 IO_L4P_T0_33 PL_DDR3_D2 IO_L1P_T0_33 PL_DDR3_D3 IO_L2N_T0_33 PL_DDR3_D4 IO_L5P_T0_33 PL_DDR3_D5 IO_L2P_T0_33 PL_DDR3_D6 IO_L4N_T0_33 PL_DDR3_D7 IO_L7N_T1_33 PL_DDR3_D8 IO_L10N_T1_33 PL_DDR3_D9 IO_L7P_T1_33 PL_DDR3_D10 IO_L8N_T1_33 PL_DDR3_D11 IO_L11N_T1_SRCC_33 PL_DDR3_D12 IO_L8P_T1_33 PL_DDR3_D13 IO_L11P_T1_SRCC_33 PL_DDR3_D14 IO_L10P_T1_33 PL_DDR3_D15 Amazon Store: https://www.amazon.com/alinx 18 / 61...
  • Page 19 IO_L12P_T1_MRCC_33 PL_DDR3_DM1 IO_L13N_T2_MRCC_33 PL_DDR3_DM2 IO_L23N_T3_33 PL_DDR3_DM3 IO_L17N_T2_34 PL_DDR3_A0 IO_L23P_T3_34 PL_DDR3_A1 IO_L14P_T2_SRCC_34 PL_DDR3_A2 IO_L15N_T2_DQS_34 PL_DDR3_A3 IO_L10N_T1_34 PL_DDR3_A4 IO_L17P_T2_34 PL_DDR3_A5 IO_L11N_T1_SRCC_34 PL_DDR3_A6 IO_L15P_T2_DQS_34 PL_DDR3_A7 IO_L12N_T1_MRCC_34 PL_DDR3_A8 IO_L18N_T2_34 PL_DDR3_A9 IO_L24N_T3_34 PL_DDR3_A10 IO_L11P_T1_SRCC_34 PL_DDR3_A11 IO_L23N_T3_34 PL_DDR3_A12 IO_L16P_T2_34 PL_DDR3_A13 Amazon Store: https://www.amazon.com/alinx 19 / 61...

  • Page 20: Part 2.4: Qspi Flash

    ZYNQ chip. In the system design, the GPIO port functions of these PS ports need to be configured as the QSPI FLASH interface. Figure 2-4-1 shows the QSPI Flash in the schematic. Amazon Store: https://www.amazon.com/alinx 20 / 61...

  • Page 21: Part 2.5: Emmc Flash

    PS_MIO0_500 QSPI1_CS PS_MIO10_500 QSPI1_D0 PS_MIO11_500 QSPI1_D1 PS_MIO12_500 QSPI1_D2 PS_MIO13_500 QSPI1_D3 Part 2.5: eMMC Flash The FPGA core board AC7Z100 is equipped with a large-capacity 8GB eMMC FLASH chip, model THGBMFG6C1LBAIL, which supports the JEDEC Amazon Store: https://www.amazon.com/alinx 21 / 61...
  • Page 22 Flash in the schematic. MMC_CCLK MMC_CMD eMMC ZYNQ BANK (THGBMFG6C1 LBAIL) MMC_DAT0~MMC_DAT3 Figure 2-5-1: eMMC Flash in the Schematic Pin Assignment of eMMC Flash Signal Name ZYNQ Pin Name ZYNQ Pin Number PS_MIO48_501 MMC_CCLK PS_MIO47_501 MMC_CMD Amazon Store: https://www.amazon.com/alinx 22 / 61...

  • Page 23: Part 2.6: Clock Configuration

    X4 crystal on the FPGA core board AC7Z100. The input of the clock is connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2: Amazon Store: https://www.amazon.com/alinx 23 / 61...
  • Page 24 (MRCC) of the FPGA BANK34, which can be used to drive the DDR3 controller and user logic in the FPGA. The schematic diagram of the clock source is shown in Figure 2-6-3 Figure 2-6-3: PL system clock source Amazon Store: https://www.amazon.com/alinx 24 / 61...
  • Page 25 Figure 2-6-4. Figure 2-6-4: GTX Clock Source Figure 2-6-5: Programmable Clock Source on the AX7Z100 FPGA Core Board GTX clock source ZYNQ pin assignment:： Signal Name ZYNQ Pin BANK111_CLK1_P BANK111_CLK1_N Amazon Store: https://www.amazon.com/alinx 25 / 61...

  • Page 26: Part 2.7: Led Light

    PS reset pin of the ZYNQ chip. The user can use the buttons on the carrier board to reset the ZYNQ system. The schematic diagram of the reset connection is shown in Figure 2-8-1: Amazon Store: https://www.amazon.com/alinx 26 / 61...

  • Page 27: Part 2.9: Power Supply

    The AC7Z100 FPGA core board is powered by DC5V and is powered by a connection carrier board. The power supply design diagram on the FPGA board is shown in Figure 2-9-1 Figure 2-9-1：Power interface section in the schematic Amazon Store: https://www.amazon.com/alinx 27 / 61...
  • Page 28 Because the power supply of the ZYNQ FPGA has the power-on sequence requirements, in the circuit design, we have designed according to power requirements chip. power-on sequence +1.0V->+1.8V->(+1.5 V, +3.3V, VCCIO10,VCCIO11) circuit design to ensure Amazon Store: https://www.amazon.com/alinx 28 / 61...

  • Page 29: Part 2.10: Ac7Z100 Core Board Size Dimension

    The physical diagram of the power circuit on the AX7Z100 core board is shown in Figure 2-9-2: Figure 2-9-2: Power Supply on the AX7Z100 Core Board Part 2.10: AC7Z100 Core Board Size Dimension Figure 2-10-1: AC7Z100 Core Board Size Dimension Amazon Store: https://www.amazon.com/alinx 29 / 61...

  • Page 30: Part 2.11: Board To Board Connectors Pin Assignment

    B11_L12_N AF22 B11_L2_P AK22 B11_L12_P AE22 B11_L5_N AH24 B11_L16_N AK18 B11_L5_P AH23 B11_L16_P AK17 B11_L15_P AJ20 B11_L6_N AH22 B11_L15_N AK20 B11_L6_P AG22 B11_L13_N AH21 B11_L17_N AJ19 B11_L13_P AG21 B11_L17_P AH19 B11_L14_N AG20 B11_L18_N AG19 Amazon Store: https://www.amazon.com/alinx 30 / 61...
  • Page 31 B10_L5_P AJ15 B10_L18_P AD16 B10_L23_P AC17 B10_L18_N AD15 B10_L23_N AC16 B10_L14_N AG15 B10_L12_P AF14 B10_L14_P AF15 B10_L12_N AG14 B10_L1_P AK13 B10_L22_P AB15 B10_L1_N AK12 B10_L22_N AB14 B10_L8_P AH14 B10_L3_P AJ14 B10_L8_N AH13 B10_L3_N AJ13 Amazon Store: https://www.amazon.com/alinx 31 / 61...
  • Page 32 J30 Pin Signal Name J30 Pin Signal Name Number Number BANK111_TX0_N BANK111_RX0_N BANK111_TX0_P BANK111_RX0_P BANK111_TX1_N BANK111_RX1_N BANK111_TX1_P BANK111_RX1_P BANK111_TX2_N BANK111_RX2_N BANK111_TX2_P BANK111_RX2_P BANK111_TX3_N BANK111_RX3_N BANK111_TX3_P BANK111_RX3_P BANK111_CLK0_N BANK111_CLK1_N BANK111_CLK0_P BANK111_CLK1_P BANK112_TX0_N BANK112_RX0_N BANK112_TX0_P BANK112_RX0_P Amazon Store: https://www.amazon.com/alinx 32 / 61...
  • Page 33 BANK112_CLK0_N BANK112_CLK1_N BANK112_CLK0_P BANK112_CLK1_P BANK109_RX2_N BANK110_RX0_N BANK109_RX2_P BANK110_RX0_P BANK109_RX3_N BANK110_TX0_N BANK109_RX3_P BANK110_TX0_P BANK109_RX1_P BANK110_RX1_N BANK109_RX1_N BANK110_RX1_P BANK109_TX1_P BANK110_TX1_N BANK109_TX1_N BANK110_TX1_P BANK109_TX2_P BANK110_RX2_N BANK109_TX2_N BANK110_RX2_P BANK109_TX3_P BANK110_TX2_N BANK109_TX3_N BANK110_TX2_P AA12 BANK109_TX0_N BANK110_RX3_N BANK109_TX0_P AK10 BANK110_RX3_P Amazon Store: https://www.amazon.com/alinx 33 / 61...
  • Page 34 J31 Pin Signal Name J31 Pin Signal Name Number Number FPGA_TCK FPGA_TDI FPGA_TMS FPGA_TDO B35_L2_P B35_L8_N B35_L2_N B35_L8_P B35_L9_P B35_L3_N B35_L9_N B35_L3_P B35_L22_N B35_L5_P B35_L22_P B35_L5_N B35_L20_N B35_L10_P B35_L20_P B35_L10_N AA12 B35_L19_N B35_L12_N B35_L19_P B35_L12_P Amazon Store: https://www.amazon.com/alinx 34 / 61...
  • Page 35 ZYNQ FPGA Development Board AX7Z100 User Manual B35_L24_N B35_L11_N B35_L24_P B35_L11_P B35_L4_N B35_L23_P B35_L4_P B35_L23_N B35_L1_N B35_L21_P B35_L1_P B35_L21_N B35_L16_N B35_L14_P B35_L16_P B35_L14_N B35_L18_N B35_L13_N B35_L18_P B35_L13_P B35_L15_N B35_L17_N B35_L15_P B35_L17_P B35_L7_N B35_L7_P B35_L6_N B35_L6_P Amazon Store: https://www.amazon.com/alinx 35 / 61...
  • Page 36 ZYNQ Pin ZYNQ Pin J32 Pin Signal Name J32 Pin Signal Name Number Number PS_MIO5 PS_MIO17 PS_MIO4 PS_MIO18 PS_MIO14 PS_MIO19 PS_MIO15 PS_MIO20 PS_MIO52 PS_MIO16 PS_MIO53 PS_MIO21 PS_MIO7 PS_MIO26 PS_MIO25 PS_MIO40 PS_MIO24 PS_MIO41 PS_MIO23 PS_MIO42 PS_MIO27 Amazon Store: https://www.amazon.com/alinx 36 / 61...
  • Page 37 PS_MIO38 B12_L5_N AA28 PS_MIO39 B12_L8_N AE30 B12_L21_P AJ28 B12_L8_P AD30 B12_L21_N AJ29 B12_L15_N AG29 B12_L7_N AD26 B12_L15_P AF29 B12_L7_P AC26 B11_L23_N AA23 B11_L11_P AD23 B11_L23_P AA22 B11_L11_N AE23 B11_L21_N B11_L9_P AF23 B11_L21_P B11_L9_N AF24 Amazon Store: https://www.amazon.com/alinx 37 / 61...
  • Page 38 ZYNQ FPGA Development Board AX7Z100 User Manual B11_L22_N AB24 B11_L10_N AE21 B11_L22_P AA24 B11_L10_P AD21 B11_L7_P AC24 B11_L24_P AC22 B11_L7_N AD24 B11_L24_N AC23 Amazon Store: https://www.amazon.com/alinx 38 / 61...

  • Page 39: Part 3: Carrier Board

    USB port of the upper PC with a USB cable for separate power supply and serial data communication of the core board. The schematic diagram of the USB Uart circuit design is shown in Figure 3-2-1: Amazon Store: https://www.amazon.com/alinx 39 / 61...

  • Page 40: Part 3.3: Gigabit Ethernet Interface

    PS system end, and the other one is connected to the logical IO port of the PL. The Gigabit Ethernet interface connected to the PL side needs to be mounted to the ZXIQ AXI bus system by calling the IP. Amazon Store: https://www.amazon.com/alinx 40 / 61...
  • Page 41 25Mhz. Data is sampled on the rising edge and falling samples of the clock. Figure 3-3-1 detailed the connection of the ZYNQ PS end 1 way Ethernet PHY chip, and Figure 3-3-2 detailed the connection of the 1 Amazon Store: https://www.amazon.com/alinx 41 / 61...
  • Page 42 Figure 3-3-1: The connection of the ZYNQ PS end and GPHY chip PHY2_TXCK PHY2_TXCTL PHY2_TXD0~PHY2_TXD3 PHY2_RXCK ZYNQ GPHY BANK PHY2_RXCTL (KSZ9031RNX) PHY2_TXD0~PHY2_RXD3 PHY2_MDC PHY2_MDIO PHY2_RESET Figure 3-3-2: The connection of the ZYNQ PL end and GPHY chip Amazon Store: https://www.amazon.com/alinx 42 / 61...
  • Page 43 Transmit data bit3 PHY2_TXD3 B35_L3_P Transmit enable signal PHY2_TXCTL B35_L5_N RGMII Receive Clock PHY2_RXCK B35_L11_P Receive data Bit0 PHY2_RXD0 B35_L12_P Receive data Bit1 PHY2_RXD1 B35_L12_N Receive data Bit2 PHY2_RXD2 B35_L10_N Receive data Bit3 PHY2_RXD3 B35_L10_P Amazon Store: https://www.amazon.com/alinx 43 / 61...

  • Page 44: Part 3.4: Usb2.0 Host Interface

    The schematic diagram of the ZYNQ processor, USB3320C-EZK chip, USB2514 chip connection are shown as Figure 3-4-1 OTG_CLK OTG_STP BANK OTG_NXT ZYNQ USB PHY USB Hub OTG_DIR DP/DM (USB3320C) (USB2514) OTG_DATA0~OTG_DATA7 OTG_RESET BANK Figure 3-4-1: The connection between Zynq7000 and USB chip Amazon Store: https://www.amazon.com/alinx 44 / 61...

  • Page 45: Part 3.5: Hdmi Output Interface

    I2C configuration interface are connected with the BANK35 IO of the ZYNQ7000 PL part. The ZYNQ7000 system initializes and controls the ADV7511 through the I2C pin. The hardware connection diagram of ADV7511 chip and ZYNQ7000 is shown in Figure 3-5-1. Amazon Store: https://www.amazon.com/alinx 45 / 61...
  • Page 46 HDMI Video signal data1 HDMI_D1 B35_L22_N HDMI Video signal data2 HDMI_D2 B35_L22_P HDMI Video signal data3 HDMI_D3 B35_L20_N HDMI Video signal data4 HDMI_D4 B35_L20_P HDMI Video signal data5 HDMI_D5 B35_L19_N HDMI Video signal data6 HDMI_D6 B35_L19_P Amazon Store: https://www.amazon.com/alinx 46 / 61...

  • Page 47: Part 3.6: Hdmi Input Interface

    HDMI_SCL B35_L13_N HDMI IIC Control data HDMI _SDA B35_L13_P Part 3.6: HDMI Input Interface The HDMI input interface uses Silion Image's SIL9011/SIL9013 HDMI decoder chip, which supports up to 1080P@60Hz input and supports data Amazon Store: https://www.amazon.com/alinx 47 / 61...
  • Page 48 AF23 9013 video signal is valid 0 9013_D[1] B11_L11_N AE23 9013 video signal is valid 1 9013_D[2] B11_L7_N AD24 9013 video signal is valid 2 9013_D[3] B11_L7_P AC24 9013 video signal is valid 3 Amazon Store: https://www.amazon.com/alinx 48 / 61...

  • Page 49: Part 3.7: Sfp Interface

    GNK transceiver of the BANK110 of ZYNQ. The TX signal and the RX signal are connected to the ZYNQ and the optical module through the DC blocking capacitor in differential signal mode. The TX and RX data rates are up to each Amazon Store: https://www.amazon.com/alinx 49 / 61...
  • Page 50 Optical module 2 receive data negative SFP3_TX_P BANK110_TX1_P Optical module 3 transmit data positive SFP3_TX_N BANK110_TX1_N Optical module 3 transmit data negative SFP3_RX_P BANK110_RX1_P Optical module 3 receive data positive SFP3_RX_N BANK110_RX1_N Optical module 3 receive data negative Amazon Store: https://www.amazon.com/alinx 50 / 61...

  • Page 51: Part 3.8: Pcie Slot

    The single channel communication rate can be up to 5G bit bandwidth. The PCIe interface design diagram of the FPGA development board is shown in Figure 3-8-1, where the TX transmission signal is connected in AC coupling mode. Amazon Store: https://www.amazon.com/alinx 51 / 61...
  • Page 52 PCIE_TX3_N BANK112_TX0_N PCIE Channel 4 Data Transmit Positive PCIE_TX4_P BANK111_TX3_P PCIE Channel 4 Data Transmit Negative PCIE_TX4_N BANK111_TX3_N PCIE Channel 5 Data Transmit Positive PCIE_TX5_P BANK111_TX2_P PCIE Channel 5 Data Transmit Negative PCIE_TX5_N BANK111_TX2_N Amazon Store: https://www.amazon.com/alinx 52 / 61...

  • Page 53: Part 3.9: Sd Card Slot

    SD card is 3.3V, connected through the TXS02612 level shifter. The schematic of the Zynq7000 PS and SD card connector is shown in Figure 3-9-1: Figure 3-9-1: SD Card Connection Diagram Amazon Store: https://www.amazon.com/alinx 53 / 61...

  • Page 54: Part 3.10: Expansion Header

    Part 3.10: Expansion Header The carrier board is reserved with one 2.54-mm standard 40-pin expansion ports J33, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 55 AF13 IO1_6P IO1_7N AH13 AH14 IO1_7P IO1_8N AJ13 AJ14 IO1_8P IO1_9N AK12 AK13 IO1_9P IO1_10N AB14 AB15 IO1_10P IO1_11N AF15 AG15 IO1_11P IO1_12N AG14 AF14 IO1_12P IO1_13N AD15 AD16 IO1_13P IO1_14N AC16 AC17 IO1_14P Amazon Store: https://www.amazon.com/alinx 55 / 61...

  • Page 56: Part 3-11: Led Light

    LED light: Figure 3-11-1: The User LEDs Hardware Connection Diagram Pin assignment of user LED lights Signal Name ZYNQ Pin Name ZYNQ Pin Number Description PL User LED1 PL_LED1 B10_L4_P AJ16 Amazon Store: https://www.amazon.com/alinx 56 / 61...

  • Page 57: Part 3-12: Reset Button And User Button

    ZYNQ Pin Name ZYNQ Pin Number Description PL button 1 input PL_KEY1 B10_L15_P AF18 PL button 2 input PL_KEY2 B10_L15_N AF17 PL button 3 input PL_KEY3 B10_L6_P AH17 PL button 4 input PL_KEY4 B10_L6_N AH16 Amazon Store: https://www.amazon.com/alinx 57 / 61...

  • Page 58: Part 3-13: Jtag Debug Port

    MIO4) to determine which startup mode. The user can select different startup modes through the DIP switch SW1 on the board. The SW1 startup mode configuration is shown in Table 3-14-1. Switch Position （1， 2） MIO5,MIO4 Level Start Mode JTAG ON、ON 0、0 Amazon Store: https://www.amazon.com/alinx 58 / 61...

  • Page 59: Part 3-15: Power Supply

    The schematic diagram of the power supply design on the AX7Z100 FPGA development board is shown in Figure 3-15-1 Figure 3-15-1: Power interface section in the schematic The functions of each power distribution are shown in the following table: Power Supply Function Amazon Store: https://www.amazon.com/alinx 59 / 61...

  • Page 60: Part 3.16: Fan

    The fan has been screwed to the AX7Z100 FPGA development board before leaving the factory. The power of the fan is connected to the socket of J25. The red is positive and the black is negative. Part 3.17: Dimensional structure Amazon Store: https://www.amazon.com/alinx 60 / 61...
  • Page 61 ZYNQ FPGA Development Board AX7Z100 User Manual Figure 3-17-1: Top View Amazon Store: https://www.amazon.com/alinx 61 / 61...

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