Alinx ZYNQ UltraScale+ AXU2CG-E User Manual
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Alinx ZYNQ UltraScale+ AXU2CG-E User Manual

Fpga development board
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ZYNQ UltraScale+
FPGA Development Board
AXU2CG-E
User Manual

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Summary of Contents for Alinx ZYNQ UltraScale+ AXU2CG-E

  • Page 1 ZYNQ UltraScale+ FPGA Development Board AXU2CG-E User Manual...

  • Page 2: Version Record

    ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual Version Record Version Date Release By Description Rev 1.0 2021-09-11 Rachel Zhou First Release www.alinx.com 2 / 56...

  • Page 3: Table Of Contents

    Part 3.8: Expansion Header ............. 44 Part 3.9: CAN communication interface ........... 46 Part 3.10: 485 communication interface ........... 47 Part 3.11: MIPI camera interface ............48 Part 3.12: JTAG Debug Port ............. 49 Part 3.13: Real-time clock ..............50 www.alinx.com 3 / 56...
  • Page 4 Part 3.15: User LEDs ............... 52 Part 3.16: Keys ................. 53 Part 3.17: DIP Switch Configuration ..........53 Part 3.18: Power Supply ..............54 Part 3.19: ALINX Customized Fan ........... 55 Part 3.20: Carrier Board Size Dimension ......... 56 www.alinx.com 4 / 56...
  • Page 5 It is a "professional" ZYNQ development platform. For high-speed data transmission and exchange, pre-verification and post-application of data processing is possible. This product is very suitable for students, engineers and other groups engaged in MPSoCs development. www.alinx.com 5 / 56...

  • Page 6: Part 1: Fpga Development Board Introduction

    Ethernet interfaces, 1 SD card slot,2-Channel 40-pin expansion header, 2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI Camera Interface and some keys and LEDs. The following figure shows the structure of the entire development system: www.alinx.com 6 / 56...
  • Page 7 SSD solid state drives, with a communication speed of up to 6Gbps.  DP Output Interface 1 standard Display Port output display interface, used for video image display. Supports up to 4K@30Hz or 1080P@60Hz output  USB 3.0 Interface www.alinx.com 7 / 56...
  • Page 8  40-pin expansion port 2 40-pin 0.1-inch pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1-channel 5V power supply, 2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
  • Page 9 There are 1 power indicator and 1 DONE Configuration indicator on the core board, 1 power indicator on the carrier board. There are 1 power indicator and 2 user indicators on the carrier board.  KEYs 3 KEYs, include 1 Rest KEY and 2 User KEYs. www.alinx.com 9 / 56...

  • Page 10: Part 2: Acu2Eg Core Board

    PL side (HP I/O: 96, HD I/O: 84). The wiring between the XCZU2CG chip and the interface has been processed with equal length and differential, and the core board size is only 3.15*2.36 (inch), which is very suitable for secondary development. www.alinx.com 10 / 56...

  • Page 11: Part 2.2: Zynq Chip

    LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. www.alinx.com 11 / 56...
  • Page 12 2 CPUs  ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU 32KB level 1 instruction and data cache, and 128K tightly coupled memory.  External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3 interface www.alinx.com 12 / 56...

  • Page 13: Part 2.3: Ddr4 Dram

    DDR4 chips, model is PANGO CXDQ2BFAM-CG (Compatible with MT40A256M16GE-083E), to form a 64-bit data bus bandwidth and 2GB capacity. The maximum operating speed of the DDR4 SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems www.alinx.com 13 / 56...
  • Page 14 PCB design to ensure high-speed and stable operation of DDR4. The hardware connection of DDR4 SDRAM on the PS Side is shown in Figure 2-3-1: Figure 2-3-1: DDR4 DRAM schematic diagram on the PS Side www.alinx.com 14 / 56...
  • Page 15 PS_DDR4_DQ4 PS_DDR_DQ4_504 AH21 PS_DDR4_DQ5 PS_DDR_DQ5_504 AH20 PS_DDR4_DQ6 PS_DDR_DQ6_504 AH19 PS_DDR4_DQ7 PS_DDR_DQ7_504 AG19 PS_DDR4_DQ8 PS_DDR_DQ8_504 AF22 PS_DDR4_DQ9 PS_DDR_DQ9_504 AH22 PS_DDR4_DQ10 PS_DDR_DQ10_504 AE22 PS_DDR4_DQ11 PS_DDR_DQ11_504 AD22 PS_DDR4_DQ12 PS_DDR_DQ12_504 AH23 PS_DDR4_DQ13 PS_DDR_DQ13_504 AH24 PS_DDR4_DQ14 PS_DDR_DQ14_504 AE24 PS_DDR4_DQ15 PS_DDR_DQ15_504 AG24 www.alinx.com 15 / 56...
  • Page 16 PS_DDR4_DQ33 PS_DDR_DQ33_504 PS_DDR4_DQ34 PS_DDR_DQ34_504 PS_DDR4_DQ35 PS_DDR_DQ35_504 PS_DDR4_DQ36 PS_DDR_DQ36_504 PS_DDR4_DQ37 PS_DDR_DQ37_504 PS_DDR4_DQ38 PS_DDR_DQ38_504 PS_DDR4_DQ39 PS_DDR_DQ39_504 PS_DDR4_DQ40 PS_DDR_DQ40_504 PS_DDR4_DQ41 PS_DDR_DQ41_504 PS_DDR4_DQ42 PS_DDR_DQ42_504 PS_DDR4_DQ43 PS_DDR_DQ43_504 PS_DDR4_DQ44 PS_DDR_DQ44_504 PS_DDR4_DQ45 PS_DDR_DQ45_504 PS_DDR4_DQ46 PS_DDR_DQ46_504 PS_DDR4_DQ47 PS_DDR_DQ47_504 PS_DDR4_DQ48 PS_DDR_DQ48_504 PS_DDR4_DQ49 PS_DDR_DQ49_504 PS_DDR4_DQ50 PS_DDR_DQ50_504 www.alinx.com 16 / 56...
  • Page 17 PS_DDR4_A1 PS_DDR_A1_504 PS_DDR4_A2 PS_DDR_A2_504 AB28 PS_DDR4_A3 PS_DDR_A3_504 AA28 PS_DDR4_A4 PS_DDR_A4_504 PS_DDR4_A5 PS_DDR_A5_504 AA27 PS_DDR4_A6 PS_DDR_A6_504 PS_DDR4_A7 PS_DDR_A7_504 AA23 PS_DDR4_A8 PS_DDR_A8_504 AA22 PS_DDR4_A9 PS_DDR_A9_504 AB23 PS_DDR4_A10 PS_DDR_A10_504 AA25 PS_DDR4_A11 PS_DDR_A11_504 AA26 PS_DDR4_A12 PS_DDR_A12_504 AB25 PS_DDR4_A13 PS_DDR_A13_504 AB26 www.alinx.com 17 / 56...

  • Page 18: Part 2.4: Qspi Flash

    QSPI FLASH is connected to the GPIO port of the BANK500 in the PS section of the ZYNQ chip. In the system design, the GPIO port functions of these PS ports need to be configured as the QSPI FLASH interface. Figure www.alinx.com 18 / 56...

  • Page 19: Part 2.5: Emmc Flash

    FLASH, it can be used as a large-capacity storage device in the ZYNQ system, such as storing ARM applications, system files and other user data files The specific models and related parameters of eMMC FLASH are shown in Table 2-5-1. www.alinx.com 19 / 56...
  • Page 20 Configuration Chip pin assignment: Signal Name Pin Name Pin Number MMC_DAT0 PS_MIO13_500 AH18 MMC_DAT1 PS_MIO14_500 AG18 MMC_DAT2 PS_MIO15_500 AE18 MMC_DAT3 PS_MIO16_500 AF18 MMC_DAT4 PS_MIO17_500 AC18 MMC_DAT5 PS_MIO18_500 AC19 MMC_DAT6 PS_MIO19_500 AE19 MMC_DAT7 PS_MIO20_500 AD19 MMC_CMD PS_MIO21_500 AC21 www.alinx.com 20 / 56...

  • Page 21: Part 2.6: Clock Configuration

    PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2: Figure 2-6-2: Passive Crystal Oscillator for RTC www.alinx.com 21 / 56...
  • Page 22 (MRCC) of PL BANK64. This global clock can be used to drive the DDR4 controller and user logic circuits in the FPGA. The schematic diagram of this clock source is shown in Figure 2-6-4 www.alinx.com 22 / 56...

  • Page 23: Part 2.7: Led

    FPGA configuration program, the configuration LED light will light up. The LED Schematic in the Core Board is shown in Figure 2-7-1: Figure 2-7-1: LED Schematic in the Core Board www.alinx.com 23 / 56...

  • Page 24: Part 2.8: Power Supply

    The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU2CG chip. For the TPS6508641 power supply design, please refer to the power supply chip manual. The design block diagram is as follows: www.alinx.com 24 / 56...

  • Page 25: Part 2.9: Acu2Eg Core Board Form Factor

    The core board has a total of four high-speed expansion ports. It uses four 120-pin inter-board connectors (J29/J30/J31/J32) to connect to the carrier board. The connectors used is Panasonic AXK5A2137YG, and the corresponding connector model in the carrier board is Panasonic AXK6A2337YG. Among www.alinx.com 25 / 56...
  • Page 26 Signal Name Pin Number J29 Pin Signal Name Pin Number B65_L2_N B65_L22_P B65_L2_P B65_L22_N B65_L4_N B65_L20_P B65_L4_P B65_L20_N B65_L1_N B65_L6_N B65_L1_P B65_L6_P B65_L7_P B65_L17_P B65_L7_N B65_L17_N B65_L15_P B65_L9_P B65_L15_N B65_L9_N B65_L16_P B65_L3_N B65_L16_N B65_L3_P B65_L14_P B65_L19_P www.alinx.com 26 / 56...
  • Page 27 B65_L11_N B65_L8_P B65_L11_P B65_L8_N B65_L10_N B65_L24_N B65_L10_P B65_L24_P B66_L3_P B65_L12_P B66_L3_N B65_L12_N B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N B65_L23_N B66_L15_P B66_L5_N B66_L15_N B66_L5_P B66_L4_P B66_L2_P B66_L4_N B66_L2_N B66_L11_P B66_L20_P B66_L11_N B66_L20_N www.alinx.com 27 / 56...
  • Page 28 Signal Name Pin Number J30 Pin Signal Name Pin Number B66_L14_P FPGA_TDI B66_L14_N FPGA_TCK B66_L22_P FPGA_TDO B66_L22_N FPGA_TMS B66_L19_N B66_L21_N B66_L19_P B66_L21_P B66_L24_P B66_L17_P B66_L24_N B66_L17_N B66_L23_N B25_L9_P B66_L23_P B25_L9_N B25_L5_N B25_L10_P B25_L5_P B25_L10_N B66_L18_N B25_L12_P www.alinx.com 28 / 56...
  • Page 29 B26_L11_P B25_L6_N B26_L11_N B25_L6_P B26_L10_N B26_L6_N B26_L10_P B26_L6_P B26_L7_N B26_L3_N B26_L7_P B26_L3_P B26_L9_N B26_L2_N B26_L9_P B26_L2_P B26_L5_N B26_L4_N B26_L5_P B26_L4_P B26_L1_P B26_L12_P B26_L1_N B26_L12_N 505_CLK2_P 505_CLK1_P 505_CLK2_N 505_CLK1_N 505_CLK0_P 505_CLK3_P 505_CLK0_N 505_CLK3_N 505_TX3_P 505_TX1_P 505_TX3_N 505_TX1_N www.alinx.com 29 / 56...
  • Page 30 B44_L6_P AC12 B24_L6_N AC13 B44_L6_N AD12 B24_L5_P AD15 B44_L7_P AD11 B24_L5_N AD14 B44_L7_N AD10 B24_L1_P AE15 B44_L8_N AC11 B24_L1_N AE14 B44_L8_P AB11 B24_L12_P B24_L2_P AG14 B24_L12_N AA12 B24_L2_N AH14 B24_L3_P AG13 B24_L3_N AH13 B44_L12_N B44_L9_P AA11 www.alinx.com 30 / 56...
  • Page 31 B44_L1_P AG10 B24_L9_N B24_L4_P AE13 B24_L9_P B24_L4_N AF13 B24_L8_P AB15 B44_L5_P AE12 B24_L8_N AB14 B44_L5_N AF12 B44_L2_N AG11 B44_L4_N AF10 B44_L2_P AF11 B44_L4_P AE10 VBAT_IN B44_L11_P B44_L11_N PS_POR_B 224_CLK0_P 224_CLK1_P 224_CLK0_N 224_CLK1_N 224_RX3_P 224_TX3_P 224_RX3_N 224_TX3_N www.alinx.com 31 / 56...
  • Page 32 Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number PS_MIO35 PS_MIO30 PS_MIO29 PS_MIO31 PS_MIO58 PS_MIO53 PS_MODE0 PS_MIO52 PS_MODE1 PS_MIO55 PS_MODE2 PS_MIO56 PS_MODE3 PS_MIO57 PS_MIO36 PS_MIO54 PS_MIO37 PS_MIO27 PS_MIO28 PS_MIO77 PS_MIO59 PS_MIO76 PS_MIO60 www.alinx.com 32 / 56...
  • Page 33 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64 PS_MIO48 PS_MIO69 PS_MIO41 PS_MIO74 PS_MIO32 PS_MIO73 PS_MIO46 PS_MIO72 PS_MIO50 PS_MIO71 PS_MIO49 PS_MIO75 PS_MIO34 PS_MIO70 PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33 VCCO_65 VCCO_66 VCCO_65 VCCO_66 www.alinx.com 33 / 56...
  • Page 34 ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V www.alinx.com 34 / 56...

  • Page 35: Part 3: Carrier Board

     2-Channel 10/100M/1000M Ethernet RJ-45 interface  2-Channel USB Uart Interfaces  1-Channel Micro SD card slot  1-Channel MIPI camera interface  2-Channel 40-pin expansion port  2-Channel CAN communication interfaces  2-Channel 485 communication interfaces www.alinx.com 35 / 56...

  • Page 36: Part 3.2: M.2 Interface

    Si5332 chip, the frequency is 100Mhz, and the schematic diagram of the M.2 circuit design is shown in Figure 3-2-1: PCIE_TX_P PCIE_TX_C_P PCIE_TX_N PCIE_TX_C_N ZYNQ BANK PCIE_RX_P Ultra PCIE_RX_N Scale+ 505_PCIE_REFCLK_P PCIE_REFCLK_P Si5332 PCIE_REFCLK_N 505_PCIE_REFCLK_N PCIE_RSTn_MIO37 M2_PCIE_RST_N 电平转换 Figure 3-2-1: M.2 Interface Schematic www.alinx.com 36 / 56...

  • Page 37: Part 3.3: Dp Interface

    MGT are connected to the DP connector in a differential signal mode. The DisplayPort auxiliary channel is connected to the MIO pin of the PS. The schematic diagram of the DP output interface design is shown in Figure 3-3-1: www.alinx.com 37 / 56...
  • Page 38 DP Reference Clock 505_CLK1_P 505_CLK2_P Positive DP Reference Clock 505_CLK1_N 505_CLK2_N Negative DP_AUX_OUT PS_MIO27 DP Auxiliary Data Output DP_AUX_IN PS_MIO30 DP Auxiliary Data Input DP_OE PS_MIO29 DP Auxiliary Data Output Enable DP_HPD PS_MIO28 DP Insertion Signal Detection www.alinx.com 38 / 56...

  • Page 39: Part 3.4: Usb3.0 Interface

    Signal Name Pin Name Pin Number Description USB_SSTXP 505_TX1_P USB3.0 Data Transmit Positive USB_SSTXN 505_TX1_N USB3.0 Data Transmit Negative USB_SSRXP 505_RX1_P USB3.0 Data Receive Positive USB_SSRXN 505_RX1_N USB3.0 Data Receive Negative USB_DATA0 PS_MIO56 USB2.0 Data Bit0 www.alinx.com 39 / 56...

  • Page 40: Part 3.5: Gigabit Ethernet Interface

    CLK125_EN Enable 125Mhz clock output selection Enable LED_MODE LED light mode configuration Single LED light mode 10/100/1000 adaptive, compatible Link adaptation and full duplex MODE0~MODE3 with full-duplex, half-duplex configuration Table 3-5-1: PHY chip default configuration value www.alinx.com 40 / 56...
  • Page 41 Ethernet 1 Transmit data bit0 PHY1_TXD1 PS_MIO66 Ethernet 1 Transmit data bit1 PHY1_TXD2 PS_MIO67 Ethernet 1 Transmit data bit2 PHY1_TXD3 PS_MIO68 Ethernet 1 Transmit data bit3 PHY1_TXCTL PS_MIO69 Ethernet 1 Transmit Enable Signal PHY1_RXCK PS_MIO70 Ethernet 1 RGMII Receive Clock www.alinx.com 41 / 56...

  • Page 42: Part 3.6: Usb To Serial Port

    PC's USB port for serial data communication. The schematic diagram of the USB Uart circuit design is shown in the figure below: The schematic diagram of the USB Uart circuit design is shown in Figure 3-6-1: www.alinx.com 42 / 56...

  • Page 43: Part 3.7: Sd Card Slot Interface

    ZU3EG. Since the VCCMIO of the BANK is set to 1.8V, but the data level of the SD card is 3.3V, connected through the TXS02612 level shifter. The schematic of the Zynq7000 PS and SD card connector is shown in Figure 3-10-1: www.alinx.com 43 / 56...

  • Page 44: Part 3.8: Expansion Header

    Part 3.8: Expansion Header The AXU3EG board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J45 and J46, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 45 Signal Name Pin Number B43_L2_N AG11 B43_L2_P AF11 B44_L8_N AB14 B44_L8_P AB15 B44_L9_N B44_L9_P B44_L11_N B44_L11_P B43_L10_N B43_L10_P B43_L12_N B43_L12_P AB10 B44_L3_N AH13 B44_L3_P AG13 B44_L12_N AA12 B44_L12_P B44_L1_N AE14 B44_L1_P AE15 B44_L5_N AD14 B44_L5_P AD15 www.alinx.com 45 / 56...

  • Page 46: Part 3.9: Can Communication Interface

    The connection of the CAN transceiver chip on the PS side is show as Figure 3-9-1 PS_CAN1_RX CANH SN65HVD232 PS_CAN1_TX CANL ZYNQ BANK Ultra Scale+ PS_CAN2_RX CANH SN65HVD232 PS_CAN2_TX CANL Figure 3-9-1: Connection diagram of CAN transceiver chip on PS side www.alinx.com 46 / 56...

  • Page 47: Part 3.10: 485 Communication Interface

    Scale+ PL_485_RXD2 PL_485_TXD2 MAX3485 PL_485_DE2 Figure 3-3-1: 485 Communication on the PL Side The 485 communication pins are assigned as follows: Signal Name Pin Name Pin Number Description PL_485_TXD1 B43_L1_N AH10 The 1 Channel 485 Transceiver www.alinx.com 47 / 56...

  • Page 48: Part 3.11: Mipi Camera Interface

    Part 3.11: MIPI camera interface The AXU3EG carrier board includes a MIPI camera interface, which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641. MIPI interface 15PIN FPC connector, 2 LANE data and 1 pair of clock, connected to the differential IO pin of BANK65, the level standard is 1.2V;...

  • Page 49: Part 3.12: Jtag Debug Port

    ZYNQ UltraScale+ chip by plugging and unplugging under power, we aded a protection diode to the JTAG signal to ensure that the signal voltage is within the range accepted by the FPGA and avoid damage to the ZYNQ UltraScale+ chip. www.alinx.com 49 / 56...

  • Page 50: Part 3.13: Real-Time Clock

    5V) to supply power to the clock chip. The BT1 on the development board is a battery Socket. After we put the coin battery, even the system is off, the coin battery can also power the RTC system and provide continuous time information. www.alinx.com 50 / 56...

  • Page 51: Part 3.14: Eeprom And Temperature Sensor

    ZYNQ UltraScale+ through the I2C bus. Figure 3-14-1 is the schematic diagram of EEPROM and temperature sensor LM75 ZYNQ BANK Ultra PS_IIC1_SCL 电平转 PS_IIC_B_SCL EEPROM PS_IIC1_SDA 换 PS_IIC_B_SDA Scale+ Figure 3-14-1: EEPROM and Sensor connection diagram www.alinx.com 51 / 56...

  • Page 52: Part 3.15: User Leds

    Figure 3-15-1: The User LEDs Hardware Connection Diagram Pin assignment of user LED lights Signal Name ZYNQ Pin Name ZYNQ Pin Number Description PS_LED1 PS_MIO40 User LED controlled by PS PL_LED1 B43_L5_P AE12 User LED controlled by PL www.alinx.com 52 / 56...

  • Page 53: Part 3.16: Keys

    There is a 4-digit DIP switch SW1 on the FPGA development board to configure the startup mode of the ZYNQ system. The AXU3EG system development platform supports 4 startup modes. The 4 startup modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After www.alinx.com 53 / 56...

  • Page 54: Part 3.18: Power Supply

    MP1482. In addition, the Carrier board generates +1.2V through LDO to supply power to the core board BANK65, and the power supply of BANK66 is +1.8V. The schematic diagram of the power supply design on the board is shown in Figure 3-18-1: www.alinx.com 54 / 56...

  • Page 55: Part 3.19: Alinx Customized Fan

    Ethernet, USB2.0, SD, DP, CAN, RS485 +1.2V BANK65 of Core Board Part 3.19: ALINX Customized Fan Because AXU3EG generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating.

  • Page 56: Part 3.20: Carrier Board Size Dimension

    The fan has been screwed to the AXUEG FPGA development board before leaving the factory. The power of the fan is connected to the socket of J24. The red is positive and the black is negative. Part 3.20: Carrier Board Size Dimension Figure 3-20-1: Top View www.alinx.com 56 / 56...

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