Table of Contents
Advertisement
69
B67_L23_P
71
73
B67_L7_N
75
B67_L7_P
77
B67_L9_P
79
B67_L9_N
81
83
B67_L18_P
85
B67_L18_N
87
B67_L10_P
89
B67_L10_N
91
93
228_RX1_N
95
228_RX1_P
97
99
228_TX1_N
101
228_TX1_P
103
105
228_RX3_N
107
228_RX3_P
109
111
228_TX3_N
113
228_TX3_P
115
117
228_CLK0_N
119
228_CLK0_P
Pin assignment of board to board connector J30
J30 is connected to the transceiver signal of BANK505 MGT, MIO of PS,
VCCO_66, VCCO_67 and +12V power supply.
standard
J29 Pin
Signal Name
1
505_TX0_P
3
505_TX0_N
32 / 66
ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
L13
GND
-
V7
V8
U9
U8
GND
-
L12
K12
T7
T6
GND
-
P1
P2
GND
-
P5
P6
GND
-
L3
L4
GND
-
M5
M6
GND
-
L7
L8
Pin
Number
AB29
AB30
Amazon Store: https://www.amazon.com/alinx
70
B67_L17_N
72
GND
74
B67_L13_P
76
B67_L13_N
78
B66_L23_N
80
B66_L23_P
82
GND
84
B67_L12_P
86
B67_L12_N
88
B67_L14_P
90
B67_L14_N
92
GND
94
228_RX0_N
96
228_RX0_P
98
GND
100
228_TX0_N
102
228_TX0_P
104
GND
106
228_RX2_N
108
228_RX2_P
110
GND
112
228_TX2_N
114
228_TX2_P
116
GND
118
228_CLK1_N
120
228_CLK1_P
The MIO level of PS is 1.8V
J29 Pin
Signal Name
2
505_CLK0_P
4
505_CLK0_N
L11
-
P11
N11
V1
V2
-
T8
R8
P10
P9
-
T1
T2
-
R3
R4
-
M1
M2
D1
N3
N4
-
J7
J8
Pin
Number
AA27
AA28
Advertisement
Table of Contents
Need help?
Do you have a question about the ZYNQ UltraScale+ and is the answer not in the manual?
Questions and answers