Part 3.5: Gigabit Ethernet Interface - Alinx ZYNQ UltraScale+ User Manual

USB Interface Pin Assignment:
Signal Name
USB_SSTXP
USB_SSTXN
USB_SSRXP
USB_SSRXN
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
USB_STP
USB_DIR
USB_CLK
USB_NXT
USB_RESET_N

Part 3.5: Gigabit Ethernet Interface

There are 2 Gigabit Ethernet ports on the AXU15EG carrier board, one is
connected to the PS end, and the other is connected to the PL end. The GPHY
chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide users with
network communication
10/100/1000 Mbps network transmission rate, and communicates with the
MAC layer of the ZU4EV system through the RGMII interface. KSZ9031RNX
supports MDI/MDX adaptation, various speed adaptation, Master/Slave
adaptation, and MDIO bus for PHY register management.
When the KSZ9031RNX is powered on, it will detect the level status of
some specific IOs to determine its own operating mode. Table 3-5-1 describes
the default settings after the GPHY chip is powered on.
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
Pin Name Pin Number
505_TX1_P
505_TX1_N
505_RX1_P
505_RX1_N
PS_MIO56
PS_MIO57
PS_MIO54
PS_MIO59
PS_MIO60
PS_MIO61
PS_MIO62
PS_MIO63
PS_MIO58
PS_MIO53
PS_MIO52
PS_MIO55
PS_MIO32
services.
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Y29 USB3.0 Data Transmit Positive
Y30 USB3.0 Data Transmit Negative
AA31 USB3.0 Data Receive Positive
AA32 USB3.0 Data Receive Negative
C23 USB2.0 Data Bit0
A23 USB2.0 Data Bit1
F23 USB2.0 Data Bit2
B24 USB2.0 Data Bit3
E24 USB2.0 Data Bit4
C24 USB2.0 Data Bit5
G24 USB2.0 Data Bit6
D24 USB2.0 Data Bit7
G23 USB2.0 Stop Signal
E23 USB2.0 Data Direction Signal
F22 USB2.0 Clock Signal
B23 USB2.0 Next Data Signal
H22 USB2.0 Reset Signal
The KSZ9031RNX
Description
chip supports