Table of Contents
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PS_DDR4_A2
PS_DDR4_A3
PS_DDR4_A4
PS_DDR4_A5
PS_DDR4_A6
PS_DDR4_A7
PS_DDR4_A8
PS_DDR4_A9
PS_DDR4_A10
PS_DDR4_A11
PS_DDR4_A12
PS_DDR4_A13
PS_DDR4_WE_B
PS_DDR4_CAS_B
PS_DDR4_RAS_B
PS_DDR4_ACT_B
PS_DDR4_ALERT_B
PS_DDR4_BA0
PS_DDR4_BA1
PS_DDR4_BG0
PS_DDR4_CS0_B
PS_DDR4_ODT0
PS_DDR4_PARITY
PS_DDR4_RESET_B
PS_DDR4_CLK0_P
PS_DDR4_CLK0_N
PS_DDR4_CKE0
PL Side DDR4 DRAM pin assignment:
Signal Name
PL_DDR4_DQS0_N
PL_DDR4_DQS0_P
PL_DDR4_DQS1_N
PL_DDR4_DQS1_P
PL_DDR4_DQS2_N
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
PS_DDR_A2_504
PS_DDR_A3_504
PS_DDR_A4_504
PS_DDR_A5_504
PS_DDR_A6_504
PS_DDR_A7_504
PS_DDR_A8_504
PS_DDR_A9_504
PS_DDR_A10_504
PS_DDR_A11_504
PS_DDR_A12_504
PS_DDR_A13_504
PS_DDR_A14_504
PS_DDR_A15_504
PS_DDR_A16_504
PS_DDR_ACT_N_504
PS_DDR_ALERT_N_504
PS_DDR_BA0_504
PS_DDR_BA1_504
PS_DDR_BG0_504
PS_DDR_CS_N0_504
PS_DDR_ODT0_504
PS_DDR_PARITY_504
PS_DDR_RST_N_504
PS_DDR_CK0_504
PS_DDR_CK_N0_504
PS_DDR_CKE0_504
IO_L22N_T3U_N7_DBC_AD0N_65
IO_L22P_T3U_N6_DBC_AD0P_65
IO_L16N_T2U_N7_QBC_AD3N_65
IO_L16P_T2U_N6_QBC_AD3P_65
IO_L10N_T1U_N7_QBC_AD4N_65
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Pin Name
AP26
AP27
AP25
AN24
AM29
AM28
AM26
AM25
AL28
AK27
AJ25
AL25
AK25
AK24
AM24
AG25
AF22
AH26
AG26
AK28
AN28
AM30
AF20
AF21
AN26
AN27
AN29
Pin Number
AF1
AJ1
AH1
AJ5
AJ6
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