Alinx ZYNQ UltraScale+ User Manual page 45

PS Gigabit Ethernet pin assignment is as follows
Signal Name
PHY1_TXCK
PHY1_TXD0
PHY1_TXD1
PHY1_TXD2
PHY1_TXD3
PHY1_TXCTL
PHY1_RXCK
PHY1_RXD0
PHY1_RXD1
PHY1_RXD2
PHY1_RXD3
PHY1_RXCTL
PHY1_MDC
PHY1_MDIO
PL Gigabit Ethernet pin assignment is as follows
Signal Name
PHY2_TXCK
PHY2_TXD0
PHY2_TXD2
PHY2_TXD1
PHY2_TXD3
PHY2_TXCTL
PHY2_RXCK
PHY2_RXD0
PHY2_RXD1
PHY2_RXD2
PHY2_RXD3
PHY2_RXCTL
PHY2_MDC
PHY2_MDIO
PHY2_RESET
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
Pin Name
PS_MIO64
PS_MIO65
PS_MIO66
PS_MIO67
PS_MIO68
PS_MIO69
PS_MIO70
PS_MIO71
PS_MIO72
PS_MIO73
PS_MIO74
PS_MIO75
PS_MIO76
PS_MIO77
Pin Name
B66_L17_N
B66_L4_N
B66_L10_N
B66_L4_P
B66_L10_P
B66_L17_P
B66_L12_P
B66_L18_N
B66_L18_P
B66_L6_N
B66_L6_P
B66_L12_N
B67_L15_P
B67_L15_N
B67_L11_N
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Pin Number
A25 Ethernet 1 RGMII Transmit Clock
A26 Ethernet 1 Transmit data bit0
A27 Ethernet 1 Transmit data bit1
B25 Ethernet 1 Transmit data bit2
B26 Ethernet 1 Transmit data bit3
B27 Ethernet 1 Transmit Enable Signal
C26 Ethernet 1 RGMII Receive Clock
C27 Ethernet 1 Receive Data Bit0
E25 Ethernet 1 Receive Data Bit1
H24 Ethernet 1 Receive Data Bit2
G25 Ethernet 1 Receive Data Bit3
D25 Ethernet 1 Receive Enable Signal
H25 Ethernet 1 MDIO Clock Management
F25 Ethernet 1 MDIO Management Data
Pin
Number
V3 Ethernet 2 RGMII Transmit Clock
AC9 Ethernet 2 Transmit data bit0
AB5 Ethernet 2 Transmit data bit1
AB9 Ethernet 2 Transmit data bit2
AB6 Ethernet 2 Transmit data bit3
V4 Ethernet 2 Transmit Enable Signal
AA7 Ethernet 2 RGMII Transmit Clock
U4 Ethernet 2 Receive Data Bit0
U5 Ethernet 2 Receive Data Bit1
Y9 Ethernet 2 Receive Data Bit2
Y10 Ethernet 2 Receive Data Bit3
AA6 Ethernet 2 Receive Enable Signal
M10 Ethernet 2 MDIO Clock Management
L10 Ethernet 2 MDIO Management Data
R9 Ethernet 2 Reset Signal
Description
Description