Part 2.6: Clock Configuration - Alinx ZYNQ UltraScale+ User Manual

Configuration Chip pin assignment:
Signal Name
MMC_CCLK
MMC_CMD
MMC_DAT0
MMC_DAT1
MMC_DAT2
MMC_DAT3
MMC_DAT4
MMC_DAT5
MMC_DAT6
MMC_DAT7
MMC_CCLK

Part 2.6: Clock configuration

The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
Figure 2-5-1: eMMC Flash in the schematic
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Pin Name
PS_MIO22_500
PS_MIO21_500
PS_MIO13_500
PS_MIO14_500
PS_MIO15_500
PS_MIO16_500
PS_MIO17_500
PS_MIO18_500
PS_MIO19_500
PS_MIO20_500
PS_MIO22_500
Pin Number
AD20
AF18
AK17
AL16
AN16
AM16
AP16
AE18
AL17
AD18
AD20