Alinx ZYNQ7000 FPGA User Manual
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Alinx ZYNQ7000 FPGA User Manual

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ZYNQ7000 FPGA
Development Board
AX7350
User Manual

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  • Page 1 ZYNQ7000 FPGA Development Board AX7350 User Manual...

  • Page 2: Version Record

    ZYNQ FPGA Development Board AX7350 User Manual Version Record Revision Date Release By Description Rev 1.0 2019-04-05 Rachel Zhou First Release 2 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 3: Table Of Contents

    Part 16: Reset Button and User Button ........... 46 Part17: JTAG Debug Port ................ 47 Part 18: DIP Switch Configuration ............48 Part 19: Power Supply ................49 Part 20: Fan ..................... 51 Part 21: Dimensional structure ..............53 3 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 4 ZYNQ FPGA Development Board AX7350 User Manual The ZYNQ7000 FPGA development platform uses XILINX's Zynq7000 SOC chip XC7Z035 solution, which uses ARM+FPGA SOC technology to integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip. ZYNQ has two 512MB high-speed DDR3 SDRAM chips on the PS and PL sides.

  • Page 5: Part 1: Fpga Development Board Introduction

    USB2.0 HOST interfaces, one HDMI output interface, and one UART serial interface. 1 SD card interface, 1 FMC expansion interface and some button LEDs. Figure 1-1 is the Schematic diagram of the entire FPGA development boards: 5 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 6 ZYNQ chip data, or as a memory for the operating system. The other two are attached to the PL end and can be used as data storage, image analysis cache, and data processing of the FPGA.  eMMC 6 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 7 ANALOG DEVICE, up to 1080P@60Hz output, support 3D output.  USB2.0 HOST Interface Extend the 4-channe USB HOST interface through the USB Hub chip for connecting external USB slave devices, such as connecting a 7 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 8 GTX. Provide a reference clock for PCIE, SFP and DDR operation.  LED Light 9 LEDs, 1 power indicator; 1 DONE configuration indicator; 2 serial 8 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 9: Part 2: Zynq Chip

    UART interface, GPIO etc. The PS can operate independently and start up at power up or reset. Figure 2-1 detailed the Overall Block Diagram of the ZYNQ7000 Chip. Figure 2-1: Overall Block Diagram of the ZYNQ7000 Chip 9 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 10  8-channel high-speed GTX transceiver, supporting PCIE Gen2x8;  Two AD converters for on-chip voltage, temperature sensing and up to 17 external differential input channels, 1MBPS XC7Z020-2CLG484I chip speed grade is -2, industrial grade, package is 10 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 11 FGG676, pin pitch is 1.0mm the specific chip model definition of ZYNQ7000 series is shown in Figure 2-2 Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series Figure 2-3: The XC7Z035 chip used on the Core Board 11 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 12: Part 3: Ddr3 Dram

    The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3. 12 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 13 ZYNQ FPGA Development Board AX7350 User Manual Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side 13 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 14 Figure 3-4: Two DDR3 DRAMs on the PL side. PS side DDR3 DRAM pin assignment: Signal Name ZYNQ Pin Name ZYNQ Pin Number PS_DDR3_DQS0_P PS_DDR_DQS_P0_502 PS_DDR3_DQS0_N PS_DDR_DQS_N0_502 PS_DDR3_DQS1_P PS_DDR_DQS_P1_502 PS_DDR3_DQS1_N PS_DDR_DQS_N1_502 PS_DDR3_DQS2_P PS_DDR_DQS_P2_502 PS_DDR3_DQS2_N PS_DDR_DQS_N2_502 PS_DDR3_DQS3_P PS_DDR_DQS_P3_502 PS_DDR3_DQS4_N PS_DDR_DQS_N3_502 14 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 15 PS_DDR3_D19 PS_DDR_DQ19_502 PS_DDR3_D20 PS_DDR_DQ20_502 PS_DDR3_D21 PS_DDR_DQ21_502 PS_DDR3_D22 PS_DDR_DQ22_502 PS_DDR3_D23 PS_DDR_DQ23_502 PS_DDR3_D24 PS_DDR_DQ24_502 PS_DDR3_D25 PS_DDR_DQ25_502 PS_DDR3_D26 PS_DDR_DQ26_502 PS_DDR3_D27 PS_DDR_DQ27_502 PS_DDR3_D28 PS_DDR_DQ28_502 PS_DDR3_D29 PS_DDR_DQ29_502 PS_DDR3_D30 PS_DDR_DQ30_502 PS_DDR3_D31 PS_DDR_DQ31_502 PS_DDR3_DM0 PS_DDR_DM0_502 PS_DDR3_DM1 PS_DDR_DM1_502 PS_DDR3_DM2 PS_DDR_DM2_502 PS_DDR3_DM3 PS_DDR_DM3_502 15 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 16 PS_DDR3_ODT PS_DDR_ODT_502 PS_DDR3_RESET PS_DDR_DRST_B_502 PS_DDR3_CLK0_P PS_DDR_CKP_502 PS_DDR3_CLK0_N PS_DDR_CKN_502 PS_DDR3_CKE PS_DDR_CKE_502 PL side DDR3 DRAM pin assignment: Signal Name ZYNQ Pin Name ZYNQ Pin Number PL_DDR3_DQS0_P IO_L3P_T0_DQS_33 PL_DDR3_DQS0_N IO_L3N_T0_DQS_33 PL_DDR3_DQS1_P IO_L9P_T1_DQS_33 PL_DDR3_DQS1_N IO_L9N_T1_DQS_33 PL_DDR3_DQS2_P IO_L15P_T2_DQS_33 16 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 17 PL_DDR3_D16 IO_L18P_T2_33 PL_DDR3_D17 IO_L14P_T2_SRCC_33 PL_DDR3_D18 IO_L14N_T2_SRCC_33 PL_DDR3_D19 IO_L13P_T2_MRCC_33 PL_DDR3_D20 IO_L16P_T2_33 PL_DDR3_D21 IO_L17P_T2_33 PL_DDR3_D22 IO_L16N_T2_33 PL_DDR3_D23 IO_L17N_T2_33 PL_DDR3_D24 IO_L23P_T3_33 PL_DDR3_D25 IO_L22N_T3_33 PL_DDR3_D26 IO_L19P_T3_33 PL_DDR3_D27 IO_L20N_T3_33 PL_DDR3_D28 IO_L24P_T3_33 PL_DDR3_D29 IO_L20P_T3_33 PL_DDR3_D30 IO_L24N_T3_33 PL_DDR3_D31 IO_L22P_T3_33 PL_DDR3_DM0 IO_L6P_T0_33 17 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 18: Part 4: Qspi Flash

    PL_DDR3_BA2 IO_L22N_T3_34 PL_DDR3_S0 IO_L14N_T2_SRCC_34 PL_DDR3_RAS IO_L19P_T3_34 PL_DDR3_CAS IO_L20N_T3_34 PL_DDR3_WE IO_L20P_T3_34 PL_DDR3_ODT IO_L22P_T3_34 PL_DDR3_RESET IO_L16N_T2_34 PL_DDR3_CLK0_P IO_L21P_T3_DQS_34 PL_DDR3_CLK0_N IO_L21N_T3_DQS_34 PL_DDR3_CKE IO_L24P_T3_34 Part 4: QSPI Flash The AX7350 FPGA development board is equipped with a 256MBit 18 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 19 PS ports need to be configured as the QSPI FLASH interface. Figure 4-1 shows the QSPI Flash in the schematic. QSPI_CS QSPI_SCK QSPI FLASH ZYNQ BANK (W25Q256F) QSPI_D0~QSPI_D3 Figure 4-1: QSPI Flash in the schematic 19 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 20: Part 5：Emmc Flash

    The specific models and related parameters of eMMC FLASH are shown in Table 5-1. Position Model Capacity Factory THGBMFG6C1LBAIL 8G Byte TOSHIBA Table 5-1: eMMC FLASH Specification 20 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 21 PS ports need to be configured as the SD interface. Figure 5-1 shows the eMMC Flash in the schematic. MMC_CCLK MMC_CMD eMMC ZYNQ BANK (THGBMFG6C1 LBAIL) MMC_DAT0~MMC_DAT3 Figure 5-1: eMMC Flash in the Schematic Figure 5-2: eMMC Flash on the AX7350 FPGA Board 21 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 22: Part 6: Clock Configuration

    X4 crystal on the development board. The input of the clock is connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic diagram is shown in Figure 6-1: Figure 6-1: Active crystal oscillator to the PS section 22 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 23 (MRCC) of the FPGA BANK35, which can be used to drive user logic circuit within the FPGA. The schematic diagram of the clock source is shown in Figure 6-3. Figure 6-3: PL system clock source 23 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 24 GTX transceiver; the fourth reference clock is provided to the PCIE slot, to provide a reference clock for AX7350 FPGA board as a PCIE master. The schematic diagram of the Si5338 circuit design is shown below: 24 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 25 BANK CLK0A ZYNQ CLK0B CLOCK PCIE_CLK0_P/N (SI5338P) 50Mhz BANK CLK1A CLK1B SFP_CLK0_P/N BANK CLK2A CLK2B CLK3A CLK3B PCIE PCIE_REFCLK_P/N 插槽 Figure 6-5: Programmable Clock Source Figure 6-6: Programmable Clock Source on the AX7350 Board 25 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 26: Part 7: Usb To Serial Port

    The schematic diagram of the USB Uart circuit design is shown in Figure 7-1: UART_TXD VBUS BANK ZYNQ UART-USB REGIN UART_RXD (CP2102-GM) D+/- Micro USB Figure 7-1: USB to serial port schematic 26 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 27: Part 8: Gigabit Ethernet Interface

    PS side is connected to the GPIO interface of the PSNK501 of the PS side of ZYNQ. The Ethernet PHY chip on the PL side is connected to the IO of the BANK35. The KSZ9031RNX chip supports 10/100/1000 Mbps network 27 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 28 Figure 8-1 detailed the connection of the ZYNQ PS end 1 way Ethernet PHY chip, and Figure 8-2 detailed the connection of the 1 way Ethernet PHY chip on the ZYNQ PL side: 28 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 29 Figure 8-1: The connection of the ZYNQ PS end and GPHY chip PHY2_TXCK PHY2_TXCTL PHY2_TXD0~PHY2_TXD3 PHY2_RXCK ZYNQ GPHY BANK PHY2_RXCTL (KSZ9031RNX) PHY2_TXD0~PHY2_RXD3 PHY2_MDC PHY2_MDIO PHY2_RESET Figure 8-2: The connection of the ZYNQ PL end and GPHY chip 29 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 30 Receive data Bit2 PHY1_RXD3 PS_MIO26_501 Receive data Bit3 PHY1_RXCTL PS_MIO27_501 Receive data valid signal PHY1_MDC PS_MIO52_501 MDIO Management clock PHY1_MDIO PS_MIO53_501 MDIO Management data PHY1_RESET PS_MIO7_500 Reset signal PL-side Gigabit Ethernet pin assignments are as follows： 30 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 31: Part 9: Usb2.0 Host Interface

    The four USB ports are flat USB ports (USB Type A), which allows users to connect different USB Slave peripherals (such as USB mouse and USB keyboard) at the same time. Each USB interface provides +5V power. 31 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 32 Figure 9-1: The connection between Zynq7000 and USB chip Figure 9-2 shows the physical diagram of the USB 2.0 chip and interface, where the USB interface uses a dual USB interface. Figure 9-2: The USB2.0 on the AX7350 Board 32 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 33: Part 10: Hdmi Output Interface

    I2C configuration interface are connected with the BANK35 IO of the ZYNQ7000 PL part. The ZYNQ7000 system initializes and controls the ADV7511 through the I2C pin. The hardware connection diagram of ADV7511 chip and ZYNQ7000 is shown in Figure 10-1. 33 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 34 ZYNQ Pin Name ZYNQ Pin Description Number HDMI_CLK IO_L8P_T1_AD10P_35 HDMI Video signal clock HDMI_HSYNC IO_L23P_T3_35 HDMI Video signal line synchronization HDMI_VSYNC IO_L22N_T3_AD7N_35 HDMI Video signal column synchronization HDMI_DE IO_L9P_T1_DQS_AD3P_35 HDMI video signal is valid 34 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 35: Part 11: Sfp Interface

    The AX7350 FPGA development board has two optical interfaces. Users can purchase SFP optical modules (1.25G, 2.5G, 10G optical modules on the market) and insert them into these two optical interfaces for optical data 35 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 36 ZYNQ SFP2 SFP2_RX_P SFP2_RX_N BANK111 SFP2_TX_P SFP2_TX_N BANK SFP2_TX_DIS_LS LEVEL SFP2_TX_DIS SFP2_LOSS SFP2_LOSS SHIFT Figure 11-1: The schematic diagram of FPGA and Fiber Interface Figure 11-2: The 2-Port Fiber Interface on the AX7350 Board 36 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 37: Part 12: Pcie Slot

    RX signals are connected to the BANK112 by differential signals, and the single-channel communication rate can be up to 5G bit bandwidth. The reference clock of the PCIe slot is provided by the clock chip SI5338P with a 37 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 38 SHIFT SI5338P Figure 12-1: PCIe slot design schematic Figure 12-2: PCIe x8 Slot on the AX7350 Board PCIe x2 Interface Pin Assignment： Signal Name FPGA Pin Description PCIE_RX0_P PCIE Channel 0 Data Receive Positive 38 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 39: Part 13: Sd Card Slot

    BANK501 of ZYNQ. Since the VCCMIO of the BANK is set to 1.8V, but the data level of the SD card is 3.3V, connected through the TXS02612 level shifter. The schematic of the Zynq7000 PS and SD card connector is shown in Figure 13-1: 39 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 40 Description Number SD_CLK PS_MIO40 SD Clock Signal SD_CMD PS_MIO41 SD Command Signal SD_D0 PS_MIO42 SD Data0 SD_D1 PS_MIO43 SD Data1 SD_D2 PS_MIO44 SD Data2 SD_D3 PS_MIO45 SD Data3 SD_CD PS_MIO10 SD Card Insertion Signal 40 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 41: Part 14: Fmc Connector

    The AX7350 FPGA development board has a standard FMC LPC expansion port that can be connected to various FMC modules of XILINX or ALINX (HDMI input and output modules, binocular camera modules, high-speed AD modules, etc.). The FMC expansion port contains 34 pairs of differential IO signals and one high-speed GTX transceiver signal.
  • Page 42 FMC reference 0th channel data FMC_LA00_CC_N IO_L13N_T2_MRCC_12 AD14 (clock)N FMC reference 1st channel data FMC_LA01_CC_P IO_L14P_T2_SRCC_12 AB15 (clock) P FMC reference 1st channel data FMC_LA01_CC_N IO_L14N_T2_SRCC_12 AB14 (clock) N FMC_LA02_P IO_L3P_T0_DQS_12 FMC reference 2nd channel data P 42 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 43 FMC reference 17th channel data FMC_LA17_CC_P IO_L12P_T1_MRCC_13 AC23 (clock) P FMC reference 17th channel data FMC_LA17_CC_N IO_L12N_T1_MRCC_13 AC24 (clock) N FMC reference 18th channel data FMC_LA18_CC_P IO_L11P_T1_SRCC_13 AD23 (clock) P FMC_LA18_CC_N IO_L11N_T1_SRCC_13 AD24 FMC reference 18th channel data 43 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 44 FMC reference 31st channel data N FMC reference 32nd channel data FMC_LA32_P IO_L2P_T0_13 AB26 FMC reference 32nd channel data FMC_LA32_N IO_L2N_T0_13 AC26 FMC_LA33_P IO_L1P_T0_13 AA25 FMC reference 33rd data P FMC_LA33_N IO_L1N_T0_13 AB25 FMC reference 33rd data N 44 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 45: Part 15: Led Light

    LED light hardware connection diagram 3.3V 3.3V 3.3V 3.3V 3.3V PS_LED LED2 LED1 LED3 LED4 BANK ZYNQ BANK Figure 15-1: The User LEDs Hardware Connection Diagram Figure 15-2: The User LEDs on the AX7350 FPGA Board 45 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 46: Part 16: Reset Button And User Button

    The connection between the reset button and the user button is shown in Figure 16-1. RESET 复位芯片 PS_POR_B (TCM811) BANK PS KEY PS_KEY ZYNQ PL KEY1 PL_KEY1 PL KEY2 PL_KEY2 BANK PL KEY3 PL_KEY3 PL KEY4 PL_KEY4 Figure 16-1: Buttons Connection Diagram 46 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 47: Part17: Jtag Debug Port

    With a USB cable, you can develop and debug ZYNQ. On the AX7350 FPGA development board, a FTDI USB bridge chip FT232HL is used to realize USB of PC and JTAG debug signals TCK, TDO, TMS, TDI of ZYNQ for data communication. 47 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 48: Part 18: Dip Switch Configuration

    ZYNQ system's startup mode. The AX7350 system development platform supports three boot modes. The three boot modes are JTAG debug mode, QSPI FLASH and SD card boot mode. After the XC7Z035 chip is 48 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 49: Part 19: Power Supply

    LDO chip SPX3819-1-8. The VTT and VREF voltages of the DDR3 of the PS section and the PL section are generated by U6, U9. The schematic diagram of the power supply design on the AX7350 FPGA development board is shown in Figure 19-1 49 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 50 ZYNQ Bank0,Bank500， QSIP FLASH, Clock Crystal, SD Card， +3.3V SFP optical module +1.5V DDR3, ZYNQ Bank501, Bank33,Bank34, +1.2V Gigabit Ethernet VADJ(+2.5V) ZYNQ Bank12, Bank13, FMC VREF, VTT（+0.75V） PS DDR3，PL DDR3 MGTAVCC(+1.0V) ZYNQ Bank111, Bank112 MGTAVTT(+1.2V) ZYNQ Bank111, Bank112 50 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 51: Part 20: Fan

    Because ZYNQ035 generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating. The control of the fan is controlled by the ZYNQ chip. The control 51 / 53 Amazon Store: https://www.amazon.com/alinx...
  • Page 52 The power of the fan is connected to the socket of J22. The red is positive and the black is negative. Figure 20-2 shows the physical diagram of the fan on AX7350 FPGA development board. Figure 20-2: Fan on the AX7350 board 52 / 53 Amazon Store: https://www.amazon.com/alinx...

  • Page 53: Part 21: Dimensional Structure

    ZYNQ FPGA Development Board AX7350 User Manual Part 21: Dimensional structure Figure 21-1: Top View 53 / 53 Amazon Store: https://www.amazon.com/alinx...

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