Alinx ZYNQ UltraScale+ User Manual page 41

DisplayPort V1.2a output standard, up to 4K x 2K@30Fps output, supports
Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video formats, each color
supports 6, 8, 10, or 12 bits.
The DisplayPort data transmission channel is directly driven and output by
the BANK505 PS MGT of ZU9EG, and the LANE2 and LANE3 TX signals of
MGT are connected to the DP connector in a differential signal mode. The
DisplayPort auxiliary channel is connected to the MIO pin of the PS. The
schematic diagram of the DP output interface design is shown in Figure 3-3-1:
The DisplayPort interface ZYNQ pin assignment is as follows:
Signal Name
GT0_DP_TX_P
GT0_DP_TX_N
GT1_DP_TX_P
GT1_DP_TX_N
505_DP_CLKP
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
Figure 3-3-1: DP interface design Schematic
ZYNQ Pin Number
505_TX3_P
505_TX3_N
505_TX2_P
505_TX2_N
505_CLK2_P
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ZYNQ Pin Number Description
Low bits of DP Data
V29
Transmit Positive
Low bits of DP Data
V30
Transmit Negative
High bits of DP Data
W31
Transmit Positive
High bits of DP Data
W32
Transmit Negative
DP Reference Clock
U27
Positive