Part 3.3: Dp Interface - Alinx ZYNQ UltraScale+ User Manual

The PCIE signal is directly connected to the BANK505 PS MGT
transceiver of ZU9EG, and the TX signal and RX signal of one channel are
connected to the LANE1 of MGT in a differential signal mode. The PCIE clock
is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic
diagram of the M.2 circuit design is shown in Figure 3-2-1:
The pin assignment of M.2 interface ZYNQ is as follows:
Signal Name
PCIE_TX_P
PCIE _TX_N
PCIE _RX_P
PCIE _RX_N
505_PCIE_REFCLK_P
505_PCIE_REFCLK_N
PCIE_RSTn_MIO37

Part 3.3: DP Interface

The AXU15EG FPGA development board has a standard DisplayPort
output display interface for video image display. The interface supports VESA
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
Figure 3-2-1: M.2 Interface Schematic
Pin Name
505_TX0_P
505_TX0_N
505_RX0_P
505_RX0_N
505_CLK0_P
505_CLK0_N
PS_MIO37
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Pin Number Description
AB29 PCIE Data Transmit Positive
AB30 PCIE Data Transmit Negative
AB33 PCIE Data Receive Positive
AB34 PCIE Data Receive Negative
AA27 PCIE Reference Clock Positive
AA28 PCIE Reference Clock Negative
N22 PCIE Reset Signal